Low Power Programmable Frequency Divider for IEEE 802.15.4a

Standard

Denys Martynenko, Gunter Fischer, Oleksiy Klymenko

IHP, Frankfurt (Oder), 1m Technologiepark 25, Germany

Abstract - This paper presents a frequency divider with a programmable division ratio between 208 and 320 intended for the standard IEEE 802.15.4a. The divider is based on high speed, low power, triple modulus prescalers. The wide division range is achieved by cascading these programmable prescalers. Each prescaler includes a phase selector and an ECL D-flip-flop which acts as a divider by 2. The triple operation of the prescaler is achieved by switching between different output phases of the D-flip-flop in the positive direction from 00 to 2700 and to the negative direction from 270° to 0°. In addition, a clock of 499.2 MHz with 50% duty cycle is available independent of the selected communication channel. The proposed divider has been evaluated for a SiGe BiCMOS technology and a maximum simulated input frequency of at least 13.5 GHz has been achieved.

Index Terms - Low power programmable frequency divider, prescaler, analog multiplexer.

I. INTRODUCTION

The commercial interest in short-range wireless

communication systems has strongly increased in the last

years. These systems become important due to their

relation with the future vision of achieving a ubiquitous

communication. Recently introduced UWB technology

shows a potential to fulfill technical and economical

requirements and to provide necessary services for such a

vision [I]. The IEEE 802.15.4a standard has been

developed based on the UWB technology. This standard

provides the physical layer for ultra-low complexity, ultra­

low power, and ultra-low cost UWB devices [2].

The direct conversion front-end architecture is often

chosen as a good candidate for implementing the impulse

radio system in accordance with the IEEE 802.15.4a

standard due to its robustness and flexibility. The

frequency synthesizer (FS) is a basic building block of

many direct conversion UWB transceiver architectures. It

provides the center frequencies for 11 channels (low and

high UWB bands) and 499.2 MHz clocks for the IEEE

802.15.4a standard transceiver. Since a clock of 499.2

MHz has to be provided for all communication channels,

the multi modulus division has to be done at the high

frequency domain and the fixed division has to be moved

into the low frequency domain. All this makes the low

power design of the programmable frequency divider very

challenging.

978-1-4577-0516-8/11/$26.00 ©2011 IEEE

Several programmable high frequency dividers have

been already presented in the literature. For instance, in [3]

and [4] the authors proposed a programmable high

frequency divider architecture which is based on dual

modulus prescalers. Each of them has the same circuit

implementation, and the power dissipation of the dual

modulus prescaler is scalable with its input frequency.

However, each prescaler consists of four D latches and

additional logic and foresees the synchronous operation.

This increases the complexity of the design and raises the

overall divider power dissipation. Another solution, which

improves the power dissipation and speed of the divider, is

presented in [5] and [6]. The authors utilized a

programmable divider architecture which is based on the

fast dual-modulus prescaler. The proposed dual-modulus

prescaler uses a technique which enables the limitation of

its high-speed section to only one divide by two flip-flop.

Moreover, the control of the prescaler modes is shifted

into the low frequency domain and correspondently, the

power dissipation of the complete divider is strongly

decreased. Unfortunately, in those divider architectures,

the multi-modulus division operation is shifted in the low

frequency domain and high frequency clock of 499.2 MHz

could not be generated for each of the channels as it is

foreseen by the standard.

In this paper a low power programmable divider

architecture which provides 11 division ratios and 499.2

MHz clock for all communication channels of the IEEE

802.l5.4a standard is presented.

II. PROGRAMMABLE DIVIDER ARCHITECTURE

The block diagram of the proposed programmable

frequency divider is shown in Fig. l. The architecture

consists of high-speed EeL divide by two stages and phase

selectors (high frequency parts), ECL to CMOS converter,

CMOS divide by two stages and multi modulus CMOS

control logic (low frequency part). In order to achieve a

clock of 499.2 MHz for each of the communication

channels (IEEE 802.15.4a), the multi modulus high

frequency part of the divider is designed as a cascade of

the fast triple modulus prescalers and provides the division

range from l3 to 20. Further division is applied in the low

frequency domain with a single modulus divider by 16.

:== __ =-__ = __ =_-.HighTrequency part ---- 1 Low frequency part

I

L

I I I I I I I I I I I I I I

I I I I I : Prescaler : L _____ __________________ 1

Figure I. The block diagram of the programmable divider

D+ 1+ F+ D· I. F· MIS Q

�� Q-

F+/2 F·/2

D+ 1+ � Ph. D+ 1+ D· I. F 1 /4 , sel D· I. MIS Q ::;; F/4 5 MIS Q

• • •

�� Q _ FQ/4 .Ii �� Q_

-0 -0

Control si nal

Control F+/N

block F·/N

Figure 2. The block diagram of the conventional dual­

modulus prescaler architecture

Figure 3. The principle of the N+ I operation above, and

N-l operation below

A. ECL divide by two stage and phase selector

The IEEE 802.15.4a standard foresees the

communication frequency range between 3.1 GHz and

10.6 GHz. The communication frequency range consists of

high and low UWB frequency bands, which are divided

into 11 channels. Additionally, the standard requires an

internal clock of 499.2 MHz for each of the channels.

The frequency divider is designed for 0.25 �m BiCMOS

process of IHP [7]. The CMOS part of the process allows

building the digital circuits with a clock slightly higher

than l.0 GHz. Therefore, the first four dividers by two are

499.2 MHz

I

__ __ __ __ __ --.J __

implemented with the high-speed bipolar Emitter Coupled

Logic (ECL). The ECL divide by two stage uses the

conventional master-slave architecture. This architecture is

intensively discussed in the literature [4]-[5] and will not

be described in this paper in detail.

The phase selector consists of four differential

amplifiers with switchable current sources. Each input of

the amplifiers is connected to one of the four outputs of

the ECL divider by two, as it is shown in Fig. 2.

B. Conventional and exploited NIN±l prescalers

The conventional NIN+ 1 prescaler is shown in Fig. 2.

The prescaler realization is similar to the described in [5].

The differential input signal (F+, F-) is fed in to the first

ECL divider by 2 which is connected in the master/slave

configuration. The resulting signal is ones again divided

by 2. The second divider provides, at the output, signals as

follows: differential signal of the master (1+, 1-) and

differential signal of the slave (Q+, Q-). When the control

signal is constant, the phase selector is in the passive mode

and one of the two differential signals bypasses the phase

selector and goes straight into the next ECL divider by

two. As a result, the prescaler divides the input frequency

(F) by 4. When the control signal changes its state, the

phase selector joins the actual signal F(I)/4 with 90°

delayed signal F(Q)/4. In other words, the signal with the

duration of 4*To will increase by To. Correspondently, the

period of the signal at the prescaler output will increase by

To (Fig. 3). As a result, the prescaler divides the input

frequency by 5, ones per control signal period.

The principle of the prescaler has been further exploited

in this work in order to achieve N -1 operation mode,

without introducing any additional high-speed circuitry.

The difference between the N+l and N-l operation modes

lies in the different method of phase selection. Instead of

rotating the phase in positive direction from 0° to 270°, the

phase is rotated in negative direction from 270° to 0°. In

this case, the F/4 signal will be delayed by -90°. In other

words, the signal with the duration of 4*T 0 will decrease

by To. Correspondently, the period of the signal at the prescaler output will decrease by To (Fig. 3). As a result, the prescaler divides the input frequency by 3, ones per control signal period.

,oo,� :: § � §�B�� After the shift

registers

After the control

impulses former

After the control

impulses distributor

2 shift Control 3 control registers

Figure 4. The generation of the control impulses.

C. High frequency part of the programmable divider

The divider has to provide 11 division ratios and a clock of 499.2 MHz for all communication channels in order to satisfy the requirements of the IEEE 802.15.4a standard. As it was already mentioned, the multi modulus division is shifted into the high frequency domain and provided by the high frequency divider part. The programmable division range is realized as a cascade of the triple modulus prescalers. Indeed, the placement of the prescalers one after another allows obtaining control over multiple division ratios such as NIN±I, NIN±2, NIN±4 and so on, with respect to the input frequency (F). The cascade of mentioned prescalers provides the division range between:

• minimum division ratio 2n+2 - (2n -1) • maximum division ratio 2ll+2 + (2ll -I)

where n is number of the prescalers (phase selector and the ECL divider). Unfortunately, with the divider architecture which foresees implementing minimum two dividers by two in front of the first prescaler, it is not possible to achieve the clock of the 499.2 MHz for all communication channels, as it is required by the standard. Therefore, in the proposed architecture, the first prescaler is placed after the first divider by two (Fig. 1). However, in order to provide the NIN±1 modes in this configuration,

the phase rotation in the phase selector has to be done twice per 499.2 MHz period. New divider architecture allows achieving the division ratios 2/2± 1 already after the first prescaler, the division ratios 4/4±2 after the second prescaler and so on. In this case, the cascade of the NIN±1 prescalers allows the division range between:

• minimum division ratio 2ll+1 _ (2n_l) • maximum division ratio 2n+1+ (2n_l)

The new high frequency part includes three prescalers and one ECL divider by two. This provides the division ratio from 9 to 23 with the step size of 1 and a clock of 499.2 MHz for each communication channel of the IEEE 802.15.4a standard. Another important advantage of this approach is the assurance of the clock of 499.2 MHz with 50% duty cycle. The control of triple modulus prescalers requires the design of a sophisticated control block. Nevertheless, all requirements of the IEEE 802.15.4a standards concerning the divider will be satisfied.

Additionally, the optimum configuration of the division ratios of the prescalers is improving the power dissipation of the complete divider chain. For example, the divide by 23 configuration is the most relaxed one with respect to the speed of the prescalers, because the frequency is decreased at least twice from stage to stage. The divide by 9 configuration is the most difficult one concerning the speed of the prescalers, because all prescalers operate in the N -1 mode and the first prescaler has to operate with the same speed as the first divider by two, at least ones per control signal period. However, the IEEE standard requires the division ratios between 13 and 20 and these division ratios could be achieved by different ways. For instance, the division ratio 13 could be obtained as 16-2-1 or as 16-4+l. The second configuration is much more beneficial from the power dissipation point of view, because it does not require the operation of the first prescaler in the N-I mode. Therefore, the power consumption of the first prescaler can be reduced 35% -40% with respect to the first divider by two without performance degradation of the complete divider chain. Similar combinations for the rest of the division ratios can be found without using the first prescaler in N-l operation mode.

D. Pre scalers control block

The place of the prescalers control block in the divider chain is very critical. The control block has to provide control impulses twice per 1/499.2 MHz for each of the phase selector individually. Moreover, the power dissipation of the control block has to be low. In the presented architecture, the control block is placed in the divider chain, after the ECL to CMOS converter and

designed with low power CMOS logic. The core of the

control block consists of two shift registers which are

clocked by the different phases of the 499.2 MHz input

signal (0° and IS00). Each of the shift register provides

four impulses with the duration of 2ns. The former block

processes those impulses and forms eight control impulses

with the duration of Ins in order to rotate the phase in the

phase selector twice per 499.2 MHz.

Additionally, the control block includes the start up

circuit and three control impulses distributors, one per

phase selector. The start up circuit insures that the

complete divider chain starts to operate before the first

phase rotation event happens. The distributors provide the

control impulses to the phase selectors. It is important to

mention that the control impulses have to be completely

overlap each other; otherwise the proper operation of the

phase selector will be not possible. For this reason, the

raising edge of the control impulse has to be sharp and the

falling edge has to be smooth. The generation of the

control impulses is shown in Fig. 4.

E. Low frequency divider chain

The low frequency divider chain consists of four CMOS

divide by two cells. They are implemented in order to

divide 499.2 MHz down to 31.2 MHz. Frequency of 31.2

MHz is recommended by the IEEE S02.15.4a standard as

a reference frequency for the complete system. The CMOS

divider by two is designed as dynamic CMOS D flip-flop

similar to [5].

III. SIMULATION RESULTS

The programmable frequency divider is designed using

0.25 11m BiCMOS SiGe technology of IHP. The

simulation has been done for the worst case corners and

with the temperature of 125° C. All required division ratios

between 20S and 320 with the step size of 16 are obtained.

The divider chain provides a clock of 499.2 MHz with

50% duty cycle for all communication channels of the

IEEE S02.15.4a standard. The maximum simulated input

frequency for minimum possible division ratio (the most

stringent condition) results in l3.5 GHz. The main input

frequency limitation factor is the speed of the CMOS

control block. The speed of the control block seems to be

problematic to improve due to the technological limitation

of the CMOS devices. The performance of the

programmable divider chain is summarized in table I.

Table I The performance of the programmable frequency

divider

Input frequency range 6.0 GHz .. I 0.6 GHz

High frequency clock 499.2 MHz

Output frequency 3l.2 MHz

Division ratio 20S .. 320

Step size 16

Supply voltage 2.6V

Current consumption

- high freq uency part 5.06 mA

- control block 1.02 rnA

- ECL to CMOS converter 1.06 rnA

- CMOS divider by 16 0.45 mA

- total 7.59 rnA

VII. CONCLUSION

The programmable frequency divider which provides all

required division ratios and a clock of 499.2 MHz with

50% duty cycle in accordance with the IEEE S02.15.4a

standard has been designed and simulated. This divider is

based on the cascade of the high frequency triple modulus

prescalers. The control of the prescalers is shifted into the

low frequency domain. Therefore, the power consumption

of the complete programmable divider is strongly

decreased without degradation of the speed performance.

REFERENCES

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[2] IEEE Std. S02.15.4a-2007. [3] S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson and

others "A family of low-power truly modular programmable dividers in standard 0.35-/lm CMOS Technology," JSSC, Vol. 35, No.7, July 2000, pp. 1039-1045.

[4] M. Ray, W. Souder, M. Ratcliff, F. Dai and J. D. Irwin "A 13 GHz low power multi-modulus divider implemented in 0.13 /lm SiGe technology," SiRF, Feb. 2009, pp. 1-4.

[5] J. Craninckx and M. S. J. Steyaert, "A 1.75-GHz/3V dual­modulus divide-by-128/129 prescaler in 0.7-/lm CMOS," JSSC, Vol. 31, No.7, July 1996, pp. 890-897.

[6] N. Krishnapura and P. R. Kinget, "A 5.3-GHz programmable diver for HiPerLAN in 0.25-/lm CMOS," JSSC, Vol. 35, No.7, July 2000, pp. 1019-1024.

[7] Foundry Service of IHP,

Available: http://www.ihp-microelectronics.com