103978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Low-Power and Robust 6T SRAM cell using Symmetric Dual-k Spacer FinFETs

Pankaj Kumar Pal, B. K. Kaushik, and S. Dasgupta

Abstract - This paper proposes a dual-k spacer FinFET architecture that shows superior electrostatic integrity over the conventional low-k spacer underlap device and thus suppress SCEs. Furthermore, the proposed dual-k structure explores the possibility of symmetric FinFETs that helps to augment all SRAM design metrics without affecting cell-ratio and pull-up ratio.

I. INTRODUCTION

FinFETs are the most promising and mature technology among all the multi-gate devices. As Intel progresses to use three-dimensional tri-gate (or, FinFET) transistor commercially in the 22 nm technology node, a strong interest has emerged among the semiconductor foundries in forming 14 nm and 10 nm bulk FinFETs [1]. However, there are several challenges that need to be addressed. The two major inherent challenges associated with FinFETs are the increased parasitic (due to its 3D nature) and the fin width quantization that limits its use for high-performance circuit or memory applications. Also, the undoped underlap region is unavoidable in devices with gate length 20 nm or less. It helps in reducing short channel effects (SCEs) but at the expense of drive-current (ION). As the underlap length (Lun) increases, the series resistance (RS/D) starts dominating and hence G-S/D barrier restricts the carriers to flow from source-to-drain, even at high VDS [2]. Introducing high-k spacers can provide strong fringe field coupling between the gate and the underlap region that reduce RS/D [3]. But it also increases the fringe capacitance (Cfr) component of the total gate capacitance (Cgg) that may worsens the circuit performance in terms of delay/access-time.

A 6T SRAM cell has the most critical design considerations in terms of leakage power, access-times and noise margins. The other design concern is the read/write conflict, wherein a transistor sizing to enhance the read-stability degrades the write-ability and vice-versa. Several radical departures from conventional design have been proposed that claimed to mitigate read-write stability conflict. Most of them use independent-gate configurations for threshold (Vth) adjustment and the rest proposed device architectures are asymmetric in nature that enhances

process as well as circuit complexity. The asymmetricity introduces with respect to the source and drain terminal helps in adjusting the pull-up (PR) and cell ratio (CR) but in turn adversely affects the cell-area, leakage power and access-times [4]. Therefore, this paper explores the possibility of symmetric FinFETs that helps to augment all SRAM design metrics without affecting PR and CR.

This research paper is further organized as follows: Section II describes the proposed dual-k spacer FinFET architecture, the physical parameters and the simulation methodology adopted throughout the paper. Also, the brief electrostatics and the merits of the proposed dual-k structure over the conventional low-k spacer FinFETs are discussed. Consequently, the SRAM analysis using dual-k structure demonstrates in Section III that helps to improve the noise-margins, access-times and leakage-power. Finally Section VI concludes this paper.

II. DEVICE STRUCTURE

A proposed dual-k spacer FinFET structure is shown

in Fig. 1. It consists of an inner high-k (HfO2, k=25) and an outer low-k (SiO2, k=3.9) spacer material in contrast to the conventional FinFET where single low-k spacer is used. The key process step involved in proposed device is dual-k spacer technology for creating a symmetric underlap region at the source/drain. All the physical dimensions are calibrated to meet the specification of ITRS that are summarized in Table 1 [5]. The inner high-k spacer length (Lhk), outer low-k spacer length (Llk) and underlap length (Lun) are optimized to 12 nm, 8 nm and 8 nm, respectively. The work-function of metal-gate is tuned to achieve a requisite threshold voltage of ~220 mV.

Fig. 1. Cross-sectional view of the proposed dual-k underlap FinFET structure.

P. K. Pal, B. K. Kaushik, and S. Dasgupta are with the Microelectronics & VLSI Group, Department of Electronics & Communication Engineering, Indian Institute of Technology-Roorkee, Roorkee, Uttarakhand-247667, India. E-mail: pankajpal86@gmail.com

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TABLE I ITRS PROJECTIONS FOR HIGH PERFORMANCE DEVICE

Device Parameters ITRS Value

Physical Gate Length (LG) 14 nm Eq. Oxide Thickness (EOT) 0.72 nm

Fin Thickness (TSi) 9.4 nm Supply Voltage (VDD) 0.75 V Channel Doping (NA) Intrinsic

Source/Drain Doping (ND) 1×1020 cm-3 Threshold Voltage (Vtsat) 220 mV

Device and SRAM mixed mode simulations are

carried out using Synopsys TCAD [6]. The quantum potential model is enabled to include the quantum confinement effect of inversion carriers in the thin body and also the direct tunneling model is included to take the gate leakages into account. The Lombardi mobility model has been activated to account mobility degradation at the silicon-insulator interface.

In comparison to conventional low-k FinFET, the proposed dual-k structure displays higher conduction band edge under the gate region in OFF-state (at VGS = 0 V) as observed in Fig. 2, that substantially reduces the sub-threshold leakage current. In ON-state (When VGS = VDD), the increased fringe field produces an accumulation on the underlap region through the inner high-k spacer that evidently lowers the series resistance. Furthermore, the barrier directly under the channel is lowered to a lesser extent by the drain bias in dual-k than in the low-k; hence the electrostatic integrity increases that reduces SCEs. Influence of drain field reduction depends upon the type of inner high-k spacer used. The barrier directly under the gate increases with increasing inner spacer k value and it does not affect the ION unless it is significantly higher than the underlap barrier. Once the carriers cross the G-S underlap barrier, they can be easily transported to the drain end.

Fig. 2. Conduction band energy profile along the channel for low-k and dual-k spacer FinFETs

For dual-k FinFET, the drive current increases 2.41 ×, with a reduction of 75% in subthreshold leakage current as shown in Fig. 3. Moreover, the dual-k structure shows 27.8% improvement in ION/IOFF, with an improved DIBL and sub-threshold swing (SS). The output characteristics of the proposed device compared with the conventional low-k structure is plotted in Fig. 4.

Fig. 3. Device performance comparison between low-k and dual-k spacer underlap FinFET structure.

Fig. 4. Output characteristics of the proposed dual-k FinFETs compared the conventional one.

Fig. 5(a) plots the variation effect of the length of

inner high-k layer on the ION and IOFF. The inner high-k spacer length (Lhk) is varied from gate edge to S/D edge by keeping the Lun fixed. As we keep on increasing the Lhk, there is an optimal point where ION is at peak with a minimum IOFF. Thereafter, if we further increase Lhk towards S/D, ION starts decreasing. Fig. 5(b) clearly depicts the increase in fringe capacitance component with increasing spacer dielectric as function of inner high-k spacer length. The circuit delay depends on the relative rate of change of ION and Cgg [3], therefore the ION/Cgg must be enough high to substantially reduce the delay.

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Fig. 5. Effect of increasing Lhk on (a) ON and OFF-state current, (b) normalized total gate capacitance, and (c) normalized ION/Cgg in dual-k structure for different spacer material as function.

Fig. 5(c) shows the variation of ION/Cgg normalized with the conventional at different k value with increasing Lhk. A maximum ION/Cgg and ION/IOFF are obtained near the S/D-channel junction. Therefore, better performance can be achieved by having an extended Lhk upto 4 nm more than the Lun with Gaussian doping profile.

III. SRAM ANALYSIS

The static noise-margins (SNMs) comparisons with

conventional SRAM in all three possible modes of operations are shown in Fig. 6. The hold, read and write margins are increased by 8.67%, 9.37% and 9.12%, respectively. The read/write stability is not directly dependent on the absolute value of ION [7]. Apparently; SNM has a negative correlation with DIBL [8]. In agreement to this, it is observed that the SNMs are considerably improved using proposed configuration without affecting design ratios (CR and PR).

Fig. 6. Static noise margins (SNMs) improvement in 6T-SRAM cell using dual-k spacer over the conventional low-k FinFET.

A 2.31 × and 1.22 × reductions in read access and write access times, respectively compared to conventional one as depicted in Fig. 7. It is due to the optimal high-k spacer layer increases the ION/Cgg that also helps to reduce delay. Furthermore, the leakage power is reduced by 3.34 ×

without affecting the cell-area as compared with the conventional low-k FinFET based SRAM. Fig. 8 presents the impact of cell-ratio in SNMs of dual-k based SRAM cell with respect to the conventional one. The read SNMs shows large improvement with increase in CR while the hold and write-margin marginally degrades.

Fig. 7. Comparison of read/write access time and cell leakage power using dual-k FinFETs over the conventional one.

Fig. 8. Impact of cell-ratios on SNMs in dual-k based SRAM cell with respect to the conventional one.

Supply voltage (VDD) reduction generally lowers the leakages, limited by a tolerable noise immunity. Therefore, VDD scalability on SRAM design metrics is also explored.

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Fig. 9. Comparison of (a) hold SNM, (b) read SNM, and (c) write SNM between low-k and dual-k FinFET as function of VDD.

Fig. 9-10 presents the effect of lowering the VDD on

hold, read, write-margin and write-access time respectively. Compared to conventional, dual-k FinFET based SRAM configuration shows 0.9-9.2% improvement in hold SNM and 3.6-21.7% in read stability for supply voltage ranging from 0.3-0.9 V. Moreover, the write-margin enhances up to 10.6% and write access time reduces by 19.4%. It is observed that the dual-k FinFET based SRAM performs better in super-threshold region and shows significant improvement with higher VDD. However, the proposed configurations are not viable candidates in sub-threshold region. The percentage improvement metrics decreases with scaling down of supply voltage. This is due to reduction in gate fringe coupling through inner high-k spacer that increases series resistance with reduced VDD.

Fig. 10. Write-access time comparison with VDD.

IV. CONCLUSION

This paper presented the merits and brief electrostatics associated with the proposed dual-k spacer FinFET architecture. The dual-k architecture exhibits excellent electrostatic integrity over channel that improves device performance and SRAM design metrics. Current

characteristics and short channel metrics of the proposed device are presented and compared with conventional single/low-k FinFET structures. The proposed configurations yields a large reduction in leakage power, improved noise margins and reduced access time without affecting cell area. Therefore, it can be concluded that the proposed dual-k FinFET structure exhibits excellent electrostatic integrity over channel that improves the digital performance and SRAM design metrics.

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