978-1-4244-4547-9/09/$26.00 ©2009 IEEE TENCON 2009

A New Design For Four Switch Three Phase Inverter Based On FPGA For Induction Motor Control

Hong Hee Lee

School of Electrical Engineering, University of Ulsan, Ulsan, Korea hhlee@mail.ulsan.ac.kr

Phan Quoc Dzung Faculty of Electrical & Electronic Engineering HCMC University of

Technology Ho Chi Minh City, Vietnam

pqdung@hcmut.edu.vn

Le Minh Phuong Faculty of Electrical & Electronic Engineering HCMC University of

Technology Ho Chi Minh City, Vietnam

lmphuong@hcmut.edu.vn

Le Dinh Khoa Faculty of Electrical & Electronic Engineering HCMC University of

Technology Ho Chi Minh City, Vietnam khoaledinh@hcmut.edu.vn

Abstract-- This paper presents a realization of the space-vector

pulse-width modulation (SVPWM) strategy for control system induction motor (IM). In this paper is presented a space vector PWM algorithm for four switch three phase inverters (B4, FSTPI) based on the one for six switch three phase inverters (B6, SSTPI) (principle of similarity) where the αβ plan is divided into 6 sectors and the formation of the required reference voltage space vector is done in the same way as for B6 by using effective (mean) vectors. That has been developed using the ready-to-use field-programmable gate array (FPGA) technology. The programming SVPWM algorithm, deadtime algorithm, and control IM algorithm are described. The proposed SVPWM control scheme can be realized using FPGA (Spartan 3E) from Xilinx, Inc. Experimental results are demonstrated. The interface between PC and FPGA is created by a Visual Basic programming

Index Terms-- Induction motor, FPGA, space-vector PWM, three-phase voltage source inverter, B4 (Four Switch Three Phase Inverter), B6 (Six Switch Three Phase Inverter).

I. INTRODUCTION Nowadays, most AC drives and universal pulse-width

modulation (PWM) inverters in use today adopt microprocessor-based digital control strategy. Variable speed AC Induction motors powered by switching power converters are becoming more and more popular. Switching power converters offer an easy way to regulate both the frequency and magnitude of the voltage and current applied to a motor. The most common principle of this kind is the constant V/f principle which requires that the magnitude and frequency of the voltage applied to the stator of a motor maintain a constant ratio [1]. To easy design control system induction motor and reliable a request about very high witching frequency of power inverters is used the ready-to-use field-programmable gate array [2].

The properties of the algorithm processing, such as capability of performing real parallel calculations combined with solutions’ flexibility, are probably the main reasons for applying the FPGA to many technical domains in Power Electronics [2]. Employing FPGA to realize PWM strategies provides advantages such as rapid prototyping, simple hardware and software design, higher switching frequency, and relieving the computation load of microprocessors.

Fig. 1. Four switch three phase inverter (FSTPI)

To reduce number of power semiconductor devices in a three phase voltage inverter, where there are only 4 switches, were proposed different control methods. One of them is [6], which presents a modified space vector PWM algorithm for four switch three phase inverters (B4, FSTPI) based on the one for six switch three phase inverters.

The paper presents the application of FPGA (Spartan 3E from Xilinx, Inс) to realize the SVPWM technique for B4 inverter (FSTP) modeled on the basis of a B6 by using the principle of similarity and revealing perspective solution for the PWM and control induction motor by V/f principle. The principal control schema is presented in Fig.1.

II. ANALYSIS OF SPACE VOLTAGE VECTORS AND STATOR FLUX According to the scheme in fig.1 the switching status is

represented by binary variables S1 to S4, which are set to “1” when the switch is closed and “0” when open. In addition the switches in one inverter branch are controlled complementary (1 on, 1 off), therefore: S1+S2 = 1 ; S3+S4 = 1 (1)

Phase to common point voltage depends on the turning off signal for the switch:

( ) ( ) ;0;2

12;2

12 03010 =⋅−=⋅−= cdc

bdc

a VVSVVSV (2)

Combinations of switching S1-S4 result in 4 general space vectors 41 VV → (Table 1), components αβ of the voltage vectors are gained from abc voltages by using Clark’s transformation:

1

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

−

−−=⎥

⎦

⎤⎢⎣

⎡

c

b

a

VVV

VV

23

230

21

211

32

β

α (3)

where Va, Vb, Vc : phase voltages on the load (Y connection), defined by:

( )00231

baa VVV −= ; ( )00231

abb VVV −= ; ( )0031

bac VVV +−= (4)

In order to form the required voltage space vector refV , we

can use 3 or 4 vectors in one sampling interval Ts. The constant value 0 (zero) vectors can be formed by dividing t0 (duration of zero vector) among 2 opposite vectors ( 31,VV ) or

( 42 ,VV ) [2, 7]. For three phase induction motors the stator flux linkage

vector can be represented as follows [2, 8]: ( )dttV∫=Ψ (5)

In case the motor is fed from a B4 inverter the flux linkage vector is:

0Ψ+⋅=Ψ nn Vt (6) where n = 1..4 ; tn : duration of Vn.

If the switching algorithms can ensure the best approximation by minimizing the discrepancy between vector loci Ψ and *Ψ , the stator voltage performance will be optimized. Thus the design of the algorithm for PWM samples in the inverter phases based on this rule has a very important role.

TABLE 1 COMBINATIONS OF SWITCHINGS AND VOLTAGE SPACE VECTORS

S1 S3 βα jVVV +=

0 0 3

2

1 3

πjdc eVV−

=

1 0 6

2 3

πjdc e

VV

−=

1 1 3

3 3

πjdc eVV =

0 1 6

5

4 3

πjdc eV

V =

III. THE SVPWM APPROACH FOR B4 INVERTER UNDER DC-LINK VOLTAGE BALANCE CONDITION

SVPWM methods presented in papers [4, 5, 9, 10, 12] are based on the formation of the reference vector on the plan αβ which is divided into four sectors (sector I...IV). The active vectors and their duration in one sampling interval are selected and calculated on the basis of the required Vref location respective for these sectors (Fig.2).

SVPWM method used in this paper is based on the principle of similarity of the one for B6 inverters, where plan αβ is divided into 6 sectors and the formation of Vref is done similarly as for B6 is detailed in paper [6]. This facilitates the calculation for B4 and some issues for B6 can be applied for B4 thanks to this approach.

To simulate 6 non-zero vectors in B6, in this proposed method, beside the two V1 and V3, we use the effective vectors V23M, V34M, V41M and V12M. These vectors are formed as follows:

( ) ( )

( ) ( ) 321121441

32

43340

3223

321;

321

;32

1;32

1

ππ

π

jdc

Mjdc

M

jdc

Mjdc

M

eVVVVeVVVV

eVVVVeVVVV

−=+==+=

=+==+= (7)

To simulate zero vectors of B6, we use the effective V0M:

( );21

310 VVV M += or ( );21

420 VVV M += (8)

The similarity between space vectors of B4 (Fig.2) and B6 (Fig.3) is presented in Fig.4 and Table 2. The basic vectors in each sector used to form the required space vector Vref is presented in Table 3.

Below we will describe the space vector modulation for B4 inverter based on the modulation for B6 with the principle of similarity.

Fig. 2. Sectors used in conventional SVPWM methods for B4

Fig. 3. Basic space vectors in B6 inverter.

Fig. 4. SVPWM method used for B4 on the principle of similarity of B6.

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TABLE 2 VECTORS USED IN THE SPACE VECTOR MODULATION B6 & B4

Sector B6 (VX, VY, VZ) B4 (VX, VY, VZ) I V1, V2, VZ V23M, V3, V0M II V2, V3, VZ V3, V34M, V0M III V3, V4, VZ V34M, V41M, V0M IV V4, V5, VZ V41M, V1, V0M V V5, V6, VZ V1, V12M, V0M VI V6, V1, VZ V12M, V23M, V0M

The space vector modulation in this zone is based on the formation of three voltage vectors in sequence in one sampling interval Ts so that the average output voltage meets the requirement. The calculations of the switching states in B6 and B4 are as follows for ½ Ts [11]:

( )

( )

yxsz

sy

sx

ttTt

MTt

MTt

−−=

=

−=

2/

;sin3

;3/sin3

απ

αππ

(9)

where: tx - duration for vector Vx ty - duration for vector Vy tz - duration for vector Vz M – the index of modulation M = V*/V1sw (V* - amplitude of the required voltage vector, V1sw – peak value of six step voltage).

However in B4 inverter since mean vectors tXYM and zero vectors t0M are formed from the two base vectors the duration of base vectors is equal to ½ as for the above mentioned mean and zero vectors.

In order to ensure the closest following and the minimized discrepancy between Ψ and *Ψ loci, the approach shall be done in a symmetrical way from both sides.

It can be used, for example, the effective vectors V23M, V3, V0M for sector I, where V23M, V0M are defined as (12):

( ) ( )

2;

2;

2;

2

;2/

;sin3;3/sin3

01

03

233

232

323

323

fz

fz

fm

fm

ffsofz

sfysfx

tt

tt

tt

tt

ttTtt

MTttMTtt

====

−−==

==−== απ

αππ (10)

Thus the total durations for base vectors V1, V2, V3 are: zmfVmVzV tttttttt 33332211 ;; ++=== (11)

Similarly we can calculate the space vector modulation for the other sectors. The calculation results are shown in Table 3. Pulse patterns for switching in the used method is shown in Fig.5.

a) For sectors I, V, VI

b) For sectors II, III, IV

Fig.5. Pulse patterns for switching in the used method

TABLE 3 VECTOR DURATIONS IN THE USED SVPWM METHOD

Sector I Sector II

( )

( )

2;

2

;2

;2

;2/

;sin3

;3/sin3

01

03

233

232

323

3

23

fz

fz

fm

fm

ffsofz

sfy

sfx

tt

tt

tt

tt

ttTtt

MTtt

MTtt

==

==

−−==

==

−==

απ

αππ

( )

( )

2;

2

;2

;2

;2/

;sin3

;3/sin3

01

03

344

343

343

34

3

fz

fz

fm

fm

ffsofz

sfy

sfx

tt

tt

tt

tt

ttTtt

MTtt

MTtt

==

==

−−==

==

−==

απ

αππ

⇒

zmfV

mV

zV

tttttttt

3333

22

11

++===

⇒

zmfV

mV

zV

tttttttt

3333

44

11

++===

Sector III Sector IV

( )

( )

2;

2

;2

;22

;2

;2/

;sin3

;3/sin3

01

03

411

41344

343

4134

41

34

fz

fz

fm

ffm

fm

ffsofz

sfy

sfx

tt

tt

tt

ttt

tt

ttTtt

MTtt

MTtt

==

=

+==

−−==

==

−==

απ

αππ

( )

( )

2;

2

;2

;2

;2/

;sin3

;3/sin3

01

03

411

414

141

1

41

fz

fz

fm

fm

ffsofz

sfy

sfx

tt

tt

tt

tt

ttTtt

MTtt

MTtt

==

==

−−==

==

−==

απ

αππ

⇒

zmV

mV

zmV

ttttt

ttt

333

44

111

+==

+= ⇒

zV

mV

zmfV

tttt

tttt

33

44

1111

==

++=

Sector V Sector VI

( )

( )

2;

2

;2

;2

;2/

;sin3

;3/sin3

01

03

122

121

121

12

1

fz

fz

fm

fm

ffsofz

sfy

sfx

tt

tt

tt

tt

ttTtt

MTtt

MTtt

==

==

−−==

==

−==

απ

αππ

( )

( )

2;

2

2

;22

;2

;2/

;sin3

;3/sin3

01

03

233

23122

121

2312

23

12

fz

fz

fm

ffm

fm

ffsofz

sfy

sfx

tt

tt

tt

ttt

tt

ttTtt

MTtt

MTtt

==

=

+==

−−==

==

−==

απ

αππ

⇒

zV

mV

zmfV

tttt

tttt

33

22

1111

==

++= ⇒

zmV

mV

zmV

ttttt

ttt

333

22

111

+==

+=

IV. SIMULATION OF THE PROPOSED SVPWM FOR B4 Matlab/ Simulink is used for the simulation of the proposed

SVPWM for the undermodulation, overmodulation mode 1 and 2. DC voltage Vdc = 600V. Output voltage fundamental harmonic f = 50Hz. Switching frequency fsw = 4.8 kHz. The

3

Fig. 7. Phase voltage waveform (M=0.7).

Fig. 8. Line voltage waveform (M=0.7)

Fig. 9. Trajectory of flux space vector (M=0.7)

phase voltage, line voltage waveforms and trajectory of flux space vector are shown in Fig. 7-9 respectively (for M=0.7).

V. HARDWARE IMPLEMENTATION USING FPGA

A. THE PROGRAMMING ALGORITHMS. In this section is presented programming algorithms in

VHDL, where load voltage’s frequency is setting by externally 4-bit data input, the magnitude modulator is getting from control principle V/f=const. An external main clock was used as the clocking signal for the FPGA due to frequency of carrier signal used in this work. A ten bit up-down counter is clocked at 50 MHz to produce a carrier frequency at 31kHz

The Theta and sectors can be obtained from multiplication of the modulating signal from the look-up table (ROM) with an external basic frequency input. The algorithm of sin/cos generator & calculation THETA. Finally, the PWM gating signals are inserted with adjustable time delay to protect the

phase legs from short circuiting. The algorithm of deadtime definition is described follow. The value of deadtime is called TD and pulse of the main clock

66 10.50.)(

10.501

DD T

TT

countersT ==⇒= (12)

The interval 2Ts is divided in 8 small intervals, as shown in figure 8. Where for top switches: W1, W2, W3, W4, W5, W6 are calculated same odd sectors (I, III, V) and same for even sectors (II, IV, VI) by replaced W3 = W7; W4 = W8. The full algorithm definition deadtime is presented in fig 10.

Where in sectors I, V, VI

W1 = T1 W5 = W1 + TD W2 = Ts – W1 W6 = W2 - TD W3 = T1 + T2 W7 = W3 + TD W4 = Ts – W3 W8 = W4 – TD

And in sectors II, III, IV

W1 = T1 + T4 W5 = W1 + TD W2 = Ts – W1 W6 = W2 - TD W3 = T1 W7 = W3 + TD W4 = Ts – W3 W8 = W4 – TD

B. HARDWARE DESIGN To realize the proposed SVPWM scheme, cost

considerations led to selecting an SRAM-based FPGA Spartan 3E XC3S500E from Xilinx, Inc. for implementing of the SVPWM. Xilinx also provides ISE 8.2i tools for the development of ASIC’s employing FPGA’s. The simplicity in the interface circuit design illustrates its feasibility for practical applications. The functional block diagram of control algorithm developed for implementation of Xilinx to produce switching pattern for SVPWM power inverter is shown in Fig.11, which depicts the block diagram of a proposed programmable FPGA-based SVPWM.

Fig. 10. The deadtime diagram

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Fig.11 Block diagram of B4 Power circuit

Fig.12 Functional block diagram of the programmable FPGA- SVPWM

Power Circuit is constructed using 4 IGBTs FGL60N100BNTD from Fairchild Semiconductor with rating voltage 1000V, current 60A. The Isolation and Driver Block is designed from Gate Drive Optocoupler HCPL 3120 with a maximum switching speed 500ns. The load used in this case is represented by resistive (R=20 Ω) and inductive (R=20 Ω and L=75mH). The DC link voltage was adjusted at 100V-200V, and the split capacitors are rated at 1000μF

VI. EXPERIMENTS ON THE PROPOSED SVPWM FOR B4 To observe experimental results Tektronic Oscilloscope

200MHz, 4 channels is used. 1. Case study 1: The fundamental harmonic of output voltages is 50Hz with PWM frequency 5.5 kHz. Fig. 13-16 show the phase voltages ; line voltages waveforms of Vab, and harmonic of a phase load current ia.

Fig.13 Phase load voltages Fig.14 Line load voltage

Fig.15 The harmonic spectrum

of line voltage Fig.16 Phase load current

Case study 2: The fundamental harmonic of output voltages is 50Hz with PWM frequency 27.5 kHz. Fig. 17-20 show the phase voltages; line voltages waveforms of Vab, and a harmonic of a phase load current ia.

Figures 21-22 demonstrate experimental model and a control interface between PC and FPGA, which is programmed by Visual Basic. The interface allows connecting PC to a model FPGA-IM, and controlling from PC.

Fig.17 Phase load voltages Fig.18 Line load voltage

Fig.19 The harmonic spectrum

of line voltage

Fig.20 Phase load current

Fig.21. The experimental model control induction motor

Fig. 22 The control interface between PC and model

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VII. CONCLUSION The proposed SVPWM in this paper is based on the one for

six switch three phase inverters (B6, SSTP) using principle of similarity where the αβ plan is divided into 6 sectors and the formation of the required reference voltage space vector is done in the same way as for B6 by using the additional effective vectors. This facilitates the SVPWM calculation for B4 and some studies on B6 can be applied for B4 as well through this proposed approach. The implementation of the proposed SVPWM is done by simulation and in experiment to serve the practical production of the cost effective inverters in the future.

The presented experimental results shows that the extremely fast FPGA computation time allows obtaining much higher throughput and overcoming the typical bottlenecks of DSP sequential algorithms mentioned at the beginning. Applying FPGA for power electronics control seems is an interesting alternative to the recently used digital signal processors. It should be emphasized that such high processing frequency (low loop period) as in the proposed FPGA application.

An application FPGA for SVPWM technique allows to prove Power Electronic Device, such voltage source inverters and increase switching frequency of power electronic switches.

ACKNOWLEDGMENT

The authors gratefully acknowledge the University of Technology of Ho Chi Minh City (Vietnam) and Network-Based Automation Research Center of University of Ulsan (Korea) for providing excellent supports and facilities.

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