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Lei Zhang, Hongtao Liu, Yan Zhao, Xiangnan Sun, Yugeng Wen, Yunlong Guo, Xike Gao, Chong-an Di, Gui Yu, and Yunqi Liu*

Inkjet Printing High-Resolution, Large-Area Graphene Patterns by Coffee-Ring Lithography

Reduced graphene oxide (RGO) is considered as a promising candidate for transparent electrodes because of its high elec-tric conductivity and the potential to be processed in solu-tion.[1–3] Furthermore, the molecular structure and energy level of RGO also guarantee it to be an attractive injection electrode for organic semiconductors. In fact, RGO has found a few applications in various organic electronic devices since its dis-covery.[4–9] For example, organic thin film transistors (OTFTs) including RGOs as source–drain electrodes have been fabri-cated, and show excellent performance.[10,11] In previous works, graphene electrodes have mainly been patterned by photolithog-raphy, shadow mask methods, and electron beam lithography (EBL).[12–14] Because these techniques are expensive or time consuming, we believed that inkjet printing should be a better method for the patterning of graphene materials. Moreover, inkjet printing is also suitable for application on large area sub-strates. However, features prepared directly by inkjet printing in additive motif often possess poor resolution, typically tens of micrometers. This low resolution is the main drawback of the inkjet printing technique and hinders the practical application of RGOs in OTFTs.[15]

Along with significant progress in solution-processable functional materials, some printing techniques, such as inkjet printing, have been developed in order to incorporate these materials into practical manufacturing process.[16,17] In recent years, resolution enhancement of a given inkjet printer has become an important focus of research.[18–23] Such efforts have been mainly based on wettability patterns, but to date high resolution inkjet-printed graphene oxides (GOs) have not been obtained using this method. That is partly because inks with

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L. Zhang, H. T. Liu, Y. Zhao, Dr. X. N. Sun, Y. G. Wen, Dr. Y. L. Guo, Dr. C.-a. Di, Prof. G. Yu, Prof. Y. Q. LiuBeijing National Laboratory for Molecular Sciences Key Laboratory of Organic Solids Institute of Chemistry Chinese Academy of Sciences Beijing 100190, P.R. China E-mail: liuyq@iccas.ac.cnL. Zhang, H. T. Liu, Y. Zhao, X. N. Sun, Y. G. WenGraduate School of Chinese Academy of Sciences Beijing 100039, P.R. ChinaDr. X. K. GaoLaboratory of Materials Science Shanghai Institute of Organic Chemistry Chinese Academy of Sciences Shanghai 200032, P.R. China

DOI: 10.1002/adma.201103620

large suspended particles like GOs or carbon nanotubes often clog the nozzle, especially when the nozzle size is reduced in order to enhance the line resolution. Furthermore, in an addi-tive inkjet printing process, flight deviation of ink drops is inev-itable and, in addition, the ink drops can migrate after they hit the substrate. These two factors often lead to an electrical short when the ink drops are placed close together to reduce the channel length. Therefore, patterning high-resolution graphene electrodes by inkjet printing remains a challenging task.[15,22]

Here we have successfully addressed this challenge by inkjet etching a polymer mask and then delaminating the mask layer in water. Taking advantage of the coffee-ring effect, electrode pairs with 1–2 micrometer channel length have been achieved using this method. Therefore, the patterning technique is referred to as coffee-ring lithography (CRL) herein. Using these graphene electrodes, we have successfully fabricated bottom contact OTFTs based on a pentacene active layer. As the fundamental components of logic circuits, complementary inverters with both n- and p-channel semiconductors deposited by inkjet printing are also described. In detail, the graphene electrode fabrication process includes the following steps as shown in Figure 1: 1) a uniform polyacrylonitrile (PAN) film

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Figure 1. Fabrication of the PAN mask layer by spin coating (1). Inkjet printing of pure solvent to dissolve the mask layer drop-on-demand (2). The substrate with patterned mask layer on top (3). Deposition of graphene oxide layer (4). Fabrication of the PS strengthening layer (5). Peeling off the mask layer and the strengthening layer (6).

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Figure 2. SEM images of PAN masks patterned into a) a dot array and b) an interdigital electrode using inkjet printing. c,d) The resulting graphene patterns after the lift-off process and thermal reduction.

was spin-coated onto the silica substrate as a mask layer; 2) pure N,N-dimethylformamide (DMF) was inkjet printed onto the substrate to dissolve the PAN film; 3) a silica–PAN pattern was formed by inkjet etching; 4) GO was spin-coated onto the silica–PAN pattern; 5) a polystyrene (PS) film was spin-coated to serve as a strengthening layer; and 6) the PS layer was lifted off in water. As shown in our previous work,[24] a PAN film was readily peeled off a silica substrate in water and was

Figure 3. a) Plot of coffee-ring width versus drop diameter for different mask layer thickness. b) Channel resolution as a function of distance between adjacent drops with fixed drop diameter of 87 μm. c,d) Graphene electrode pairs patterned using CRL under optimized conditions.

removed along with the PS strengthening layer, whereas GO remained on the substrate because of its large adhesion to silica. Thus, PAN masks can successfully produce a GO pattern on the substrate through a lift-off process. A dot array and an interdigital elec-trode fabricated using this CRL method are illustrated in Figure 2.

As shown in Figure 1, a drop of DMF dis-solved the underlying mask layer after landing on the substrate. During the drying process, the solvent migrated to the pinned contact line and carried the dissolved PAN to the edge of the drop, resulting in a ring-like dried residue. This phenomenon is often observed in dried coffee drops in daily life, so it was referred to as the coffee-ring effect.[25] This phenomenon has been utilized to create via-holes through polymer dielectric films.[26,27] Although the overall diameter of the DMF drop is large, partly because of the nozzle size of the inkjet equipment, the widths of the rings at the edge of the drop are much smaller (typically less than 5 μm; Figure S1, Supporting Infor-mation). Because the patterns of the PAN

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mask layer are complementary to the eventual GO patterns in this CRL method, a narrower coffee-ring width has the potential to produce lower channel length electrode pairs. We carefully investigated the relationship between the coffee-ring width and the drop diameter for different thicknesses of the mask layer. As shown in Figure 3a, a thinner mask layer and smaller drop diameter lead to narrower coffee-ring width.

Because two adjacent drops eventually form source–drain electrode pairs, we also investigated the relationship between the distance of adjacent drops and the channel length of the PAN masks. As shown in the left part of Figure 3b, if the adja-cent drops do not interact with each other, the decrease in channel length is directly proportional to the decrease in the distance between the drops. When the distance between the drops becomes less than the drop diameter, neighboring drops begin interacting with each other, and further reduction of the distance between two drops does not lead to higher resolution or electrical shorts (Figure S1). In this case—as illustrated in the right part of Figure 3b—for a mask layer with a given thickness, the optimized channel resolution does not depend on the dis-tance between two adjacent drops. In other words, slight devia-tion in the inkjet printing process (less than 10 μm) does not have a significant effect on the channel resolution (about 2 μm) or on the yield of the PAN masks (Figure S1). The observed tol-erance of deviation in the inkjet printing process is interesting and is one of the advantages of our method compared with the additive patterning method. Note that the channel length of the PAN masks determines the channel length of the resulting RGO electrode. In Figure 3b, we find that the best channel res-olution of the mask layer is about 1–2 μm, demonstrating the shortest channel length by using this method.

According to Figure 3b, we should reduce the thickness of the mask layer in order to improve the channel resolution. However, an additional strengthening layer is required to complete the

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Figure 4. Demonstration of CRL for the fabrication of graphene patterns on a large substrate. In (a) and (d) are shown the masks with an inkjet etched PAN/silica pattern and spin coated GOs, while (b) and (e) show the resulting GO pattern after lift-off and (c) and (f) show a large area graphene pattern after thermal reduction.

Figure 5. a,c) The morphology of a pentacene polycrystalline film grown on electrodes with different channel lengths, the color scale is 200 nm. b,d) The corresponding graphene electrode for the same location, the color scale is 20 nm. The scan range of all pictures is kept 10 μm.

lift-off procedure if the PAN layer is too thin. Hence, we depos-ited a thick PS film as a strengthening layer and then peeled off the PS layer in water. The introduction of an extra PS layer leads to a new problem for the lift-off process. As delamination of the mask layer was by the aid of water, when the PS layer was too thick, it would prevent water from penetrating between the PAN layer and the silica. We solve this problem by immersing the slide into water for a few minutes to wet the PAN/silica interface prior to spin coating the PS layer. Because of the large adhesion force between GO and the silica substrate, the GO pattern sur-vived the delamination process while the PAN layer was removed together with the PS layer. After vacuum annealing at 450 °C, we successfully obtained conductive graphene electrodes with channel lengths of 1–2 μm, as shown in the SEM photographs in Figure 3c and d. The Raman spectra of GOs and RGOs after 450 °C thermal treatment were taken to assess the reduction degree (Figure S2, Supporting Information). The channel reso-lution of 1−2 μm is satisfying as the scale of the graphene sheet is even comparable to the channel length. In addition to the enhanced resolution originating from the coffee-ring effect, this method could also be used in the fabrication process on large area substrates. In Figure 4 and e, we demonstrate graphene materials which have been patterned into a potted plant and the words “coffee-ring lithography” on a 5 × 5 cm2 silica slide using the CRL method. Because the successful patterning of the electrodes is based on the adhesion force between the electrode and the substrate being larger than that between the mask and the substrate, Cr—which is commonly used as an adhesive layer in the electronics industry—can also be patterned using this method (as shown in Figure S3, Supporting Information). This suggests that other materials, not only GOs or Cr, could also be patterned using this methodology only if they adhere firmly to the substrate. Another interesting point of our result is the zone selective deposition of the GOs arising from the surface

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difference between PAN and the silica layer (Figure S4, Supporting Information). During the spin-coating process, GOs are likely to deposit onto the silica surface rather than the PAN surface because of the large affinity of GOs to the silica surface. Although the zone selectivity is not sensitive enough to directly lead to high resolution feature, it suggests that fine surface energy patterns could also be fabricated using this method.

From the viewpoint of OTFT performance, the development of a patterning technique enables the fabrication of a high resolution electrode, which will enhance the on-current of discrete transistors and the integration density. However, when the channel length is too small, the channel resistance will decrease and eventually become comparable with the contact resistance. As the extra con-tact resistance cannot be tuned by the gate voltage, short channel transistors often pos-sess poor mobility and low on/off ratios (this is known as the short-channel effect). Thanks to the efficient charge carrier injection into the organic semiconductors, graphene has

been proposed as an attractive electrode material to suppress the short-channel effect.[28,29] Therefore, we fabricated OTFTs with an evaporated 45 nm pentacene layer as the semiconductor combined with graphene as source–drain electrodes. The mor-phology of the pentacene film grown on the electrode with varying channel length has been characterized by atomic force microscopy (AFM) as shown in Figure 5 and c. In the channel area, pentacene molecules were grown into large crystal grains

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Figure 6. a) Transfer and b) output characteristics of pentacene OTFTs with bottom contact graphene electrodes. c) Output voltage as a function of VIN measured at different driving volt-ages. The inset shows a schematic diagram of the complementary inverter. d) Output voltage and signal gain as a function of VIN measured at a 50 V driving voltage.

independent of the channel length. However, on top of the graphene electrode, the pen-tacene grain size was relatively small. The small grain size of pentacene when grown on graphene may be caused by the roughness of the underlying graphene electrode which would serve as a nucleation centre for penta-cene. To assure that the morphology change was induced by the underlying graphene, we re-evaporated the pentacene under high vacuum at 400 °C to expose the electrode again and then take the AFM picture at the same location (Figure 5b,d). Although the grain size of pentacene on the electrode was small, interestingly, the OTFT’s performance was not severely affected. The current–voltage (I –V) output and transfer curves are given in Figure 6 and b: the calculated charge carrier mobility is 0.2 cm2 V−1 s−1 in the saturation region, and the on/off ratio is larger than 105. For bottom-contact OTFTs with unmodified silica as the dielectric layer, this performance is satisfactory since the channel length is well below 5 μm and the semiconductor layer is prepared without substrate temperature opti-

mization.[30] We should note that our graphene electrode might also be used in OTFTs including a Langmuir–Blodgett film as transporting channel.[31] The electrode yield (about 80%) of the patterning process and the device mobility statistics for penta-cene OTFTs based on these graphene electrodes are summa-rized in Figure S6, Supporting Information.

Compared with evaporation-deposited semiconductors, solution-processed organic semiconducting materials are more suitable for application in low cost electronic circuits, as they can be deposited and patterned through a variety of printing techniques. We deposited solutions of 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) and core-expanded naph-thalene diimide fused with 2-(1,3-dithiol-2-ylidene)malonitrile groups (NDI2OD–DTYM2) by inkjet printing onto octadecyl-trichlorosilane (OTS)-modified silica substrates having pre-patterned graphene electrodes to form OTFTs. The molecular structures of TIPS-pentacene and NDI2OD–DTYM2, together with the discrete device transfer curves are given in Figure S5, Supporting Information. Using TIPS-pentacene as the p-type semiconductor and NDI2OD–DTYM2 as the n-type, we also fabricated complementary inverters and tested them in air. As shown in the circuit layout of the inverter in the inset of Figure 6c, a high input voltage turned off the p-channel tran-sistor and turned on the n-channel transistor, leading to a low voltage at the output terminal. When the input voltage was assigned a low value, the opposite effect was observed. As illustrated in Figure 6c, by sweeping the input voltage at dif-ferent driving voltages the working curve of a complementary inverter was obtained. When driven at 50 V, the best inverter gain reached 22 as shown in Figure 6d.

In conclusion, we have developed an innovative method for the fabrication of graphene electrodes based on inkjet printing, namely coffee-ring lithography. This method is similar to the traditional lift-off process, except that the mask is patterned by

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direct inkjet printing of a pure solvent. Taking advantage of the well-known coffee-ring effect, resolution of the channel reaches 1–2 μm. Furthermore, this method exhibits an impressive tol-erance of deviation in inkjet drop ejection. After annealing at 450 °C, we successfully obtained graphene electrodes and used them as source–drain electrodes in OTFTs. With pentacene as the semiconductor, the mobility of the resulting OTFTs was about 0.2 cm2 V−1 s−1 in the saturation region, and there was no obvious short-channel effect in the output curves. Inverters were also fabricated with both p- and n-semiconductors depos-ited by inkjet printing and showed gain values exceeding 20. As a complementary methodology to the additive printing process, our work provides inspiration for the further resolu-tion improvement of other printing techniques.

Experimental SectionGO Preparation: GO was synthesized using a modified Hummers

method according to the literature.[32] Graphite flakes (natural, Alfa Aesar, 325 mesh, 99.8%), NaNO3 (Sinopharm Chemical Reagent, Co., Ltd, AR), KMnO4 (Beijing Yili Fine Chemicals, Co., Ltd, AR), and concentrated H2SO4 (Beijing Chemical Works, AR) were all used as received. Before spin-coating, the GOs were washed with deionized water to pH 7 and diluted using ethanol at a ratio of water/ethanol = 1:2.

Fabrication and Patterning of the Mask Layer: the thickness of the mask layer was controlled by spin coating a PAN solution at 3500 rpm with different concentrations. After deposition of the mask layer, inkjet printing was performed using Jetlab II inkjet printing equipment from MicroFab Technologies. During patterning of the PAN masks, the substrate was kept at 80 °C in order to accelerate DMF evaporation.

Device Fabrication and Testing: TIPS-pentacene and pentacene were purchased from Sigma Aldrich and used as received. NDI2OD–DTYM2 was synthesized and purified as described in the literature.[33] A pentacene layer was vacuum deposited at a moderate rate of about 1 Å s−1. To fabricate the inverters, the surface of a silica substrate was modified with an OTS self-assembled monolayer. The concentrations

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of the semiconductor inks were 1 mg mL−1 for both TIPS-pentacene

and NDI2OD–DTYM2 with dichlorobenzene as the solvent. After deposition of the semiconductor layers, the devices were annealed at 150°C in a vacuum oven to remove the solvent residues. All OTFTs were characterized using a Keithley 4200 semiconductor characterization system in air. The mobility in the saturation regime was extracted from the following equation: IDS = Ciμ(W/2L)(VGS–VT)2, where IDS is the drain current, Ci is the capacitance per unit area of the gate dielectric layer, and VGS and VT are the gate voltage and threshold voltage, respectively.

Supporting InformationSupporting Information is available from the Wiley Online Library or from the author.

AcknowledgementsThis work was supported by the National Natural Science Foundation of China (60736004, 60911130231, 20973184), the Major State Basic Research Development Program (2011CB808403, 2011CB932303, 2009CB623603, 2011CB932701), and the Chinese Academy of Sciences.

Received: September 21, 2011Published online: December 21, 2011

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