Innovative Substrate Technologies in the Era of IoTs

Dyi-­‐Chung  Hu  胡迪群� September  4,  2015� Unimicron

DC Hu

Contents

•  Introduction •  Substrate Technology - Evolution •  Substrate Technology - Revolution

•  Glass substrate •  Integration of Substrate

•  Embedded Interposer Carrier (EIC) •  Embedded High Density Film (eHDF)

•  Conclusion •  Q and A

DC Hu

Packaging Requirement in the Era of Everything Connected

Big Data

IoT

Cloud

Sensors: Low Cost Small form factors Low power Performance Heterogeneous integration

Cloud: High Performance Low Power Low cost

DC Hu

Unimicron CSP Product Roadmap- Evaluation

                                                                                                                               2015                                        2016                                      2017    

FC  PoP  

EPS  FC  PoP  EAS  

FCCSP  

Bond  On  Line  

Ultra  Thin  CSP  (UTS)  

UTS-EP (Protrusion

bump)

High Density

Ultra Thin

Embedded Function

High  Cu  pillar  PoP  

UTS-Embedded Pattern

Coreless UTS-EP (3 ~ 8 layers)

Finer, Thinner Multi-

Functionality

DC Hu

Glass as Substrate and as Interposer Material

DC Hu

~200 packages (20mm×14mm)

300mm Silicon Wafer

500mm Glass Panel

~800 packages (20mm×14mm)

Glass as a Candidate for Substrate •  Larger panel size than Si wafer •  Potential lower material cost and less process flow

•  Insulator, no liner required. •  Can start with thin glass, no substrate thinning required.

•  CTE from 3~10ppm/℃ available •  Smooth surface

•  Fine line process : L/S≤3/3µm�

DC Hu

Million Dollar Questions:

• How to get cost effective glass via? • How to fill the glass via cost effectively?

7

DC Hu

How to Evaluate the Glass Via? •  TGV Diameter:

–  Top –  Bottom –  Taper ratio

•  TGV Roundness •  TGV Quality

–  Crater –  Chipping –  Crack

•  Surface Roughness •  Via Position Accuracy •  Via Forming Speed

8

106µm

70µm

75µm

30µm Glass Via

Few years ago

2015

DC Hu

TGV by Via Mechanics (Example 1)

•  Glass thickness: 100µm •  Via Size: 36µm (T), 30µm (B) •  Taper Ratio: 83% •  Via Pitch: 100 µm

Via Top

Top View Cross Section view

Via Bottom

*: Courtesy of Via Mechanic, Ltd

DC Hu

20µm glass via

25µm on 50µm pitch

TGV by LPKF (Example 2)

Glass Via, Top View

•  Glass thickness: 100µm •  Via Size: 20µm (T) •  Via Pitch: 50 µm

*: Courtesy of LPKF, AG

DC Hu

TGV and Blind Via by Corning (Example 3)

Space edge to edge 24µm

35µm

100µ

m

Thru-­‐holes  on  thin  glass   Thru-­‐Holes  on  thick  glass  

90µm

330 µm

35µm

225µ

m

40µm

120µ

m

Thickness:   ~100µm  →  700µm    

Type  of  Vias:   Blind  Via,  Thru  Via  

Aspect  RaKo:   ~  3-­‐10:1    

Hole  Diameter:  

100µm  →  20µm  →  10µm  

Fully  pa6erned  wafer  with  100,000s  of  holes  

Blind-­‐  holes  120µm  deep   Blind-­‐  holes  225µm  deep  

*: Courtesy of Corning Co.

DC Hu

Glass Via Throughputs  

•  Note: The TGV throughput data is via pattern dependent.

Progress of TGV Throughput Improvement

Years

Years

DC Hu

Glass Via Filling Technology

•  Via in Via •  Direct Cu conformal plating on glass •  Filled Via in Glass Conformal plating for TGV metallization.

300µm 100µm Glass

Unit: µm

Glass

Via in via Direct Cu plating Filled via

D=30µm

200µm

DC Hu

Glass as Laminated Core Replacement Material •  Development of 2+2 glass Substrate

ABF TGV Filling

Via in via laser drilling

DC Hu

508x508 mm Glass Panel Demonstrator •  Full panel glass can be processed through the HVM

line.

•  Glass thk.= 100~200µm •  Glass size = 508mm × 508mm

508mm

508mm

Unit size : 20mm x 20mm IMAPS 2014, Yu Hua Chen, Shaun Hsu, Urmi Ray, Ravi Shenoy, Kwan-Yu Lai, Aric Shorey, Rachel Lu, Windsor Thomas, Dyi-Chung Hu

DC Hu

Warpage Comparison between Glass and Organic Substrate

•  Glass core have ~3x better flatness (R <0.5mm) than organic core (R <1.5mm).

Core Material

Glass Organic substrate

Core Thickness 200µm 200µm

Panel Size 508mm×508mm 508mm×508mm

R value 0.490mm 1.367mm

Std. Dev. 0.062mm 0.273mm

Core Material CTE 3.17ppm/℃ 3ppm/℃

DC Hu

Challenges of Fine Line (L/S≤ 2µm) Technology in Panel

•  Large panel level exposure system

•  High resolution and sensitivity photoresist materials

•  Thickness uniformity of photoresist on panel

•  Control of seed layer removal

•  Availability of dielectric materials

•  Warpage during asymmetric build.

*: Dyi Chung Hu. etc, ICEP Japan April 2015

DC Hu

Fine Line in Double Dielectric Layers on Glass Substrate - Demostration •  Two layers of fine copper lines on glass substrate; by

panel level optics.

Lin width 1.9µm 1.8µm 1.7µm

Cu trace height on the 2nd layer: ~ 3µm

*: Dyi-Chung Hu. etc., ICEP, Japan April 2015

Glass

BUF

D1 D2

DC Hu

5um 30um Line Width (µm)

TPV

Via

Dia

met

er (µ

m)

20um

30um

20um

IC Fab Si Interposer

10um

5 um

Glass as Interposer Material

Glass Via/Hole Interposer type

(Filled Via)

10um

2015

2016

DC Hu

12” Glass Wafer

Glass Interposer

Substrate Side Chip Side

Glass Interposer

Schematic

Size 21 mm x 14 mm

Design

Connection Pad

Pillar D: 20 µm Pillar pitch: 40 µm Cu pillar height: 4 µm

I-1 passivation Dielectric thickness: 6 µm

I-1 metal Line/space: 3 µm / 3 µm Pad f: 40 µm, Cu thickness: 3 µm

TGV TGV D: 25 µm, TGV depth: 100 µm

The Glass Interposer Specification • Glass interposer specifications

*: Corning Glass

DC Hu

5um 30um

Line Width (µm)

TPV

Via

Dia

met

er (µ

m)

20um

5um

70um

30um

Laminate Substrate: Substrate

PCB

IC Fab Si Interposer

10um

10um

Solutions Needed for Next Generation Substrate

*: Dyi-Chung Hu, GIT 2014, Invited Talk

Low Cost Solution needed

DC Hu

Current Major Solution Proposals for Fine Line Substrate

•  2.5D interposer (TSMC, UMC..) •  Silicon/Glass Substrate

fine line RDL on both sides. (GIT/Unimicron, NTK, Shinko..)

•  2.1D substrate (Altera, Shinko, Kyocera..)

•  EMIB (Intel) •  EIC; Embedded interposer

Carrier (DC Hu/Unimicron) •  eHDF (DC Hu/SiPlus)

*: DC Hu Edit

2.1D

eHDF

EIC

EMIB

Glass Interposer

DC Hu

Die Last High Density Interconnection Substrate Solutions Types Solder Joins on

Substrate side Through holes

Z-Profile

Organization

Glass Interposer

1 1 ¢ GIT/Unimicron, NTK, Shinko

2.5D Interposer

1 2 � TSMC, UMC, Global Foundry, ASE, SPIL, Amkor, ….

2.1D Interposer

0 1 ¢ Altera, Semco, Shinko, Kyocera

EMIB 0 1 ¢ Intel

EIC 0 1 ¢ Unimicron

eHDF 0 0 ¤ SiPlus/Unimicron

DC Hu

Unimicron Embedded Interposer Carrier Technology (EIC)

DC Hu

Chip on Interposer on Substrate vs. FC-EIC®

•  Chip on Interposer on Substrate: (CoIoS) •  Interposer need double side RDL/Bumping and assembly process. •  Four testing steps are used: Interposer, carrier, Interposer+carrier, chip+interposer +carrier.

•  FC-EIC®: Flip Chip – Embedded Interposer Carrier •  Interposer need to be embedded into the substrate. •  Only two testing steps are used: interposer, and interposer+carrier. •  Risk of thin wafer handling process is reduced.

.

CoIoS FC-EIC®

*:USP Patent

DC Hu

I0

Silicon Interposer

“An Innovative Embedded Interposer Carrier for High Density Interconnection” ECTC 2013, DC Hu, TJ Tseng, YH Chen, W Lo

Laminated Substrate Laminated Substrate

Glass Interposer

“Embed Glass Interposer to Substrate for High Density Interconnection” ECTC 2014, DC Hu, YP Hung, YH Chen, RM Tain, W Lo

EIC-Silicon/Glass/Ceramic Structure Cross Section View- Examples

DC Hu

10007505002500

20

15

10

5

0

TCT(X)

Resistance  (Ω) 1

23456

No.ChainDaisy

10007505002500

12.5

12.0

11.5

11.0

10.5

TC T(X)

Re

sis

tan

ce

(Ω

)12.4

10.15

456

No.ChainDaisy

Sample  1

sample 1 da isy cha in 4~6

Upper limit: 10%

Lower limit: 10%

Electrical Measurement and Reliability Test of EIC-Glass Substrate • Open/Short Test of the EIC substrate.

•  Pass 50 TGV vias, total resistance around 11 Ohms. •  Resistance stable after 1000X TCT test

Chip side

Substrate Side

DC Hu

5um 30um

Line Width (µm)

TXV

Via

Dia

met

er (µ

m)

20um

5um

70um

30um

Laminate Substrate

PCB

IC Fab Si Interposer

10um

10um

Solutions for Next Generation Substrate – IoS (Integration of Substrates)

Low cost Solution needed

“Integration of Substrates （IoS)”

DC Hu

Integration of Substrates

Embedded High Density Film (eHDF) •  Solder-less •  and Core-less Solution

DC Hu

New Structure of Embedded High Density Film (eHDF)

Embedded High Density Film (eHDF)

Laminate Substrate

High Density Film

Z-height reduction

Conventional Structure CoIoS

Remove all solder joints Remove all through holes

Thin and Flat

DC Hu

eHDF SiP Solution Advantages •  A green solution: not only Pb free but free of Pb. •  A true die last solution. •  Satisfy both fine line and thick line requirements of substrate. •  Good electrical performance: short interconnection length.

(electrical signal no need to go through cores and solder joints)

•  Less Materials used: no core and no solder joints inside the eHDF substrate

•  Compatible with current OSAT infrastructure. •  eHDF Cost reduction advantage by:

•  Remove core of interposer; (TXV and copper filling constitute 30% of interposer cost.)

•  Remove solder joining process; without the cost of solder, the cost of assembly process and assembly yield loss.

•  Reduce individual test of interposer, substrate and PCB; from multiple tests to one final test.

•  Large panel (500x500mm up) process possible for further cost down.

DC Hu

Conclusions •  Substrate technology are under great changes due to the progress

of the “Moore’s Law” in semiconductor and the society is entering the era of IoTs, i.e. more heterogeneous integration.

•  Low cost solutions for both in high end and in low end are needed. •  New substrate materials such as glass is starting to find some

applications in electronic packaging. •  New packaging technology such as InFO-WLP, EMIB, SWIFT,

EIC and eHDF technologies are emerging to meet the customer requirements. Cost reduction solutions is the key.

•  It is a challenging time and also opportunity time for all the material, equipment and substrate makers. And there are still many innovative solutions needed to meet the challenging in the electronic packaging industry.

DC Hu

Thanks You for Staying to the last Talk of the Day!

DC Hu

Appendix: Terminology

Technology Details Company InFO-WLP Integrated Fan Out Wafer

Level Packaging TSMC

EMIB Embedded Multi-die Interconnect Bridge

Intel

SWIFT Silicon Wafer Integrated Fan out Tech

Amkor

EIC Embedded Interposer Carrier Unimicron eHDF Embedded High Density Film SiPlus, Unimicron IoS Integration of Substrates SiPlus, Unimicron