introduction to cmos vlsi design - ewu...
TRANSCRIPT
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Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design, © Addison-Wesley, 3/e, 2004
Introduction to CMOS VLSI Design
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Introduction
Integrated Circuits:many transistors on one chipVery Large Scale Integration (VLSI):very many transistors on one chipComplementary Metal Oxide Semiconductor (CMOS):fast, cheap, low power
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Outline
A Brief HistoryMOS transistorsCMOS LogicCMOS Fabrication and LayoutChip Design Challenges
System DesignLogic DesignPhysical DesignDesign VerificationFabrication, Packaging and Testing
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A Brief HistoryT-R-A-N-S-I-S-T-O-R = TRANsfer resiSTOR
1947: John Bardeen, Walter Brattain and William Schokley at Bell laboratories built the first working point contact transistor (Nobel Prize in Physics in 1956)1958: Jack Kylby built the first integrated circuit flip flop at Texas Instruments (Nobel Prize in Physics in 2000)1925: Julius Lilienfield patents the original idea of field effect transistors1935: Oskar Heil patents the first MOSFET1963: Frank Wanlass at Fairchild describes the first CMOS logic gate (nMOS and pMOS)1970: Processes using nMOS became dominant1980: Power consumption become a major issue. CMOS process are widely adopted.
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A Brief History
Integrated Circuits enabled today’s way of life1018 transistors manufactured in 2003
100 million for every human on the planet
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Moore’s LawIn 1963 Gordon Moore predicted that as a result of continuous miniaturization transistor count would double every 18 months53% compound annual growth rate over 45 years
No other technology has grown so fast so longTransistors become smaller, faster, consume less power, and are cheaper to manufacture
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Clock Frequencies of Intel Processors
Transistor count is not the only factor that has grown exponentially, e.g.clock frequencies have doubled roughly every 34 months
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Chip Integration Level
SSI = small-scale integration ( up to 10 gates)MSI = medium-scale integration ( up to 1000 gates)LSI = large-scale integration (up to 10000 gates)VLSI = very large-scale integration (over 10000 gates)
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Technology Scaling
1971: Intel 4004transistors with minimum dimension of 10um2003: Pentium 4transistors with minimum dimension of 130 nm
Scaling cannot go on forever because transistors cannot be smaller than atoms ☺
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The Productivity Gap
Source: SEMATECH
Designers rely increasingly on design automation software tools:• to seek productivity gains• to cope with increased complexity
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Silicon LatticeSilicon is a semiconductor Transistors are built on a silicon substrateSilicon is a Group IV materialForms crystal lattice with bonds to four neighbors
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DopantsPure silicon has no free carriers and conducts poorlyAdding dopants increases the conductivityGroup V: extra electron (n-type)Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
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Transistor TypesBipolar transistors
npn or pnp silicon structureSmall current into very thin base layer controls large currents between emitter and collectorBase currents limit integration density
Metal Oxide Semiconductor Field Effect TransistorsnMOS and pMOS MOSFETSVoltage applied to insulated gate controls current between source and drainLow power allows very high integration
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MOS Transistors
Four terminals: gate, source, drain, body (= bulk = substrate)
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nMOS OperationBody is commonly tied to ground (0 V)When the gate is at a low voltage:
P-type body is at low voltageSource-body and drain-body diodes are OFFNo current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
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nMOS Operation Cont.When the gate is at a high voltage:
Positive charge on gate of MOS capacitorNegative charge attracted to bodychannel under gate gets “inverted” to n-typeNow current can flow through n-type silicon from source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
1
S
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pMOS TransistorSimilar, but doping and voltages reversed
Body tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFBubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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Power Supply Voltage
GND = 0 VIn 1980’s, VDD = 5VVDD has decreased in modern processes
High VDD would damage modern tiny transistorsLower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
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MOS Transistors as switches
We can model MOS transistors as controlled switchesVoltage at gate controls path from source to drain
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CMOS Technology
CMOS technology uses both nMOS and pMOS transistors. The transistors are arranged in a structure formed by two complementary networks
Pull-up network is complement of pull-downParallel -> series, series -> parallel
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CMOS Logic Inverter
0110YA
0 = = 1ON
OFF1 = = 0
ON
OFF
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CMOS Logic NAND
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CMOS Logic NOR
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CMOS Logic Gates (a.k.a. Static CMOS)
Pull-up network is complement of pull-downParallel series, series parallel
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Compound Gates
Example: Y = (A+B+C) D
11000
---000011--1-1-1--11
YABCD
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Compound Gates
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How good is the output signal ?Signal Strength
Strength of signalHow close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0 sources
nMOS and pMOS are not ideal switchesnMOS pass strong 0, but degraded or weak 1pMOS pass strong 1, but degraded or weak 0
Thus:nMOS are best for pull-down networkpMOS are best for pull-up network
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Pass TransistorsTransistors can be used as switches
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Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
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Static CMOS gates are fully restored
In static CMOS, the nMOS transistors only need to pass 0’s and the pMOS only pass 1’s, so the output is always strongly driven and the levels are never degradedThis is called a fully restored logic gate
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Static CMOS is inherently invertingCMOS single stage gates must be invertingTo build non inverting functions we need multiple stages
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Tristates
111001Z10Z00YAEN
Tristate buffer produces Z when not enabled
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Nonrestoring Tristates
Transmission gate acts as tristate bufferOnly two transistorsBut nonrestoring
A is passed on to Y as it is (thus, Y is not always a strong 0’s or 1’s)
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Tristate InverterTristate inverter produces restored outputFor a non inverting tristate add an inverter in front
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Multiplexers
2:1 multiplexer chooses between two inputs
1X110X0111X000X0YD0D1S
0
1
S
D0
D1Y
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Gate-Level Mux Design
Y = S D0 + S D1How many transistors are needed?
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D1
D0S Y
4
2
22 Y
2
D1
D0S
= 20 = = Too Many !!
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Transmission Gate MuxNonrestoring mux uses two transmission gates
Only 4 transistors
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Inverting MuxInverting multiplexer
Use compound gate or pair of tristate invertersEssentially the same thing
For noninverting multiplexer add an inverter
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D Latch
When CLK = 1, latch is transparentD flows through to Q like a buffer
When CLK = 0, the latch is opaqueQ holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
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D Latch Design
Multiplexer chooses D or hold Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
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D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
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D Flip-flop
When CLK rises, D is copied to QAt all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop, master-slave flip-flop
Flop
CLK
D Q
D
CLK
Q
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D Flip-flop Design
Built from master and slave D latches
QMCLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
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D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
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Summary
“If the automobile had followed the same development cycle as the computer, a Rolls Royce would today cost $100, get one million miles per gallon, and explode once a year …”
Robert X. Cringely,InfoWorld Magazine