SUBRA GANESAN

Introduction to FPGA

Embedded system Characteristics

•Need increase in performance and more functions often.• Need Integration of more devices and chips•Decrease in Power consumption•Decrease in cost •Decrease in size•Decreased time to market

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Implement using?

Microprocessor/ Microcontroller ‐‐ more commonly used.

ASIC‐‐ for large volume products

FPGA‐‐ How easy or How fast ?

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Advantages of Micros

•Flexible to program and change • Available off the shelf as processor, board, or with interface chips• You can choose from 100s of types of Micros to suit the application• Easy to bring out a product in a short time•Power consumption is medium• Custom board can be designed after developing the product using generic boards.

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Micros-- Disadvantages

If you change the requirement or processor, new board is needed.

Micro may contain more features than needed or may not have needed features.

Cost depends on the volume.

To increase performance, you need to increase the memory or change the processor etc.

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ASIC--- Advantage

Lowest per unit cost for high volume

Can optimize power consumption, speed, performance, size, etc

Initial development cost prevents others entering this market.

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ASIC– Disadvantage

Initial Cost is high and increases every year

High Labor cost to design, test, modify etc

Development is challenging

Complex

Becomes obsolete soon since technology or requirement changes.

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FPGA-- Advantages

You can reconfigure the design

True parallelism

High speed

Costs less than ASIC for medium volume

Once this product works satisfactorily, you can make ASIC later.

A number of FPGA devices available to suit the applications.

Development tools cost is nominal.

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FPGA disadvantage

Internal Memory is limited

Analog interface is challenging

Power consumption is more

Difficult to program compared to Micro

Cost is more than micro cost

Not Suitable for small volume product

Learning to use or design Complex FPGA is more challenging

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FPGA, Micro, ASIC cost

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Volume 1 Volume 2 Volume 3 Volume 4 Volume5

Series 1

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ASICFPGA

Micro

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FPGA Vendors

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Actel

Altera

Atmel

Lattice

QuickLogic

Xilinx

Future of FPGA in Embedded System

Price of Complex FPGAs with 32-bit soft microprocessor core are now falling and will be close to microprocessor system price in 5 years.

Altera, Xilinx have a number of devices for Embedded system market at different price ranges.

FPGA represent the logical extension in the Hard to Soft migration of system functionality.

Soft design methods, tools are growing.

Processors, peripheral devices, logic, software can all be changed in FPGA system even after manufacture.

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FPGA Design needs System Approach

FPGA is a configurable platform.

You can move some functions to hardware or to software easily in FPGA for optimal performance. Example: Add more features to the mobile phone FPGA core.

Schematic based FPGA development. Example: Matlab, Labivew provide FPGA support

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Glossary for FPGA devices

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FPGA--- Field Programmable Gate ArrayFPSC-- Field Programmable System Chip (Processor Core + FPGA)FPAA-- Field Programmable Analogue Array (Anadigm)PAC-- Programmable Analog IC (lattice semiconductor)PLD -- Programmable logic deviceCPLD-- Complex Programmable Logic DeviceSPLD -- Simple Programmable logic deviceEPLD -- Erasable programmable logic devicePAL -- Programmable Array LogicPLA -- Programmable Logic ArrayPsoC- Programmable System on ChipLCA --- Logic Cell Array (Xilinx FPGA)GAL- Generic Array Cell (TM Lattice)

Figure 3.24   Programmable logic device as a black box.

Logic gates and

programmableswitches

Inputs

(logic variables) Outputs

(logic functions)

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Reference: Brown and Vranesic Book on Digital design

Figure 3.25.   General structure of a PLA.

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

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Figure 3.26.   Gate‐level diagram of a PLA. f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4

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Figure 3.27.   Customary schematic for the PLA in Figure 3.26.

f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

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Figure 3.28.   An example of a PLA.

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

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Figure 3.29.   Extra circuitry added to OR‐gate from Figure 3.28.

f1

To AND plane

D Q

Clock

SelectEnable

Flip-flop

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Figure 3.30.   A PLD programming unit (courtesy of Data IO Corp).Ganesan 1-2008

Figure 3.31.   A PLCC package with socket.Ganesan 1-2008

Figure 3.32.   Structure of a complex programmable logic device (CPLD).

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O block

PAL-likeblock

I/O b

lock

PAL-likeblock

I/O block

Interconnection wires

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Figure 3.33.   A section of the CPLD in Figure 3.32.Ganesan 1-2008

Figure 3.34.   CPLD packaging and programming.Ganesan 1-2008

Figure 3.36.   A two‐input lookup table (LUT).Ganesan 1-2008

Figure 3.37.   A three‐input LUT.

f

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

x 2

x 3

x 1

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Figure 3.40.   A section of two rows in a standard‐cell chip.

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Figure 3.41.   A sea‐of‐gates gate array.Ganesan 1-2008

Figure 3.65.   Programmable version of a NOR‐NOR PLA.f1

S 1

S 2

f2

x 1 x 2 x 3 NOR plane

NOR plane

S 3

S 4

x 4

S 5

S 6

V DD

V DD

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Figure 3.66.   A NOR‐NOR PLA used for sum‐of‐products. f1

P1

P2

f2

x 1 x 2 x 3 NOR plane

NOR plane

P3

P4

x 4

P5

P6

VDD

VDD

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Figure 3.67.   PAL programmed to implement two functions in Figure 3.66.

f 2

P 1

P 2

x 1 x 2 x 3

NOR plane

P 3

P 4

x 4

P 5

P 6

V DD

f 1

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Figure 3.68.   Pass‐transistor switches in FPGAs.

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Figure 4.18.   Implementation in a CPLD.

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Figure 4.19.   Implementation in an FPGA.Ganesan 1-2008