introduction to fpgas - inspiring innovationtinoosh/cmpe650/slides/fpgas-1.pdf · gate level...
TRANSCRIPT
![Page 1: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/1.jpg)
FPGAs 1
CMPE691/491: Advanced FPGA Design
![Page 2: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/2.jpg)
FPGAs Large array of configurable logic blocks (CLB)
connected via programmable interconnects
![Page 3: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/3.jpg)
Features and Specifications of FPGAs
![Page 4: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/4.jpg)
Basic Programmable Devices
![Page 5: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/5.jpg)
Features and Specifications of FPGAs
![Page 6: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/6.jpg)
Features and Specifications of FPGAs
![Page 7: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/7.jpg)
Features and Specifications of FPGAs
![Page 8: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/8.jpg)
Generic Xilinx FPGA Architecture
![Page 9: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/9.jpg)
Features and Specifications of FPGAs
![Page 10: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/10.jpg)
Virtex FPGA family name
![Page 11: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/11.jpg)
![Page 12: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/12.jpg)
FPGA vs ASIC
![Page 13: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/13.jpg)
Standard cell based IC
vs. Custom design IC
Standard cell based IC:
Design using standard cells
Standard cells come from library provider
Many different choices for cell size, delay, leakage power
Many EDA tools to automate this flow
Shorter design time
Custom design IC:
Design all by yourself
Higher performance
![Page 14: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/14.jpg)
Standard cell based VLSI
design flow
Front end
System specification and architecture
HDL coding & behavioral simulation
Synthesis & gate level simulation
Back end
Placement and routing
DRC (Design Rule Check), LVS (Layout vs Schematic)
dynamic simulation and static analysis
![Page 15: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/15.jpg)
Simple diagram of the front-end design flow
System
Specification
RTL
CodingSynthesis Gate level code
INV (.in (a), .out (a_inv));
AND (.in1 (a_inv), .in2 (b), .out (c));Ex: c = !a & b
Cab
![Page 16: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/16.jpg)
Simple diagram of the back-end design flow
gate level Verilog
from synthesisPlace
&
Route
Final layout
(go for fabrication)
DRC
Gate level VerilogLVS
Timing information
Gate level dynamic and/or static analysis
Design rule
check
Layout vs.
schematic
![Page 17: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/17.jpg)
Flow of placement and routing
• Floorplan (place macros, do power planning)
• Placement and in-place optimization
• Clock tree generation
• Routing
![Page 18: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/18.jpg)
Import needed files
• Gate level verilog (.v)
• Geometry information (.lef)
• Timing information (.lib)
INV (.in (a), .out (a_inv));
AND (.in1 (a_inv), .in2 (b), .out (c));
INV: 1um width AND: 2 um width
INV: 1ns delay; AND: 2 ns delay
INV ANDa
b
C
Delay (a->c): 1ns + 2ns = 3ns
![Page 19: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/19.jpg)
Floorplan
• Size of chip
• Location of Pins
• Location of main blocks
• Power supply: give enough power for each gate
VDD (Metal)
Power supply (1.8V)
current
Gate 1 Gate 2 Gate 3 Gate 4
1.75v
Voltage drop equation: V2 = V1 – I * R
1.7v(need another power)
1.65v
VSS
![Page 20: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/20.jpg)
Floorplan of a single processor
Inst
Mem
ALU
MAC
Control
Data
Mem
Clock
In-
FIFO0
In-
FIFO1
Output
![Page 21: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/21.jpg)
Placement & in-placement optimization
• Placement: place the gates
• In-placement optimization
– Why: timing information difference between synthesis and layout (wire delay)
– How: change gate size, insert buffers
– Should not change the circuit function!!
![Page 22: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/22.jpg)
Placement of a single processor
![Page 23: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/23.jpg)
Clock tree
• Main parameters: skew, delay, transition time
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Q
QSET
CLR
S
R Q
QSET
CLR
S
R
Q
QSET
CLR
S
R
Original Clock
Clock Delay = y
Clock Skew= x -yClock Delay= x
![Page 24: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/24.jpg)
Clock tree of single processor
![Page 25: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/25.jpg)
Routing
• Connect the gates using wires
• Two steps
– Connect the global signals (power)
– Connect other signals
![Page 26: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/26.jpg)
Metal Layer Topology
Routing
![Page 27: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/27.jpg)
Layout of a single processor
Area:
0.8mm x 0.8mm
Estimated speed:
450 MHz
![Page 28: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/28.jpg)
Clock Tree in FPGAs• Everything is preplaced and routed (there is no
space for improvement)
• There is no gate sizing to enhance performance
![Page 29: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/29.jpg)
FPGA vs ASIC summary
• Front-end design flow is almost the same for both
• Back-end design flow optimization is different
– ASIC design: freedom in routing, gate sizing, power gating and clock tree optimization.
– FPGA design: everything is preplaced, clock tree is pre-routed, no power gating
– Designs implemented in FPGAs are slower and consume more power than ASIC
![Page 30: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/30.jpg)
FPGA vs DSP
![Page 31: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/31.jpg)
![Page 32: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/32.jpg)
FPGA vs DSP• DSP:
– Easy to program (usually standard C)
– Very efficient for complex sequential math-intensive tasks
– Fixed datapath-width. Ex: 24-bit adder, is not efficient for 5-bit addition
– Limited resources
• FPGA
– Requires HDL language programming
– Efficient for highly parallel applications
– Efficient for bit-level operations
– Large number of gates and resources
– Does not support floating point, must construct your own.
![Page 33: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/33.jpg)
Current trend
• Programming flexibility
• High performance
– Throughput
– Latency
• High energy efficiency
• Suitable for future
fabrication technologiesP
erf
orm
an
ce
&
En
erg
y e
ffic
ien
cy
Programming flexibility
ASIC
FPGA
Prog.
DSP
Many
-core
![Page 34: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/34.jpg)
Target Many-core Architecture
• High performance• Exploit task-level parallelism in
digital signal processing and multimedia
– Large number of processors per chip to support multiple applications
• High energy efficiency
– Voltage and frequency scaling capability per processor
High F, V
Low F, V
Halt
34
![Page 35: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/35.jpg)
• 164 programmable procs.
• Three dedicated-purpose procs.
• Per processor Dynamic Voltage and Frequency Scaling (DVFS)
– Selects between two voltages (VDD High and VDD Low)
– Programmable local oscillator
167-processor Multi-voltage Computational Chip
Viterbi
Decoder
FFT
16 KB Shared
Memories
Motion
Estimation
D. Truong, W. Cheng, T. Mohsenin, Z. Yu, A. Jacobson, G. Landge, M. Meeuwsen,
C. Watnik, A. Tran, Z. Xiao, E. Work, J. Webb, P. Mejia, B. Baas, VLSI Symp. 2008, JSSC 2009 35
![Page 36: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/36.jpg)
Single Tile
Transistors 325,000
Area 0.17 mm2
CMOS Tech. 65 nm ST
Microelectronics
low-leakage
Max.
frequency1.19 GHz @
1.3 V
Power
(100%
active)
59 mW @
1.19 GHz, 1.3 V
47 mW @
1.06 GHz, 1.2 V
608 μW @
66 MHz, 0.675 V
App. power
(802.11a rx)16 mW @
590 MHz, 1.3 V
55 million transistors, 39.4 mm2
5.9
39 m
m
410 μm
41
0 μ
m
FFTVit
Mot.
Est. MemMem
5.516 mm
Mem
Summary of the 167 Many-core Chip
![Page 37: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/37.jpg)
Design Flow
![Page 38: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/38.jpg)
Design Flow
![Page 39: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/39.jpg)
Features and Specifications of FPGAs
![Page 40: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/40.jpg)
Features and Specifications of FPGAs
![Page 41: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/41.jpg)
Features and Specifications of FPGAs
![Page 42: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/42.jpg)
Features and Specifications of FPGAs
![Page 43: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/43.jpg)
Features and Specifications of FPGAs
![Page 44: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/44.jpg)
Features and Specifications of FPGAs
![Page 45: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/45.jpg)
Features and Specifications of FPGAs
![Page 46: Introduction to FPGAs - Inspiring Innovationtinoosh/cmpe650/slides/FPGAs-1.pdf · Gate level Verilog LVS Timing information Gate level dynamic and/or static analysis Design rule check](https://reader031.vdocuments.net/reader031/viewer/2022030511/5abb6d8f7f8b9a24028ca412/html5/thumbnails/46.jpg)
Backup