introduction to psoc 3 / psoc 5 workshop – rev *h 1 psoc 3 / psoc 5 102: system resources

Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 1

PSoC 3 / PSoC 5 102:System Resources


Section Objectives

Objectives, you will be able to:• Understand the system block diagram of PSoC 3 / PSoC 5

devices• Understand and use the PSoC 3 / PSoC 5 System Resources,

including: Power system

Programming & debugging

Configuration and boot process

Resets

Clocking

Memory & mapping

DMA and PHUB

I/O

Interrupts


System Block Diagram


Power System and Supplies (no boost)

Standard Power Configuration• No boost pump

• Vdda Vddd >= Vddio0/1/2/3

• Vdda = 1.8 – 5.5V

• Supply Rules & Usage• Vdda: Must be highest voltage in system.

Supplies analog high voltage domain and core regulator.

• Vddd: Supplies digital system core regulators

• Vcca: Output of the analog core regulator. An external 1.3 uF capacitor to ground is required.

• Vccd: Output of the digital core regulator. A single external 1.3 uF capacitor to ground is required. Both Vccd pins must be tied together on the PCB and share the single 1.3 uF capacitor.

• Vddio0/1/2/3: Independent I/O supplies. May be any voltage in the range of 1.8V to Vdda

Vssd Vssa

Vss

d

Vdd

io1

Vdd

io2 Vddio0

Vcc

d

Vdd

d

Vss

d

Vcc

d

Vdd

d

Vssd

Vcca

Vdda

Analog Regulator

Low Voltage Analog Domain

Low Voltage Digital

Domain

I2C Regulator

Sleep Regulator

Hibernate Regulator

I/O Supply I/O Supply

I/O SupplyI/O Supply

1.3µF

1.3µF

Vddio2

Vddio0

Vddio3Vddio1

0.1µF 0.1µF

0.1µF

0.1µF

Vddd

Vddd

Vdda

0.1µF

0.1µF

0.1µF

Vdd

io3

VbatVboostIndVssb

NC

High Voltage Analog Domain

Digital Regulator

0.1µF

0.1µF

0.1µF


Power System (with boost)

Boost Converter Configuration• Used to generate up to 5.0V (Vout)

• Battery voltage as low as 0.5V (Vbat)

• Output voltage and current limit based on input voltage and boost ratio

• 75 mA max current

• 0.5 – 0.8V Vbat provides max of 1.95V Vout

• Schottky diode required when Vout is >3.6V

• Synchronous rectification maximizes efficiency

• Boost may be used to power external circuits independent of PSoC Vdda and Vddd voltage

If boost not used:• Vssb, Vbat and Vboost must be tied to ground

• Ind left floating

Vboost

Ind

Vbat

Vssb Vssd

Vdda Vddd

Vssa

22uF 0.1uF

22uF

10uH

Optional Schottky Diode

Only required Vboost > 3.6V

Vddio

Boost Converter

Sync Rectification


Programming & Debug Interfaces

JTAG• Legacy 4-wire Interface • Supports all programming and debug features

Serial Wire Debug (SWD)*• Standard 2-wire interface for all CY tools and kits• Supports all programming and debug features with same

performance of JTAG• Default debug interface in PSoC Creator

Serial Wire Viewer (SWV)• Supports 32 mailboxes for application “printf” type debug• Uses only 1 pin

Vtarget

Gnd

Gnd

(key)

Gnd

TMS

TCK

TDO

TDI

1

3

5

7

9

2

4

6

8

10nTRST/XRES

Vtarget

Gnd

Gnd

(key)

Gnd

SWDIO

SWCLK

SWV

NC

nTRST/XRES

1

3

5

7

9

2

4

6

8

10


Programming and General Features

Standard Flash Operations• Erase all

• Erase block – 256 blocks per device independent of Flash size

• Program block

• Set block security (4 levels same as PSoC 1):Unprotected – No protection

Factory Upgrade – Prevents external read

Field Upgrade – Prevents external read and write

Full Protection – Prevents external read and write as well as internal write

General Features available through JTAG/SWD• IO boundary scan through JTAG interface

• Enable/Disable JTAG and SWD interfaces

• On Chip Debug features enabled/disabled by firmware


On Chip Debug (OCD)

Debug Features:

Trace Details• PSoC 3 – 4k on chip instruction trace included in all devices.

Trace memory may be used as system memory

• PSoC 5 – Select devices include ARM External 5-wire Trace Macrocell supporting ETM, ITM and DWT

1 PC Memory Dependant


Reset Sources

PPOR - Power On Reset

XRES - External reset pin

PRES - Under voltage on external supplies Vddd, Vdda

PRES - Under voltage on internal supplies Vccd, Vcca

AHVI - Over voltage on Vdda

HRES - Hibernate mode under voltage detect

SRES - User software and/or hardware generated reset

WRES - Watchdog reset

JTAG or SWD interface generates reset


Clocking Sources

Internal Main Oscillator: 3-67 MHz. (±1% at 3 MHz; ±5% at 67 MHz)

PLL output: 12-67 MHz (can not use 32 kHz crystal)

External clock crystal input: 4-33 MHz

External clock oscillator inputs: 0-33 MHz

Clock doubler output: 12-48 MHz

Internal Low speed oscillator: 1 kHz, 33 kHz and 100 kHz

External 32 kHz crystal input for RTC

PLL

4- 33 MHz

ECO

32 kHz

ECO

3- 67 MHz

IMO

0- 33 MHz

Ext Osc

1, 33, 100 kHz

ILO


Clock Distribution

Clock dividers

16-bit dividers

8 clock source inputs

8 digital clock dividers

4 analog clock dividers• Provide skew control to reduce

digital switching noise

1 CPU divider

UDBs can be used to create additional digital clocks

Digital Clock Divider16-bit








Analog Clock Divider16-bit




Skew

Skew

Skew

Skew

Bus/ CPU Divider16-bit

7 7

PLL

4-33MHzECO

32kHzECO

3-67 MHz IMO

0-33MHzExt Osc

1,33,100 kHz ILO


System Clock Setup


Clock Management

Clocks allocated to dividers in clock tree

Clocks have software APIs to dynamically change frequency

Note: Reuse existing clocks to preserve resources


8051 Memory Map

Internal Data space (IDATA)• 256 Bytes of SRAM• Standard 8051 specific SFR registers• Access port data registers through SFRs

External Data space (XDATA/16MB)• Up to 8 KB of SRAM on lead devices• All PSoC peripheral and configuration registers• EEPROM• Flash • External memory Interface (EMIF)


ARM Cortex-M3 Memory Map

Single 4 GB address space• Registers from 8051 map into 0.5 GB peripheral region’s bit band region for

efficient bit operations


External Memory Interface (EMIF)

EMIF Supports:• Sync SRAM• Async SRAM• Cellular RAM• NOR Flash

EMIF Usage:• PSoC 3 – Data only• PSoC 5 – Data and program• 8- or 16-bit data bus• 8-,16- or 24-bit address bus• Max throughput 11-16 MHz depending on

configuration details


Software Use of Registers

8051 and ARM Cortex-M3• Provide same functionality/address mapping to all PSoC 3 / PSoC 5

registers• Use Peripheral Hub (PHUB) bus

Macros hide MCU/compiler differences enabling PSoC 3 / PSoC 5 portability• cytypes.h

CY_GET_REG8(addr)

CY_SET_REG8(addr, value)

• cydevice_trm.hContains device register #defines

8051 includes SFR registers allowing direct register access• Affects portability to PSoC 5 if used• PSoC3_8051.h

Contains SFR register #defines


Flash

Flash Blocks:• 256 Blocks in all devices – 64 KB flash has 256 byte block size• Each block may be set to 1 of 4 protection levels of increasing security

Unprotected – Allows internal and external reads and writes

Factory Upgrade – Prevents external read

Field Upgrade – Prevents external read and write

Full Protection – Prevents external read and write as well as internal write

• Flash is erased and programmed in block units

Specs:• Code executes out of Flash• Flash-writes block CPU unless executing from cache (PSoC 5 only)• 20 year minimum retention• 10k minimum endurance• 15 ms block erase + write time


Error Correcting Code (ECC)

ECC = Flash Memory Error Correction•Required for some high reliability designs (e.g. automotive and medical)•Detects and corrects 1 bit of error•Detects but does not correct 2 bits of error•Correction is automatic, interrupt and flag bit are set •1 byte of ECC data for each 8 bytes of Flash data (1 row)•64 KB device includes +8 KB of ECC memory for 72 KB total

8 KB is used for configuration data storage if ECC not used (default)•ECC memory is mapped into contiguous region in peripheral space•ECC memory may also hold user data•Code can not execute out of ECC memory

Byte Byte Byte Byte Byte Byte Byte Byte ECC







EEPROM

2 KB of EEPROM are provided

Code can not execute out of EEPROM

EEPROM Specs:• EEPROM writes do not block CPU execution• 20 year minimum retention• 100k minimum endurance• 2 ms single byte erase + write time

• Supports single byte erase and writes

• May erase or write up to 16 consecutive bytes (1 row) at the same time.


Nonvolatile Latches (NV latches)

NV Latches• Single Flash bits used to hold critical configuration data• Required at power up before normal Flash can be read• Used the same as fuse bits except resettable• Uniquely capable of asynchronously outputting the bit state immediately on POR release

NV Latch Specs:• 10 minimum endurance (Like fuse bits, not programmed often)• 20 year minimum retention• Set as required by PSoC Creator (System tab of DWRM)• NV Latches are used for:

Each IO Port’s initial reset state (High-Z, pull-up, pull-down)

Optional XRES pin (P1[2]) enable

Configuration Speed (fast, slow)

Debug Port Selection (4-wire JTAG, 5-wire JTAG, SWD, None)

Error Correcting Code (ECC) enable

Digital clock phase delay (2.5 – 12.5 ns)


Bootloaders

Single Bootloader Supports

• I2C

• UART

• USB

• Others as required

Bootloader Integration

• Bootloader platform allows easy customization

• No bootloader programmed in parts at factory

• PSoC Creator integrates bootloader support seamlessly; just another component

Bootloader Framework

CommunicationInterface

FlashProgramming


Peripheral Hub (PHUB)

Interconnect between:• CPU• DMA• All peripherals

Two potential masters• DMA controller• CPU

Arbitrates between CPU and DMA• Priority based on spoke• Supports simultaneous DMA and CPU

access on separate spokes• CPU is not a bus hog

Reduces power consumption

Translates:• Byte-order • Data width differences


Direct Memory Access (DMA)

24 hardware channels

8 priority levels with minimum bandwidth guarantees

128 Transaction Descriptors (TD) tell channel what to do• 2kB of dedicated SRAM holds all TD data

Multiple channels or TDs may be chained or nested

Configurable burst size

DMA between peripherals on same spoke limited to 1-byte burst length


GPIO - I/O Digital Features

Independent supply rails• Each quadrant of device has

separate Vddio supply (100 mA max sink or source)

• GPIO Vddio must be <= Vdda

Logic level max current• 8 mA sink• 4 mA source

Pin max current• ~25 mA sink• ~25 mA source


GPIO - I/O Digital Features

8 Drive Modes

High Impedance Analog

PSDR

PSDR

PSDR

0. High ImpedanceDigital

1. Resistive Pull-Up

2. ResistivePull-Down

3.

Open Drain,Drives Low

4. Open Drain,Drives High

5. Strong Drive6. ResistivePull-Up & Down

7.

Vio

PinPinPin

Vio

Pin

Vio

Pin

Vio

Pin

Vio

PinPinPSDR

PSDR

PSDR

PSDR

PSDR


GPIO - Interrupts

Each GPIO port has:• Port Interrupt Control Unit (PICU) • Dedicated interrupt vector

Interrupt on:• Rising edge

• Falling edge

• Any edge

Status Register• Latches which pin triggered interrupt

• Available for firmware read

• Read clear


GPIO - I/O Analog Features

• All pins inputs and outputs• Supports two independent analog

connections at each pin• Some pins have additional

routing features:• Opamps

• High Current DAC mode

• CapSense Touch Sensing• LCD char/segment drive• Hardware controlled analog mux

at pin


SIO (Special I/O) Features

Same as GPIO with exceptions:• 5.5V tolerant at all Vdda levels

Hot Swap

Overvoltage tolerance

• Configurable drive and sense voltage levels

Basic DAC output

High Speed CMP input

• Logic level max current25 mA sink

4 mA source

• Pin max current~50 mA sink

~25 mA source

• No Analog

• No LCD char/segment drive

• No CapSense touch sensing

5KDrive Mode 0

Data Register

5K

PIN

Digital Output Path

Digital Input Path

Slew Cntl

Slow Slew Enable

Drive Mode 1

Drive Mode 2

Digital Output0

1

Data Register Bypass

Bidirectional EnableBidirectional Control

Interrupt Controller

Digital Input

Pin Status Register

CMOS or LVTTL

Buffer DisableInterrupt Logic

Pin Interrupt Type Register

Pin Interrupt Status Register

DriverVhigh

Programmable Output Buffer Configuration

Programmable Input Buffer Config Buffer Thresholds

DriveLogic


I/O Registers

Standard port registers• Multiple register writes to configure a single

pin• Able to configure whole port with a couple

of register writes• Separate Port Status (PS) and Data

Register (DR) for read, modify, write of port pins

Orthogonal pin registers• Configure 1 pin in a single write• Standard and Orthogonal register

operations can be mixed on same pin

Orthogonal port register• Configure all pins in a port to same state

with a single write

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Bit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7

Data Output – (Port 3 DR)

Drive Mode 0 – (Port 3 DM0)



Pin Input State – (Port 3 PS)

Bidirectional Enable – (Port 3 BIE)

Slow Slew Rate – (Port 3 SLW)

Data Register Bypass – (Port 3 BYP)

Pin 6

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

BYP SLW BIE PS DM2 DM1 DM0 DRPort Pin Configuration – Port 3, Pin 2










DM0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0

Pin 7

Pin 6

Pin 5

Pin 4

Pin 3

Pin 2

Pin 1

Pin 0









BYP SLW BIE PS DM2 DM1 DM0 DRPort Pin Configuration – Port 3, Pin 2

BYP SLW BIE - DM2 DM1 -Port Wide Configuration – Port 3



Software Use of I/O Registers

PHUB Bus Register Macros:• cytypes.h - Contains register macro definitions

• cydevice_trm.h - Contains device register definitions

Port = CY_GET_REG8(CYREG_PRT0_DR);

CY_SET_REG8(CYREG_PRT0_DR, 0x04);

Use of SFR registers for 8051 provides direct register access, limits portability• PSoC3_8051.h - Contains SFR register #defines

SFRPRT0DR |= 0x04;

8051 provides efficient bit operations on port SFR registerssbit bLed1 = SFRPRT0DR ^ 3;

bLed1 = 1;

Pin Component provides APIs like any other component• Pin_1_Write();

• Pin_1_Read();

• Pin_1_ReadDataReg();

• Pin_1_SetDriveMode();

• Pin_1_Clearinterrupt();


Pin Management

PSoC Creator, CyFitter can select pins automatically• Best to let fitter have maximum flexibility to optimize entire design

• Lock pins when device pin out is finalized

Manual override in DWR file


Interrupts

Interrupt Controller• 32 interrupt vectors

• Dynamically adjustable vector addresses

• 8 priority levels

• Each vector supports one of three sources

Fixed function, DMA, DSI (UDB) route

8051• 32 interrupt vectors vs. standard 8051

is five

ARM Cortex-M3• 32 interrupts + 15 exceptions

• Tail chaining


Interrupt Component

GUI Configuration

API

isr_1_Start() – Configures and enables the interrupt. Typically the only API required to be called

Advanced APIs

isr_1_SetVector() – Dynamically change vector address

isr_1_SetPriority() – Dynamically change vector priority

isr_1_GetPriority() – Read current priority

isr_1_Enable() – Enable interrupt vector

isr_1_GetState() – Return current state of interrupt vector enable

isr_1_Disable() – Disable interrupt vector

isr_1_SetPending() – Force a pending interrupt

isr_1_ClearPending() – Clear a pending interrupt


Review

You should now be able to:• Understand the system block diagram of PSoC 3 / PSoC 5 devices

• Understand and use the PSoC 3 / PSoC 5 System Resources, including:

Power system

Programming & debugging

Configuration and boot process

Resets

Clocking

Memory & mapping

DMA and PHUB

I/O

Interrupts


Lab1 102:My First PSoC 3 Analog Design


Lab Objectives

Objectives:• Acquire an analog signal from the on board accelerometer and it to

display LEDS as a carpenter’s level.

• More experience with the PSoC Creator Design Flow


Step 1: Open ‘Lab 102 – My First PSoC3 Analog Design.cywrk’


Step 2: Open TopDesign.cysch


Step 3: Place/Configure Analog Pin


Step 4: Place/Configure ADC


Step 5: Wire Components


Step 6: Configure PSoC I/O


Step 7: Review Firmware


Step 8: Build Project


Step 9: Program/Debug


Step 10: Debug

introduction to psoc 3 / psoc 5 workshop – rev *h 1 psoc 3 / psoc 5 102: system resources

Documents

system memory psoc

system block diagram

trace details psoc

workshop rev

vdda slide

system block diagram

chip debug features

system resources