introduction to the courseesc.inu.ac.kr/~seban90/lab1.pdfintroduction to the course. course...
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Jaeyong Chung
SoC Laboratory
Incheon National University
Digital Integrated Circuits
Introduction to the course
Course Information
Schedule
(EPC6055001) Mon 6:55pm - 8:40pm (SI433), Tue 7:50pm -
9:35pm (SI325)
(EPC6055002) Tue 2:00pm - 3:50pm (SI223), Wed 3:00pm -
4:50pm (SI325)
(EPC6055003) Tue 10:00am - 11:50am (SI223), Wed 1:00pm
- 2:50pm (SI325)
Instructor
Jaeyong Chung (정재용, [email protected])
Office : 454, 4th floor, Building 8B
Tel: 032-835-8458
Office Hours: One hour after the lab class, or by appointment
(Send an email to schedule an appointment)
Website: http://esc.incheon.ac.kr
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Attendance / Late
Attendance : 3 absences with no notice → F
Late : 5 or more times → Penalty
Course Website
https://sites.google.com/site/epc6055000/2017fall
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Textbooks
“Digital Systems Design Using Verilog”, Charles H. Roth, Jr
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Prerequisites
Digital Logic Design
Background
Boolean Algebra (ex) Truth Table)
Combinational Logic (ex) Primitive Gates (AND, OR and etc.)
Sequential Logic (ex) Latch, Flip-Flop, Clock)
Finite State Machine (ex) Traffic Light Controller)
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Feedback
Need Feedback : Adjust Pace / Course Difficulty Level
Main Communication Language
ENGLISH
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Before Class Starts..
Grading
30% Midterm
30% Project
20% Labs
10% Quiz
10% Attendance
Late Policy
10% per day of delay
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Before Class Starts..
Thanks to..
Kyosun Kim @ Incheon National University
Nur Touba and Lizy John @ The University of Texas at
Austin
Joon-Sung Yang @ Sungkyunkwan University
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Jaeyong Chung
SoC Laboratory
Incheon National University
Digital Integrated Circuits
Lab1
Contents
Toolchain Installation
Modelsim
Download
Installation
License
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Simulation Tool
ModelSim PE 10.4a
ModelSim is an HDL Verification Tool
Developed by Mentor Graphics, an
EDA Tool Expert Company.
Both VHDL and Verilog Descriptions
can be Simulated.
ModelSim can Simulate Designs which
are Described in Mixed Languages
(VHDL, Verilog, and SystemC).
A Free Version can be Downloaded
from http://www.model.com
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Download site
www.model.com
Download
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Install program
Install modelsim-pe_student_edition
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Fill out the form and click the Request License button
Download License File
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Download License File
License file is attached to email.
Download license file.
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Download directory
C:\Modeltech_pe_edu_10.4a
Download License File
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Contents
Toolchain Installation
Modelsim
Download
Installation
License
Simulation
Half Adder
Full Adder
4 bit Adder
4 bit Adder/Subtractor
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Create New Project
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Create a new project
Create New Project
Click the “Create New File” icon.
File Name
halfAdder.v
Add file as type
Verilog
Half adder
Create Verilog File
yx
sc00
0010
1001
1011
01carry sum
Carry Sum
x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
xy
s
c
x
y
s
cHA
Select the “halfAdder.v” file.
Enter the code into the source window.
Create Verilog File
Create Test Bench File
Project -> Add to Project -> New File
Filename
halfAdderTb.v
Add file as type
Verilog
Test bench source
Create Test Bench File
Compile Project
Click the “Compile All” button.
Start Simulation
Simulation -> Start Simulation
Select halfAdderTb
Start Simulation
Wave window
Start Simulation
Select all objects.
Right click and select Add Wave.
Start Simulation
Objects are added to wave window.
Start Simulation
Enter run into command line
Start Simulation
Simulation result
Full Adder
Full Adder
Module code
Full Adder
Test bench
Full Adder
Simulation result
Full Adder
4 bit Adder
4 Bit Adder
4 Bit Adder
Hierachy structure
fourBitAdder0(4 bit Adder)
halfAdder2(Half Adder)
bit3(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
bit2(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
bit1(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
bit0(Full Adder)
halfAdder1(Half Adder)
4 Bit Adder
Hierachy structure
fourBitAdder0(4 bit Adder)
halfAdder1(Half Adder)
bit3(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
halfAdder1(Half Adder)
bit2(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
halfAdder1(Half Adder)
bit1(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
halfAdder1(Half Adder)
bit0(Full Adder)
halfAdder1(Half Adder)
halfAdder2(Half Adder)
4 Bit Adder
Module code
Test bench
4 Bit Adder
4 Bit Adder
Simulation result
4 bit Adder/Subtractor
4 Bit Adder/Subtractor
Module code
4 Bit Adder/Subtractor
Test bench
4 Bit Adder/Subtractor
Simulation result
4 Bit Adder/Subtractor
Homework
Put correct operators in each blank, and complete a 4
bit Adder/Subtractor.
Verify it through simulation.