Introduction to Digital Design using VHDL

VHDL is the acronym ofVHSIC Hardware Description Language

and VHSIC stands forVery High Speed Integrated CircuitsWhat is VHDL?

..Continues VHDL is a general-purpose programming language that can be used to model complex digital circuits for automatic circuit synthesis or for system simulation.

A description language, developed in the early 1980s, funded by the U.S. Department of Defense. The first publicly available version of VHDL, version 7.2, was released in 1985.

IEEE 1076-1993, version released in 1994 and IEEE 1164 standards together form the complete VHDL standard which is widely use today.

Part I - Introduction to VHDLStructure of a VHDL program

VHDL Terminologies Identifiers in VHDL Data types in VHDL Data Objects in VHDL Operators in VHDL

Structure of a VHDL programA VHDL program can be considered to have four declaration parts likeLibrary DeclarationPackage DeclarationEntity DeclarationArchitecture Declaration

Library DeclarationSyntax: library lib1,lib2,..libn;The library clause makes visible all libraries specified in the VHDL programFor example library ieee;The above line makes visible, the library named ieee in the design unit.

Package DeclarationSyntax: use library_name.package_name.all;ORuse library_name.package_name.component_name;For example use ieee.std_logic_1164.OR;The above line make visible OR function included in the package std_logic_1164, residing in the library named ieee.use ieee.std_logic_1164.ALL;The above line make visible all components included in the package std_logic_1164,residing in the library named ieee.

Entity DeclarationBy entity we mean the external view of the hardware to be modeled. Syntax:Entity entity_name is Port (list_of_interface_ ports:port_mode: data_type; list_of_interface_ ports:port_mode: data_type);End entity_name;Entity mux2to1 isPort(A,B,S:in bit;Z:out bit);end mux2to1;

Syntax for entity declaration is common for any type of modeling.

Architecture DeclarationBy architecture we mean the internal view of the hardware to be modeled. Syntax:Architecture architecture_name of entity_name isVarious declarations;BeginConcurrent statements;End architecture_name;Architecture a_mux2to1 of mux2to1 isBeginZ

Let us considerA two channel multiplexerTwo input channels A and BOne channel select input SOne output line - Z

External ViewInternal View

VHDL code for Mux2to1Modeling of a 2to1 Mux using dataflow style Library ieee;use ieee.std_logic_1164.all;

Entity mux2to1 isPort(A,B,S:in bit;Z:out bit);end mux2to1;Architecture a_mux2to1 of mux2to1 isBeginZ

ContinuesThe following lines are included to make library named ieee visible in the program.Library ieee;The following lines makes visible all components in package std_logic_1164, residing in library ieee.use ieee.std_logic_1164.all;Entity is declared whose name is mux2to1, with input ports A, B and S. The output port is declared as Z. All these ports can have bit type values.Entity mux2to1 isPort(A,B,S:in bit;Z:out bit);end mux2to1;

ContinuesArchitecture a_mux2to1 of mux2to1 is

BeginZ

VHDL TerminologiesIdentifiers in VHDLIn VHDL identifiers are used to identify an entity, an architecture, an input, an output port, a signal etc. Basic identifiers in VHDLName of a Basic Identifier must start with an alphabetName of a Basic Identifier must not end with an underscore(_)Two consecutive underscores are not allowed(__)Keywords like and, or are not allowed as a basic identifier. Not case sensitive MUX2to1 is same as mux2to

Some legal keywords: mux2to1, mux_2to1,mux2 Some illegal identifies: 2to1mux,mux__2to1,mux2to1_

Extended identifiers in VHDLSlashes at the start and end - \Mux2to1\Keywords can be used as an extended identifier - \and\, \or\Case sensitive - \nand\ and \NAND\ are not same.

Some legal identifiers: \nand\,\NAND\,\and\,\AND\

Let us identify the identifiers..

library ieee;use ieee.std_logic_1164.all;

Entity mux2to1 isPort(A,B,S:in bit;Z:out bit);end mux2to1;Architecture a_mux2to1 of mux2to1 isBeginZ

Ports in, out and inoutThere are two types of ports unidirectional and bidirectional

Unidirectional ports input port and output port

Bidirectional port inout port

One can read an input port and write into the output port.

One can read and write into an inout port.

In the previous VHDL program for 2to1 multiplexer the letters

A,B,S & Z indicates input and output ports.

Ports A,B & S are used to carry data into the circuit. So these are the INPUT PORTS.

The port Z is used to carry the output of the circuit under consideration. So this is the OUTPUT PORT. Ports in the VHDL code for Mux2to1

Data Objects in VHDLIn VHDL data objects are used to hold some data.

A data object belongs to any of the following classesConstantVariableSignalFileSyntax:- class data_object1,data_object2,data_objectn:data_typeAs an example let us considersignal A,B:bit;variable C:integer;constant M:std_logic_vector

Data Types in VHDLData types refers to different types of data, a data-object can have.

Different data types are Scalar data typeComposite data typeAccess data type and File data typeSome pre-defined data types in VHDL are BIT, STD_LOGIC, INTEGER, BOOLEAN

Operators in VHDL

Different operators in VHDL are

Logical operators AND, OR, NOT, XOR, NOR etc.

Arithmetic operators - +, *-, /

Relational operators - , =, /=

Miscellaneous operators ABS, MOD, REM

Shift operators ROL, ROR, SRL, SRR, SLA, SRA

Part II Different Modeling StylesDifferent modeling styles in VHDL

Dataflow Style of ModelingModeling ExampleStructural Style of ModelingModeling ExampleBehavioral Style of ModelingModeling ExampleMixed Style of ModelingModeling Example

Dataflow Style of ModelingUses statements that defines the actual flow of data. So the name Dataflow Modelingsuch as,x

Example - Dataflow Modeling2 Channel multiplexer with Enable input External View - Entity

Example - Dataflow Modeling2 Channel multiplexer with Enable input External View - Architecture Z

Example - Dataflow Modelinglibrary ieee;use ieee.std_logic_1164.all;

--Entity Declaration

Entity mux2to1e isPort(A,B,S,E:in bit;Z:out bit);end mux2to1e;--Architecture declaration

Architecture d_mux2to1e of mux2to1e isBeginZ

implements the module as a composition of subsystems

contains signal declarations, for internal interconnections

the entity ports are also treated as signals

Contains component declaration in the declaration part

Contains component instantiation in the architecture body

Structural Style of Modeling

Syntax of Structural ArchitectureSyntax for entity declaration is common for any type of modeling.

Architecure arch_name of entity_name isComponent declarations; Signal declarations;Begincomp_label1:comp_name port map(list of i/f ports);comp_label2:comp_name port map(list of i/f ports);comp_labeln:comp_name port map (list of i/f ports);End arch_name;

Component Instantiation

Syntax for component declarationComponent declaration:-

Component component_nameThe line as it appears in the entity declaration of the component; End Component;

Eg: Component mux2to1ePort(A,B,S,E:in bit;Z:out bit);End Component;

Syntax for component instantiationComponent Instantiation:-

comp_label:comp_label port map(list of i/f ports);

Eg: M0: mux2to1e Port map(P,Q,S0,X,S1);

Example Structural ModelingFour Channel Multiplexer External View - Entity

Four Channel Multiplexer Internal View - Architecture

Example Structural Modeling

External View Entity Declarationlibrary ieee;use ieee.std_logic_1164.all;

--Entity Declaration

Entity mux4to1 is Port(P,Q,R,T,S1,S0,En:in bit; Y:out bit);end mux4to1;

--Architecture Declaration

Architecture S_mux4to1 of mux4to1 iscomponent mux2to1ePort(A,B,S,E:in bit;Z:out bit);end component;signal S2,S3;BeginM0:mux2to1e port map(P,Q,S0,En,S2);M1:mux2to1e port map(R,T,S0,En,S3);M2:mux2to1e port map(S2,S3,S1,En,Y);end S_mux4to1;Internal View Architecture DeclarationComponent Declaration

Component Instantiation

Behavioral ModelingBehavioral architecture

describes the behavior of device to be modeled.

describes the algorithm performed by the module

Contains Process Statement which is sensitive to signal in the sensitivity list.

Sequential statements like if-end if, case-end case etc. are included in process statement

It is mandatory to have an End Process for the Process statementSyntax for entity declaration is common for any type of modeling.

Syntax of Behavioral ArchitectureArchitecture arch_name of entity_name isGlobal/Shared declarations;BeginProcess(Sensitivity list)Local declarations;BeginSequnetial statement1;Sequential statement n;End process;End arch_name;

Example Behavioral ModelingLet us consider an AND gate

Let us consider the behavior of an AND gateIf A=0 and B=0 then C=0If A=0 and B=1 then C=0If A=1 and B=0 then C=0If A=1 and B=1 then C=0

In other wordsIf A=1 AND B=1 then C=1 else C=0

AlsoIf A=0 or B=0 then C=0 else C=1

Example Behavioral ModelingD Flip Flop - External View - EntityLibrary ieee;Use ieee.std_logic_1164.all;Entity dff isPort(Din,CLK:in bit;Q,Qb:out bit);End dff;Entity Declaration

Behavior of D Flip FlopD CLK Q Qb1 to 0 1 000 to 11 001 to 00 10 to 10 111 to 01 0

If there is a negative clock (when clock changes from 1 to 0) output is equal to input, else there is no change in output.

Architecture/Internal Viewsensitivity listArchitecture b_dff of dff isBeginProcess(Din,CLK)BeginIf CLKevent AND CLK=0 thenQ

Mixed Style of ModelingIf any two of the modeling styles are used for the implementation of the architecture - the modeling is mixed style of modeling.

For example, an architecture can contain Behavioral and dataflow statements, structural and dataflow statements.process statements and component instancesComponent instances and signal assignments

Realization of a 4 input Multiplexer External View - Entity

External View Entity Declarationlibrary ieee;use ieee.std_logic_1164.all;

--Entity Declaration

Entity mux4to1 is Port(P,Q,R,T,S1,S0:in bit; Y:out bit);end mux4to1;

Realization of a 4 input Multiplexer Internal View - Architecture

--Architecture Declaration

Architecture S_mux4to1 of mux4to1 iscomponent mux2to1ePort(A,B,S,E:in bit;Z:out bit);end component;signal S2,S3,S4;BeginM0:mux2to1e port map(P,Q,S0,S4,S2);M1:mux2to1e port map(R,T,S0,S1,S3);

Y