introductions - ece496 administrators · - comparators with hysteresis needed - correct input...

16
1 1 ECE496 Design Project Opening Lecture Thursday, Sept. 7, 2017 Prof Phil Anderson 2 Introductions - ECE496 Administrators 3 Introductions - ECE496 Team Members Karen Irving (Registration) Mike Mehramiz (Design Centre) Ken Tallman & ECP (Engineering Communication Program) team G 4 Outline Tonight An introduction to "Real-World Engineering" (Gillett) Course Deliverables and Resources (Anderson) Next Thursday, Sept. 14 th , 7-8PM, MC102 Preparing Your Project Proposal (Tallman/Phang)

Upload: dangnguyet

Post on 21-May-2018

221 views

Category:

Documents


1 download

TRANSCRIPT

Page 1: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

1

1

ECE496 Design ProjectOpening Lecture

Thursday, Sept. 7, 2017

Prof Phil Anderson

2

Introductions - ECE496 Administrators

3

Introductions - ECE496 Team Members Karen Irving(Registration)

Mike Mehramiz (Design Centre)

Ken Tallman & ECP (Engineering Communication Program) team

G

4

Outline

Tonight An introduction to "Real-World Engineering" (Gillett) Course Deliverables and Resources (Anderson)

Next Thursday, Sept. 14th, 7-8PM, MC102 Preparing Your Project Proposal (Tallman/Phang)

Page 2: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

2

“Why am I here?” you ask

?

5

• Practice, practice, practice• Applying to Jobs / Grad School

• Experience in field• Contact in faculty• Something different than others

• Make your mistakes now…• Attributes

6

No team / project / supervisor??

After the lecture I will be meeting with all people that do not have a registered

project, including those that do not have a team.

1. People with teams fill in a form, hand it in and leave.

2. People without teams will meet together to form teams, fill in a form and leave.

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

ECE496:

An Introduction to "Real World Engineering"

Ross Gillett, M.Eng, P.Eng, FEC7 September 2017

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Agenda

• What is Engineering?• ECE 496: Essential for any career !!!

– Teamwork: The key to Engineering– Project Planning, Communication, and Risk

Management– Project system design, requirements, verification

• Design, and an example of a project• Summary

Page 3: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

3

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

What is Engineering?

• Science/Math ("knowledge"):– Matrix mathematics– Electromagnetic Forces– Material properties– Circuit theory, etc

• Engineering("creation using knowledge"):– The Canadarm2

R. Gillett, P.Eng. FEC (2017)

What is Engineering?(cont)

• Engineers (usually) produce something, whereas Scientists produce knowledge

• The something performs a function• Often a complex function, many interactions• Usually crucial for human safety and/or return on

a large investment• “Failure is not an option”• How do we ensure success and safety?

• More on this later ……..

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

ECE 496 is important for your career!!!

ECE496 = "Real World" engineering– Directing your skills toward achieving a goal:

• Teamwork• Project planning, tracking• Technical and business communication• Risk management• System design (to a limited extent)• Detailed design

ECE496 - taking it somewhere

Technical knowledge/analysis(most of undergrad)

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Teamwork

Orbital Express Satellite Servicing Demonstration Mission,

Launched February 2007

Why was teamwork essential?- Not enough hours in one lifetime- Teamwork = parallel design activities

Canada's MOST MicrosatelliteCanada's Canadarm2

The Apollo Missions

Most (all) great "engineering feats" were accomplished by large teams of people

Page 4: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

4

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Teamwork Example: My Last Project

NEOSSat: 75 kg Microsatellite to launch in 2010 80 kg Microsatellite to launch in 2011

Team: More than 20 people over 3.5 years5+ years

(i.e. approximately 60 100 person-years)

2012 (maybe 2013)R. Gillett, P.Eng. FEC (2017)

ECE496 The Design Process September 2003

NEOSSat: 74.94 kg Microsatellite, launched 25 February 2013

Team: More than 20 people over 6.5 years

(i.e. more than 160 person-years)

Take-Away Message: Projects and Timelines will change

Teamwork Example: My Current Project

8+

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

The Completed NEOSSat Spacecraft

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

In India before launch

Page 5: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

5

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Launch – 25 February 2013

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Some NEOSSat Test Images

“First light” Image

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Teamwork in Your Project

+

-U1

5

6

7

C2100

n

TL082

4

R910k

R851k

R10

330k

+12V

+12V

RCS10CTransmitter

+12V

GND

5

1

6

Circular PlasticConnector

+12V

R12

10k

R11

510

+

-U1

3

2

1TL082

+15V

8

4

R522k

R451k

R3330

k

+15V

+12V

R710k

R6510

R24k7

IRFZ30

IRFZ30

+12V

7812 C110u25V

+

R1100

k

R13

82k

9

GRN

BLU

BLK

RED

+15V

AUX Input(Grip Enable)

ESTOP

AntennaOutput

Q1

Q2

D1

D2 DIP Switch Settings:3,7 Closed

Others open

D3

RP1

330k

+12V

D4

RP2

1M0

+12V

1N4007

1N4007 C3100

n

- Voltage regulator toaccept 15 Vdc system

voltage

- Comparators withhysteresis needed

- Correct input levelsto RF unit

- Correct connectorpinouts to Unit that I also

built

"Simple_design_by_one_individual"

B0

Transmitter Chip Set

TransmitDelay

Counter(Tx_Delay_Ctr)

TransmitBlock IDCounter

(Tx_Block_ID_Ctr)4-Bit Magnitude

Comparator

TransmitController

Transmit Block Selector

Transmitter Multiplexer

32 + Strobe

32 + Strobe

3

32

32

4

Next_Block

Clear/Disable

5_Blocks

All_Sent

A0

A2

A1

STRBI

RDYI

Clear_Disable

A3

Echo Data (From ReceiverSection)

OTX

'1' '0'

B1 B3

B2

8D0 . .D7D8 . .D39

To/From

Receiver

SectionControl Word Output Enable

ControlWord

3 Rx_Ok , Tx_Enable ,Node_Addressed

Tx_Completed

(2 Additional Strobes for Growth)

ESTOP Out

('A=B')

Phase Lock Loop

Pentium III with Parallel IO card

- Interface Voltage levels- Software Design- CommunicationHandshaking

- Centre Frequency- Tracking Range- Locking Range- Jitter

- Digital Logic / VHDL- Hardware Interface Voltage levels- Firmware/Software Interface Design- Communication Handshaking

Complex Design by Multiple Individuals(like your project!)- Requires a team to complete the job within the “skule” year

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Project Planning/Tracking

Perform Weekly Lawn MaintenanceCut Grass

Cut front lawnCut back lawnCut sides

Trim EdgesTrim property boundariesTrim around gardenTrim around trees

Trim BushesPrune side hedgesPrune back hedge

Case 1: One person does Lawn MaintenancePerform Weekly Lawn Maintenance

Cut GrassCut front lawnCut back lawnCut sides

Trim EdgesTrim property boundariesTrim around gardenTrim around trees

Trim BushesPrune side hedgesPrune back hedge

Case 2: Two people do the same, each with their own equipment

A team of two:

[By adding team members, the project progresses faster ...

No Teamwork -one person

Page 6: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

6

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Perform Weekly Lawn MaintenanceCut Grass

Cut front lawnCut back lawnCut sides

Trim EdgesTrim property boundariesTrim around gardenTrim around trees

Trim BushesPrune side hedgesPrune back hedge

Case 3: Three people do the same but can’t ‘Trim’ until the grass is cut (alogical dependency)

The "critical path" is the job, or sequence of tasks, that takes the longest time and drives the completion date. - This limits how fast the team can

complete the job, regardless how many people are added

... but not always ]

Project Planning/Tracking

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Teamwork Requires Communication and Organization

• All team members work toward the same goal

• Each member working on separate portions– In parallel– No duplication of effort

• Integrated portions will work together correctly – Correct interfaces, functions, and performance

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Technical/Business Communication

• Engineers and engineering companies:

– Create proposals and project summaries– Produce and capture technical designs– Conduct design reviews– Report progress to customers (“Progress reports”)– Present project overviews to clients, conferences

and their management• Seminars and/or Conference posters

– Give project demonstrations i.e. All of the activities in ECE496 R. Gillett, P.Eng. FEC (2017)

ECE496 The Design Process September 2003

System Design Process:“Getting the team to design one solution”

• A process for developing team-based designGoal ”Use Cases” System Requirements Component Requirements Detailed Design Verification (showing you met requirements)

• The "Goal" is the top level (single sentence)• The most famous "Goal" statement in history:

- U.S. President J.F. Kennedy, 25 May 1961 -

"... I believe that this nation should commit itself to achieving the goal, before this decade is out, of landing a man on the Moon and returning him safely to the earth".

Page 7: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

7

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Engineering

Goal(or Mission)

- Top level requirements(function andperformance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

The larger and more complex the system, the more 'levels' to define it

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Engineering

Goal(or Mission)

- Top level requirements(function andperformance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

What you really want/need to do, stated simply

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Engineering

Goal(or Mission)

- Top levelrequirements (function

and performance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

The functions and performance, determined bycalculation or other analyses, that must be achieved inorder to meet the Goal

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Engineering

Goal(or Mission)

- Top level requirements(function and performance)

- Major modules of systemarchitecture defined

- "2nd Tier" requirementsgenerated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

Another iteration of analyzing the functions and performance ofeach building block defined in the above level, by calculation orother analyses, to come up with another more detailed set of thatmust be achieved in order to meet the performance of the higherlevel building blocks

Page 8: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

8

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Engineering

Goal(or Mission)

- Top level requirements(function and performance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system,defined within each module

- "3rd Tier" requirements generated

You guessed it! Yet another iteration of the above, this timeindividually breaking down and analyzing each of the elementsthat were used to defined the above building blocks

Take-Away Message: All requirements, at any level, can be ‘traced’ to the Goal

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Design Process

Requirements Definition and Design:Going "down" the pyramid- Analyzing the important parameters of the selected approach- Defining architectural building blocks for each level ("design")- Defining/calculating verifiable requirements by modeling theperformance needed to meet higher level needs- Repeat for the next level down

Goal(or Mission)

- Top level requirements(function andperformance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

System Design Process

Assembly, Integration and Test:Going "up" the pyramid- Verifying that each completed sub-element will function/performas required to meet the needs of the higher level element fromwhich it was derived (Requirements verified by Test, Review ofDesign, Inspection, et cetera)- Integrate the sub-elements and verify requirements at the nextlevel up

Goal(or Mission)

- Top level requirements(function andperformance)

- Major modules of system architecture defined- "2nd Tier" requirements generated

- Major modules of subsystem's system, defined within each module- "3rd Tier" requirements generated

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Suppose a team of sculptors work together on a sculpture, each doing a separate part ....

Effective teamwork follows a Design Process

Page 9: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

9

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Effective teamwork follows a Design Process

No Design Process(Ineffective Teamwork)

Effective Teamwork(each sculptor knew how his work needs to fit into the full 'system')

- Same eyes- Same nose- Same mouth- Same ear

Both images have:

So, which team hadbetter sculptors?

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Project Example using Requirement-Driven Design

Goal: Use “wall-plug” electrical power to amplify the specified input signal to drive 50Watts rms into a 8-ohm speaker

Input Signal Specification:Approx 80-150 mVrms signal, 40-10,000 Hz, 10kOhm output impedance

“Black Box”

[i.e. We must ignore implementation when defining requirements]

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Requirements permit a team to design "in parallel“(Note that the “design” begins with decomposition of requirements)

Pre-Amplifier StageRequirements:- Input Z: >10kohm- Output Z: < 100 ohm-Gain: 0 to +20 V/V log control- Output DC Offset: < 1 mV- Frequency Response:

-3db at 18kHz, single pole- User Tone Controls: Treble: ±10db notch at 8kHzMid: ±10db notch at 1kHzBass: ±10db notch at 150Hz- Power: ± 12 Vdc, < 200 mA

Gain Stage:Requirements:- Input Z: >1kohm-Output Z: < 20 ohm- Output DC voltage:

< 1 mV- Gain: 15 V/V- Clipping at ± 8 Volts- Frequency Response:-3db at 20kHz- Power: ± 12 Vdc,

< 500 mA

Output Driver Stage:Requirements:- Input impedance: >1kohm- Gain: 2 V/V- Output type:

Class A-B with bias trim **- Output power:

50 Watts into 8 ohm load- Power Supply: 110 Vac,

60 Hz input, ± 12 Vdc,700 mA to other circuitry

Requirement-Driven Design

** Not really a pure requirement, because it dictates implementation, but oh well …

Input signal from Electric Guitar: 80 mV rmsJames Susan David

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Example: Final Design

James' circuit Susan's circuitDavid's circuit

8-ohmspeaker

SignalInput

Power Input(120VAC,

60Hz)

David's circuit2:1

Page 10: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

10

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Alternate “Final Design”(by another team - totally different)

Lisa's circuit* Anne's circuit* * Subsystem requirements would show different decomposition from those shown earlier

8-ohmspeaker

SignalInput

PowerInput

(120VAC,60Hz)

Steven’s circuit*1:4

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Architecture Trade-off

- Both designs satisfy the Goal and Requirements- Both designs are totally different- Both designs use very different technologies

i.e. Solid-State* Amplifier

i.e. Vacuum Tube Amplifier

(* Ancient terminology meaning “it uses transistors, not vacuum tubes”)

R. Gillett, P.Eng. FEC (2017)

What is Engineering?(continued from earlier slide)

• So, again …. how do we ensure success and safety?

– Requirements and their Verification:• Showing a project will be successful before it is

completed• Proving it is successful after completion• All requirements must be verifiable … so you can

prove that the design works, or that it will work

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Requirement Verification

• Engineering is not complete (or fully paid for) until verification is completed for each requirement

• Verification method must be agreed with the customer• Common methods (all within a single project):

– Similarity (e.g. the identical circuit is already working well in another amplifier)

– Review of Design (e.g. no ceramic capacitors used in tone control circuitry)

– Analysis (e.g. “worst case” performance, performance prediction at end-of-life)

– Test (e.g. gain can be tested in the lab using a signal generator and oscilloscope)

Page 11: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

11

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Requirement Verification

• Many contracts use a “Verification Matrix” within a formal document.

• ECE496 now includes this

Requirement ID Requirement

SimilarityReview of

Design Analysis Test1 The item shall be light blue X2 The item shall have a maximum volume of 20cm x 30cm by 100cm X2 The item shall have a maximum mass of 6kg X

3.1 The gain of the amplifier in the unit shall be greater than 50db X3.2 The item shall operate for a minimum of 1 year in Low Earth Orbit X3.3 The item shall have the following maximum power demand: - - - -

3.3a 12 Watts average in standby mode X3.3b 23 Watts average in operational mode X3.3c 31 Watts peak in operational mode X

Requirement Verification Method

Verification Matrix(How you will answer the question: "Prove it!" for each requirement)

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

Risk Management

• How many of you:– Bring more than one pen/pencil to an exam?– Backup important computer files to CD/DVD?– Leave earlier for 9AM exams than for a 9AM

lectures?– Drive a car with one spare tire? Two spares?– ………………. Would not sit at desk #2

• Then you have considered risk

• Risk can impact technical, schedule, or both

Desk #1Desk #2

R. Gillett, P.Eng. FEC (2017) ECE496 The Design Process September 2003

• You undergraduate theory forms the foundation of analysis / technical implementation – this is vital

• ECE496 focuses on organizing this knowledge for successful Engineering projects– Teamwork – Project planning and tracking, Risk management– Design with Requirements, verifying against them– Technical and Business Communication (not “writing”)

• These skills are highly valued in industry

Summary This is your project, your journey…

Page 12: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

12

45

Design Fair (3 nights & final showcase)http://youtu.be/187q3KWycsIasdfcsI

ECE496 Roadmap, Milestones & Deliverables

Sept Nov JanDec MarFeb AprOct2015 2016

draft A

Design Review meeting

Individual Progress Report

Final Report

Oral Presentations

draft Bfinal version

Design Fair

Feb

Registration & background research

Project Proposal

Design Goal

System Requirements& Design

Design & Test Modules

System Integration & Testing

End of term status meeting

January status meeting

47

ECE496 Deliverable Weighting

Start Decide Whatyou must Do Do It End

Proj

ect P

ropo

sal

(fina

l dra

ft)D

esig

n R

evie

w

Indi

vidu

alPr

ogre

ss

Rep

ort/e

val

Ora

l Rep

ort

Fina

l Rep

ort &

D

esig

n Fa

ir

fall spring

15%8%

55%

5%17%

Dec

embe

r rev

iew

Janu

ary

revi

ew

Begin with a good plan …

Maps Equipment Study

terrain Avoid

pitfalls

Page 13: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

13

… to guide the rest of your journey

Design Implementation Testing Presentations Teamwork

Project “Adjustments”

Don’t be afraid to adjust the scope of your project or make major changes (with the blessing of your supervisor)– Many projects are too difficult, many are not

“open-ended” enough or don’t have enough “meat”

These adjustments are best done now. No major penalty for changes made with good reason even later on

50

51

Support Resources

Course website Your supervisor Your administrator The Design Centre (SFB520) Funding support The community

– Your classmates– Friends of Design (alumni)– Other profs, work contacts, networked people

Your Supervisor and Administrator

Supervisor Administrator

Students

• Marking consistency• Engineering design & project planning• Effective technical communication

•The ‘expert client’ •Defining the problem • Getting the technical details ‘right’

•The project

Page 14: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

14

53

Supervisor’s Almanac

Help your supervisor by keeping yourself on track

54

Design Centre

Sandford Fleming, room B520 Borrow equipment, computers, lockers, PCB CAD tools,

soldering station and microscope, wireless transceivers,etc.

Printed Guidance

55

Title Author(s) How to find Approx cost

Designing Engineers: An

Introductory Text

McCahan, Anderson,

Kortshot, Weiss, Woodhouse

Paperback now on Indigo/Amazon,

digital online $94

Engineering Communication:

From Principles to Practice

Irish, Weiss On Indigo/Amazon $64

Why Your Writing Sucks Ross On Amazon $3.50 ($11)

Made to Stick Hunt and Hunt On Amazon, Kobo, Indigo $21

Agile! The Good, the Hype and the Ugly Meyer On Indigo, others

maybe too $36

Protected Information (utorid + pwd)

Blackboard for marks The part of the course website that you already have

used (will use) for registration. Used for– Team registration– Project registration– Report submission– Marked digital reports– Evaluation information– Communications…>> access directly or using the links on main website

56

Page 15: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

15

57

Project Funding

Students contribute up to $100 each Other sources of funding and resources include:

– The ECE Department Design Project Fund. Students apply for this funding around the time of the Design Review.

– Supervisors who contribute out of their own funds, particularly where the student projects will aid their research.

– Industrial sponsors– Product suppliers often subsidize developers and

students

58

Awards / Programs

Gordon Slemon Design Award ($1000) CNIB Hochhausen Prize ($1500) and other specialized

awards Centennial Thesis Awards (2) Certificates of Recognition/Invitation to Final Showcase

Many students get jobs based on their project!

59

Administrator / Section Assignment

Registered students will be assigned a section & administrator before first administrator-marked deliverable

IMPORTANT

Please please please please please

60

Check your UofT email regularly

Page 16: Introductions - ECE496 Administrators · - Comparators with hysteresis needed - Correct input levels to RF unit - Correct connector ... 4-Bit Magnitude Comparator Transmit Controller

16

61

No team / project / supervisor??

After the lecture I will be meeting with all people that do not have a registered

project, including those that do not have a team.

1. People with teams fill in a form, hand it in and leave.

2. People without teams will meet together to form teams, fill in a form and leave.

Next Thursday … Preparing your Proposal

62

Y|Ç