inverter detailed theory

8/19/2019 Inverter Detailed Theory

1/62

Introduction to

CMOS VLSIDesign

MOS devices: static and

dynamic behavior


2/62

MOS equationsSlide 2CMOS VLSI Design

Outline

DC Response

Logic Levels and Noise Margins

Transient Response

Delay Estimation


3/62


Activity

1) If the width of a transistor increases the c!rrent will

increase decrease not change

") If the length of a transistor increases the c!rrent will


#) If the s!pply voltage of a chip increases the ma$im!mtransistor c!rrent will


%) If the width of a transistor increases its gate capacitance will


&) If the length of a transistor increases its gate capacitance will


') If the s!pply voltage of a chip increases the gate capacitanceof each transistor will



4/62


Activity

1) If the width of a transistor increases the c!rrent will


") If the length of a transistor increases the c!rrent will


#) If the s!pply voltage of a chip increases the ma$im!mtransistor c!rrent will


%) If the width of a transistor increases its gate capacitance will


&) If the length of a transistor increases its gate capacitance will


') If the s!pply voltage of a chip increases the gate capacitanceof each transistor will



5/62


DC Response

DC Response( o!t vs* in for a gate

E$( Inverter

+ ,hen in - . /0 o!t - DD

+ ,hen in - DD /0 o!t - . + In etween o!t depends on

transistor si2e and c!rrent

+ 3y 4CL m!st settle s!ch that

Idsn - 5Idsp5

+ ,e co!ld solve e6!ations

+ 3!t graphical sol!tion gives more insight

Idsn

Idsp

o!t

DD

in


6/62


ransistor Operation

C!rrent depends on region of transistor ehavior

7or what in and o!t are nM89 and pM89 in

+ C!toff:

+ Linear: + 9at!ration:


7/62


nMOS Operation

Cutoff Linear Saturated

gsn ; gsn 0

dsn ;

gsn 0

dsn 0

Idsn

Idsp

o!t

DD

in


8/62


nMOS Operation


gsn ; tn gsn 0 tn

dsn ; gsn + tn

gsn 0 tn

dsn 0 gsn + tn

Idsn

Idsp

o!t

DD

in


9/62


nMOS Operation


gsn ; tn gsn 0 tn

dsn ; gsn + tn

gsn 0 tn

dsn 0 gsn + tn

Idsn

Idsp

o!t

DD

in

gsn - in

dsn - o!t


10/62


nMOS Operation


gsn ; tn

in ; tn

gsn 0 tn

in 0 tn

dsn ; gsn + tn

o!t ; in / tn

gsn 0 tn

in 0 tn

dsn 0 gsn + tn

o!t 0 in / tn

Idsn

Idsp

o!t

DD

in

gsn - in

dsn - o!t


11/62


pMOS Operation


gsp 0 gsp ;

dsp 0

gsp ;

dsp ;

Idsn

Idsp

o!t

DD

in


12/62


pMOS Operation


gsp 0 tp gsp ; tp

dsp 0 gsp + tp

gsp ; tp

dsp ; gsp + tp

Idsn

Idsp

o!t

DD

in


13/62


pMOS Operation


gsp 0 tp gsp ; tp

dsp 0 gsp + tp

gsp ; tp

dsp ; gsp + tp

Idsn

Idsp

o!t

DD

in

gsp - in / DD

dsp - o!t / DD

tp ; .


14/62


pMOS Operation


gsp 0 tp

in 0 DD < tp

gsp ; tp

in ; DD < tp

dsp 0 gsp + tp

o!t 0 in / tp

gsp ; tp

in ; DD < tp

dsp ; gsp + tp

o!t ; in / tp

Idsn

Idsp

o!t

DD

in

gsp - in / DD

dsp - o!t / DD

tp ; .


15/62


I!V Characteristics

Ma=e pM89 is wider than nM89 s!ch that βn - βp

gsn&

gsn%

gsn#

gsn"

gsn1

gsp&

gsp%

gsp#

gsp"

gsp1

DD

/DD

dsn

/dsp

/Idsp

Idsn

.


16/62


Current vs" Vout# Vin

in&

in%

in#

in"

in1

in.

in1

in"

in#

in%

Idsn

5Idsp

5

o!t

DD


17/62


Load Line Analysis

in&

in%

in#

in"

in1

in.

in1

in"

in#

in%

Idsn

5Idsp

5

o!t

DD

7or a given in(

+ >lot Idsn Idsp vs* o!t

+ o!t m!st e where 5c!rrents5 are e6!al in

Idsn

Idsp

o!t

DD

in


18/62


Load Line Analysis

in.

in.

Idsn

5Idsp

5

o!t

DD

in - .


19/62


Load Line Analysis

in1

in1I

dsn 5I

dsp5

o!t

DD

in - .*"DD


20/62


Load Line Analysis

in"

in"

Idsn

5Idsp

5

o!t

DD

in - .*%DD


21/62


Load Line Analysis

in#

in#

Idsn

5Idsp

5

o!t

DD

in - .*'DD


22/62


Load Line Analysis

in%

in%

Idsn

5Idsp

5

o!t

DD

in - .*?DD


23/62


Load Line Analysis

in&

in.

in1

in"

in#in%

Idsn

5Idsp

5

o!t

DD

in - DD


24/62


Load Line Summary

in&

in%

in#

in"

in1

in.

in1

in"

in#

in%

Idsn

5Idsp

5

o!t

DD


25/62


DC rans$er Curve

Transcrie points onto in vs* o!t plot

in&

in%

in#

in"

in1

in.

in1

in"

in#

in%

o!t

DD

C

o!t

.

in

DD

DD

@ 3

DE

tn

DD

A" DD


26/62


Operating Regions

Revisit transistor operating regions

C

o!t

.

in

DD

DD

@ 3

DE

tn DDA" DD


27/62


Operating Regions

Revisit transistor operating regions

C

o!t

.

in

DD

DD

@ 3

DE

tn DDA" DD


28/62


%eta Ratio

If βp A βn ≠ 1 switching point will move from DDA" Called skewed gate

8ther gates( collapse into e6!ivalent inverter

o!t

.

in

DD

DD

.*&

1"

10 p

n

β

β =

0.1 p

n

β

β =


29/62


&oise Margins

Bow m!ch noise can a gate inp!t see efore it does

not recogni2e the inp!t:

Indeterminate

Region

NML

NMB

Inp!t Characteristics8!tp!t Characteristics

8B

DD

8L

ND

IB

IL

Logical Bigh

Inp!t Range

Logical Low

Inp!t Range

Logical Bigh

8!tp!t Range

Logical Low

8!tp!t Range


30/62


Logic Levels

To ma$imi2e noise margins select logic levels at

DD

in

o!t

DD

βpAβ

n 0 1

in

o!t

.


31/62


Logic Levels

To ma$imi2e noise margins select logic levels at

+ !nity gain point of DC transfer characteristic

DD

in

o!t

8B

DD

8L

IL

IB

tn

nity ain >oints

9lope - /1

DD

/

5tp5

βpAβ

n 0 1

in

o!t

.


32/62


ransient Response

DC analysis tells !s o!t if in is constant

Transient analysis tells !s o!tt) if int) changes

+ Re6!ires solving differential e6!ations

Inp!t is !s!ally considered to e a step or ramp + 7rom . to DD or vice versa


33/62


Inverter Step Response

E$( find step response of inverter driving load cap

0( )

(

)

)

(

o

i

ut

n

out

V t t

t

V

t

V

d

d

t

=

< =

=

inEt)

o!t

Et)C

load

Idsn

Et)


34/62




0

0

( )

( )

( )

( )

ou

DDin

t

out

u t t V

d

d

t

t t

V t

V

V

t

=

=<

−

=

inEt)

o!t

Et)C

load

Idsn

Et)


35/62




0

0(

( ))

(

(

)

)

DD

Do

i

D

o t

n

ut

u

V t

u t t V

V

d

d

t

t

V

V

t

t

= −

=<

=

inEt)

o!t

Et)C

load

Idsn

Et)


36/62




0

0

( )

( )

( )

(

(

)

)

DD

DD

loa

d

ou

i

d

t

o

n

ut sn

V

V

u t t V

t t

V t

V

d

dt C

t

I t

= −

=

= −

<

0

( ) DD t out

ou

ds

t DD t

n I t V V

V V V

V t t ≤= > −

< −

inEt)

o!t

Et)C

load

Idsn

Et)


37/62




0

0

( )

( )

( )

(

(

)

)

DD

DD

loa

d

ou

i

d

t

o

n

ut sn

V

V

u t t V

t t

V t

V

d

dt C

t

I t

= −

=

= −

<

( )0

2

2

0

2)

)

(( )

( DD DD t

DD

out

out

out out D t

n

t

ds

D

I V

t t

V V V V

V V V V V

t

V t V t

β

β

≤

= − > − − − < − ÷

inEt)

o!t

Et)C

load

Idsn

Et)


38/62




0

0

( )

( )

( )

(

(

)

)

DD

DD

loa

d

ou

i

d

t

o

n

ut sn

V

V

u t t V

t t

V t

V

d

dt C

t

I t

= −

=

= −

<

( )0

2

2

0

2)

)

(( )

( DD DD t

DD

out

out

out out D t

n

t

ds

D

I V

t t

V V V V

V V V V V

t

V t V t

β

β

≤

= − > − − − < − ÷

o!t

Et)

inEt)

t.

t

inEt)

o!t

Et)C

load

Idsn

Et)


39/62


Delay De$initions

tpdr (

tpdf (

tpd(

tr (

tf ( fall time


40/62


Delay De$initions

tpdr ( rising propagation delay

+ 7rom inp!t to rising o!tp!t crossing DDA"

tpdf ( falling propagation delay

+7rom inp!t to falling o!tp!t crossing DDA"

tpd( average propagation delay

+ tpd - tpdr < tpdf )A"

tr ( rise time

+ 7rom o!tp!t crossing .*" DD to .*? DD

tf ( fall time

+ 7rom o!tp!t crossing .*? DD to .*" DD


41/62


Delay De$initions

tcdr ( rising contamination delay

+ 7rom inp!t to rising o!tp!t crossing DDA"

tcdf ( falling contamination delay

+ 7rom inp!t to falling o!tp!t crossing DDA" tcd( average contamination delay

+ tpd - tcdr < tcdf )A"


42/62


Simulated Inverter Delay

9olving differential e6!ations y hand is too hard

9>ICE sim!lator solves the e6!ations n!merically

+ ses more acc!rate I/ models tooF

3!t sim!lations ta=e time to write

E)

.*.

.*&

1*.

1*&

"*.

tEs).*. "..p %..p '..p ?..p 1n

tpdf

- ''ps tpdr

- ?#psin

o!t


43/62


Delay 'stimation

,e wo!ld li=e to e ale to easily estimate delay + Not as acc!rate as sim!lation

+ 3!t easier to as= G,hat if:H

The step response !s!ally loo=s li=e a 1st order RC

response with a decaying e$ponential* se RC delay models to estimate delay

+ C - total capacitance on o!tp!t node

+ se effective resistance R

+ 9o that tpd - RC Characteri2e transistors y finding their effective R

+ Depends on average c!rrent as gate switches


44/62


RC Delay Models

se e6!ivalent circ!its for M89 transistors

+ Ideal switch < capacitance and 8N resistance

+ nit nM89 has resistance R capacitance C

+ nit pM89 has resistance "R capacitance C

Capacitance proportional to width

Resistance inversely proportional to width

=g

s

dg

s

d

=C=C

=CRA=

=g

s

d

g

s

d

=C

=C

=C

"RA=


45/62


'(ample: )!input &A&D

9=etch a #/inp!t N@ND with transistor widths chosento achieve effective rise and fall resistances e6!al to

a !nit inverter R)*


46/62




a !nit inverter R)*


47/62




a !nit inverter R)*

#

#

"""

#


48/62


)!input &A&D Caps

@nnotate the #/inp!t N@ND gate with gate anddiff!sion capacitance*

" " "

#

#

#


49/62


)!input &A&D Caps


" " "

#

#

##C

#C

#C

#C

"C

"C

"C

"C

"C

"C

#C

#C

#C

"C "C "C


50/62


)!input &A&D Caps


C

#C

#C#

#

#

"""

&C

&C

&C


51/62


'lmore Delay

8N transistors loo= li=e resistors

>!ll!p or p!lldown networ= modeled as RC ladder

Elmore delay of RC ladder

R1

R"

R#

RN

C1

C"

C#

CN

( ) ( )

nodes

1 1 1 2 2 1 2... ...

pd i to source i

i

N N

t R C

R C R R C R R R C

− −≈

= + + + + + + +∑


52/62


'(ample: *!input &A&D

Estimate worst/case rising and falling delay of "/inp!t N@ND driving h identical gates*

h copies

"

"

""

3

@

$

J


53/62



Estimate rising and falling propagation delays of a "/inp!t N@ND driving h identical gates*

h copies'C

"C"

"

""

%hC

3

@

$

J


54/62




h copies'C

"C"

"

""

%hC

3

@

$

J

R

E'


55/62




h copies'C

"C"

"

""

%hC

3

@

$

J

R

E'


56/62




h copies'C

"C"

"

""

%hC

3

@

$

J


57/62




h copies'C

"C"

"

""

%hC

3

@

$

J

pdf t =E'


58/62




h copies'C

"C"

"

""

%hC

3

@

$

J

( ) ( ) ( ) ( )( )

2 2 22 6 4

7 4

R R R pdf t C h C

h RC

= + + + = +

E'


59/62


Delay Components

Delay has two parts

+ Parasitic delay

K ' or RC

K Independent of load

+ Effort delay

K %h RC

K >roportional to load capacitance


60/62


Contamination Delay

3est/case contamination) delay can e s!stantiallyless than propagation delay*

E$( If oth inp!ts fall sim!ltaneo!sly

'C

"C"

"

""

%hC

3

@

$

J

R

E'


61/62


C

#C

#C#

#

#

"""

#C

"C"C

#C#C

IsolatedContacted

Diff!sionMergedncontacted

Diff!sion

9haredContacted

Diff!sion

Di$$usion Capacitance

we ass!med contacted diff!sion on every s A d* ood layo!t minimi2es diff!sion area

E$( N@ND# layo!t shares one diff!sion contact

+ Red!ces o!tp!t capacitance y "C

+ Merged !ncontacted diff!sion might help too


62/62

Layout Comparison

,hich layo!t is etter:

@

DD

ND

3

J

@

DD

ND

3

J

inverter detailed theory

Documents