irfu saclay 3d-maps design iphc / irfu collaboration christine hu-guo (iphc) outline 3d-maps...

7
irfu sacla y 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline 3D-MAPS advantages Why using high resistivity substrate 3 types of 3D-MAPS design

Upload: maximillian-stevens

Post on 31-Dec-2015

216 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

irfu

saclay

3D-MAPS Design IPHC / IRFU collaboration

Christine Hu-Guo (IPHC)

Outline 3D-MAPS advantages Why using high resistivity substrate 3 types of 3D-MAPS design

Page 2: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 211-14/10/2009 Ecole microélectronique de l'IN2P3

Using 3DIT to improve MAPS performances

3DIT are expected to be particularly beneficial for MAPS : Combine different fabrication processes Resorb most limitations specific to 2D MAPS

Split signal collection and processing functionalities, use best suited technology for each Tier :

Tier-1: charge collection system Epitaxy (depleted or not) ultra thin layer X0 Tier-2: analogue signal processing analogue, low Ileak, process (number of metal layers)

Tier-3: mixed and digital signal processing Tier-4: data formatting (electro-optical conversion ?)

digital process (number of metal layers)feature size fast laser driver, etc.

Analog Readout Circuit

Diode

Pixel Controller,

A/D conversion

Pix

el C

on

tro

ller

, C

DS

Digital

Analog

Sensor

~< 50 µmAnalog Readout

Circuit

Diode

~ 20 µm

Analog Readout Circuit

Diode

Analog Readout Circuit

Diode

TSV

2D - MAPS 3D - MAPS

IPHC-DUT [email protected] 714-18/01/2008

iPHC

Metal layers

Polysilicon

P-Well N-Well P-Well

N+ N+ P+ N+

Dielectric for insulation and passivation

Charged particles

100% efficiency.

Radiation

--

--

--

- ++

+++

++

- +- +- +

P-substrate (~100s m thick)

P-epitaxial layer(up to to 20 m thick)

Potential barriers

epi

sub

NN

lnq

kTV

Sensor tier = MAPS integration 1st level amplification

30

-40

µm

Radiation hard Cluster S/N

Page 3: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 311-14/10/2009 Ecole microélectronique de l'IN2P3

High resistivity sensitive volume faster charge collection

Exploration of a VDSM technology with depleted (partially ~30 µm) substrate: Project "LePix" driven by CERN for SLHC trackers (attractive for CBM, ILC and CLIC Vx

Det.) Exploration of a technology with high resistivity thin epitaxial layer

XFAB 0.6 µm techno: ~15 µm EPI ( ~ O(103).cm), Vdd = 5 V (MIMOSA25)

Benefit from the need of industry for improvement of the photo-sensing elements embedded into CMOS chip

For comparison: standard CMOS technology, low resistivity P-epi

high resistivity P-epi: size of depletion zone size is comparable to the P-epi thickness!

TCAD Simulation (by A. DOROKHOV)15 µm high resistivity EPI compared to 15 µm standard EPI

Page 4: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 411-14/10/2009 Ecole microélectronique de l'IN2P3

Landau MP (in electrons) versus cluster sizeLandau MP (in electrons) versus cluster size0 neq/cm²

0.3 x 1013 neq/cm²

1.3 x 1013 neq/cm²

3 x 1013 neq/cm²

MIMOSA25 in a high resistivity epitaxial layer

20 μm pitch, + 20°C, self-bias diode @ 4.5 V, 160 μs read-out time Fluence ~ (0.3 / 1.3 / 3·)1013 neq/cm2 Tolerance improved by > 1 order of mag. Need to confirm det (uniformity !) with beam tests

16x9

6

Pit

ch 2

0µm

MIMOSA25

To compare: «standard» non-depleted EPI substrate: MIMOSA15 Pitch=20µm, before and after 5.8x1012 neq/cm2

saturation -> >90 % of charge is collected is 3 pixels -> very low charge spread for depleted substrate

Page 5: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 511-14/10/2009 Ecole microélectronique de l'IN2P3

IPHC 3D-MAPS: Self Triggering Pixel Strip-like Tracker (STriPSeT)

Combine Tezzaron/Chartered 2-tiers process with XFAB high resistivity EPI process

Tier-1: XFAB, 15 µm depleted epitaxy ultra thin sensor!!! Depleted Fast charge collection (~5ns) should be radiation tolerant For small pitch, charge contained in less than two pixels Sufficient (rather good) S/N ratio defined by the first stage “charge amplification” ( >x10) by capacitive coupling to the second stage

Tier-2: Shaperless front-end: (Pavia + Bergamo) Single stage, high gain, folded cascode based charge amplifier, with a current source in the feedback loop

Shaping time of ~200 ns very convenient: good time resolution Low offset, continuous discriminator

Tier-3: Digital: Data driven (self-triggering), sparsified binary readout, X and Y projection of hit pixels pattern

Matrix 256x256 2 µs readout time

Tier-1 Tier-2 Tier-3

Cd~10fF

G~1

Cc=100fF

Cf~10fF off <10 mV

Digital RD

Vth

Ziptronix (Direct Bond Interconnect, DBI®*)

Tezzaron (metal-metal (Cu)

thermocompression) DBI® – Direct Bond Interconnect, low temperature CMOS compatible direct oxide bonding with scalable interconnect for highest density 3D interconnections (< 1 µm Pitch, > 108 /cm² Possible)

W. DULINSKI, A. DOROKHOV, F. MOREL, G. BERTOLONE, X. WEI, …

20 µm

Tier 2

Page 6: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 611-14/10/2009 Ecole microélectronique de l'IN2P3

IPHC 3D-MAPS Delayed R.O. Architecture for the ILC Vertex Detector

Try 3D architecture based on small pixel pitch, motivated by : Single point resolution < 3 μm with binary output Probability of > 1 hit per train << 10 % 12 μm pitch :

sp ~ 2.5 μm

• Probability of > 1 hit/train < 5 %

Split signal collection and processing functionalities : Tier-1: A: sensing diode & amplifier, B: shaper & discriminator Tier-2: time stamp (5 bits) + overflow bit & delayed readout

Architecture prepares for 3-Tier perspectives : 12 µm

~1 ms ~1 ms~200 ms

Acquisition Readout

Y. FU, A. BROGNA, A. DOROKHOV, C. COLLEDANI, C. HU, …

Detection diode

or Q injection

Amplifier

NMOS only

Amp.+Shaper

Discriminator

Hit identification

12 µ

m

24 µm

5 bits (7?) Time Stamp

2nd hit flag

Delayed Readout

Tier 1 Tier 2A B

future+Detection diode

& Amp

ASD

TS & R.O.

12 µm

Page 7: Irfu saclay 3D-MAPS Design IPHC / IRFU collaboration Christine Hu-Guo (IPHC) Outline  3D-MAPS advantages  Why using high resistivity substrate  3 types

IRFU - IPHC [email protected] 711-14/10/2009 Ecole microélectronique de l'IN2P3

IRFU & IPHC 3D-MAPS: RSBPix

FAST R.O. architecture aiming to minimise power consumption Subdivide sensitive area in ”small” matrices

running INDIVIDUALLY in rolling shutter mode Adapt the number of raws to required frame r.o. time

few µs r.o. time may be reached (???)

Planned also to connect this 2 tier circuit to XFAB detector tier

Building Blocks: PLL, 8b/10b, Bias DAC, Pre-Amplifier, Buffer….

MOSCAP (20fF)

Vclp2

PWRON_D

MOSCAP

Vclp2

PWRON_D

Latch

Latch

Clamp1 Clamp4

Vclp2

Vclp2

Clamp0

Track

CS CS

Clamp

MOSCAP (100fF)

Vclp1+Vth

PWRON_A

Vrst

Av ~ 4

CS

Tier-1: NMOS only Tier-2

Digital Memory

and

Digital Readout

DiscriminatorDREADLATCH_D

Y. DEGERLI, W. DULINSKI, … (Tier-1)

20µm