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May 4, 2011 1 Is Advanced Verification for FPGA based Logic really needed? May 2, 2012 By Nir Weintroub Verisense Ltd.

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Page 1: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 1

 Is Advanced Verification for FPGA 

based Logic really needed?

May 2, 2012

 ByNir Weintroub Verisense Ltd.

Page 2: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 2

Is FPGA Design Simpler than ASIC Design ?

Verisense Ltd.

NO ! 

2

FPGA has similar complexity issues to ASIC: 

• High-complexity applications

• Large gate-count applications

• High-quality application 

Page 3: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 3

So why are ASIC verification Methodologies much more progressive 

than FPGA ones ???

Page 4: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 4

FPGA Vs. ASIC• Biggest advantage: Re-programmable

– Fix bugs– Phased product releases– Prototype ASICs– Evolve with specifications– Field upgrades

 

4Verisense Ltd.

Page 5: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 5

FPGA Vs. ASIC• Biggest disadvantage: Re-programmable

– Relied on to fix bugs– Promotes trial-and-error engineering

 

5Verisense Ltd.

Page 6: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 6

FPGA Verification Current Problem

• Productivity issues : – Lab testing has long cycle time(debug 

+reprogramming)– direct testing – Major Manual effort 

Page 7: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 7

FPGA Verification Current Problem

• Quality issues : – Using direct testing, One can only check scenarios 

that he/she think of– Did we checked everything ?  No visibility of the 

real test quality – Certification (e.g. DO 254) !

Page 8: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 8

Here is what we are looking for ….

• Minimize cycle time

• Maximize quality 

• Certify conformance (e.g. DO254)

• Maximum visibility of the testing coverage

8Verisense Ltd.

Page 9: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 9

Here is what we are looking for …(Cont.)

• Debug environment

• Easy recreation of issues founded in the LAB

Verisense Ltd.

Page 10: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 10

What is the New Verification Methodology?

CDV : Coverage Driven Verification 

The idea: The Verification environment is an automatic machinethat uses constrained random generation of scenariosand configurations in order to exercise the design and verify (automatically) that the design is working according to the architecture specification. Verification is done after achieving pre-defined

 coverage goals

Verisense Ltd.

Page 11: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 11

What are the Coverage Goals? 

• • Checking

Definition of the functionalityrequired to be tested

to achieve the quality goals

Page 12: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 12

For Example :

Verisense Ltd.

Dut

#1 #2 #3Out I/F

CPU I/F

Pseudo image processing design with the next features :

• Pixel Input 8-10-12 bit • Pixel manipulation : 

• “7-boom”• Bitwise “not”• Bitwise “or” and “and”

• Simple Data/Valid protocol• All three phases are the same• Instead Matlab , Perl

Page 13: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 13

And Now : 

The 

DEMO !

Verisense Ltd.

Page 14: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 14

Constrained Random Generation ?

– Improves test coverage by automatically generating values.

– Reduces number of tests since a single test can check many scenarios.

– Random generation is not so useful without constraints.

Page 15: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 15

TEST

 FLO

W

So, How will our new environment will look like!?

Dut In 

I/F

Matlab #1 Matlab #2 Matlab #3

Mon #1

Mon #2

Mon #3

#1 #2 #3Out I/F

CPU I/F

SB#1

SB#2

SB#3

Test Configuration

Input Gen.

Driver

Device Configuration CPU

Driver

Given:

DUT

Matlab Model

Pre-Run Gen

Matlab Run

Simulation

Test EndPASSED/FAIL

Page 16: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 16

Now, Do we have all we need ? 

Page 17: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 17

Coverage measurement tool

This independent tool will answer the next question : – Which of the coverage goals was achieved ? – Which functionality we didn’t check yet ? – Project progress ? 20% , 80% – Can we get into lab ? – If yes, What are the exact features we can check in 

lab ? 

Page 18: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 18

And Now : 

The 

DEMO !

Coverage results are not perfect!!!

Page 19: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 19

And Now : 

The 

DEMO !

19Verisense Ltd.

Let’s analyze the ‘holes’

Page 20: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 20

And Now : 

The 

DEMO !

20Verisense Ltd.

Now , Integration is waiting for our FPGA.

Page 21: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 21

What about the cost ?

Verisense Ltd. 21

What is the cost of one bug in the lab ?

Debug : at least 5 hours of at least 2people

Recompile : another 5 hours Re-Run : another 1 hours

Page 22: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 22Verisense Ltd. 22

Bottom Line : 1 bug =~ 2 WD

30 bugs =~ 60WD =>

 3 working Months

Page 23: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 23Verisense Ltd. 23

less expensive

Advanced Verification is

will catch much more than 30 bugs!

Page 24: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 24Verisense Ltd. 24

What is the cost of one bug  that was not detected 

in the lab?

Page 25: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 25

 Is Advanced Verification for FPGA 

based Logic really needed?

May 2, 2012

Of Course !

Page 26: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 26Verisense Confidential

Verisense Background• The largest design and verification services company in Israel• Company founded in 2007• Managed by seasoned managers with many years experience in the 

industry• Currently employ over 60 employees and growing• Customers to date include:

Page 27: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 27

And remember :

Page 28: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 28

1974

Brian W. Kernighan• Debugging is twice as hard as writing the code in the 

first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it.

Page 29: Is Advanced Verification for FPGA based Logic needed

May 4, 2011 29

The END!


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