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art 1 of this article se r i es, “Calibra-tion and Dynamic Matching in Data Converters: Part 1:

Linearity Calibration and Dynamic-Matching Techniques,” considered the calibration of digital-to-analog convert-ers (DACs), dynamic element match-ing, and the calibration of pipelined

analog-to-digital converters (ADCs). In this second part, the calibration of time-interleaved ADCs is covered first. Then challenges created by back-ground calibration in the architectures described in both parts are covered. Fi-nally, conclusions are drawn based on the examples in both parts.

Calibration of Time-Interleaved ADCsFigure 1 shows a block diagram of a time-interleaved ADC [1]. This struc-

ture uses M channels in parallel, increasing the overall sampling and conversion rates by a factor of Mwithout needing a new process tech-nology. However, the performance of time-interleaved ADCs is sensitive to the following errors [1]–[6].

Offset mismatches among the ADC channels contribute a periodic pattern that is added to the output of the ADC array. In the frequency domain, this pattern appears as undesired tones at integer multiples of the channel

P

Calibration and Dynamic Matching in Data Converters

Kenneth C. Dyer, John P. Keane, and Stephen H. Lewis

Part 2: Time-interleaved analog-to-digital converters and background-calibration challenges

image licensed by ingram publishing

Digital Object Identifier 10.1109/MSSC.2018.2844609

Date of publication: 13 August 2018

62 summer 20 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

sampling rate / .f MS Gain mismatches between the parallel channels cause amplitude modulation of the input samples by the sequence of channel gains. In the frequency domain, this mismatch causes scaled copies of the input signal spectrum to appear cen-tered around integer multiples of the channel sampling rate. Ideally, each channel should sample T seconds after the previous channel, where

/T f1 S= and fS is the overall sam-pling rate. Deviations from the ideal sampling instants can be represented as a sequence of sample-time errors that phase modulate the input .Vin In the frequency domain, this modula-tion produces undesired components at the same frequencies as the errors from gain mismatch. However, the

magnitudes of these components are now proportional to the input frequen- cy because they are proportional to the slope of the input. Background calibration techniques that overcome these errors are described next.

Random Chopper-Based Background Offset CalibrationFigure 2 shows a block diagram of a random chopper-based offset ca -libration for one channel in a time-in-terleaved ADC [6]. A related tech ni que was independently developed [7]. The notch filter at the output digitally re -moves the offset from the sample-and-hold amplifier (SHA) and the ADC in a channel [8]. However, if the ana-log input is connected directly to the SHA, bypassing the multiplier (chop-

per) shown in the chopping SHA, notches in the input spectrum are in-troduced at integer multiples of the channel sample rate. To avoid intro-ducing these notches, two choppers are used, one in the analog domain at the input and the other in the digital domain at the output. These chop-pers multiply by a pseudorandom binary signal [ ],C n where n is a time index. [ ]C n 1!= and has zero mean. Also, it is uncorrelated with the analog input. The input chopper spreads the input over all frequen-cies. Then the notch filter removes the dc component, which stems mainly from offsets in the SHA and the ADC. Finally, the output chopper shifts the input signal back to the frequen-cies where it started. The part of the output that comes from the input is not affected much by this process for two reasons. First, it is chopped twice, and [ ] .C n 12 = Second, a tiny value of n is used in practice to limit the steady-state variation at the notch-filter output to a negligible level. With a tiny value of ,n the bandwidth of the notch filter is very small. This tech-nique is applied to each channel in the time-interleaved array to over-come the effect of offset mismatch. The beauty of this technique is that it works for any input that is not cor-related with the chopping signal. This technique has been used in commer-cial practice [9], [10].

Background Gain CalibrationFigure 3 shows a block diagram of the gain calibration for one channel in a time-interleaved ADC [8]. The random-number generator (RNG) produces a dither signal equal to 1! with zero mean and uncorrelated with the input. The dither is converted to the ana-log domain by a 1-bit DAC, added to the input, and digitized along with the input by the ADC. The ADC output is multiplied by ,G which is the output of an accumulator. Then the dither is subtracted from the multiplier output, producing ,Dout which is the calibrat-ed output of the channel. The accumu-lator operates in a negative feedback loop and finds G to eliminate the

Vin(t )

AnalogDemux

fS fS = 1/T

fS /M

ADC1

ADC2

ADCMDigitalMux

Dout(nT)

Figure 1: A block diagram of a time-interleaved ADC.

× ×

C [n ] C [n ]

SHA1 ADC1Analog

Input

Chopping SHA

S1

+Σ

Y1a1

Notch Filter

×

Accum

−

V1

µ

Figure 2: A block diagram of the random chopper-based offset calibration for one channel in a time-interleaved ADC.

The beauty of this technique is that it works for any input that is not correlated with the chopping signal.

IEEE SOLID-STATE CIRCUITS MAGAZINE summer 20 18 63

correlation between Dout and the dith-er by forcing the same gain to be ap-plied to the dither through two paths. The first path is through the DAC, the ADC, and the multiplication by .G The second path is directly from the RNG to the subtractor that produces .Dout The gain of the first path is the DAC gain,

,GD times the ADC gain, ,GA times .G The gain of the second path is just one. In other words, ·G GA (the cali-brated gain of the channel) is forced to equal /G1 D (the reciprocal of the DAC gain). If the same DAC is used to calibrate all the channels in the time-interleaved array, the gain mismatch between the channels is eliminated. This technique has been used in com-mercial practice [10].

Background Calibration for Timing ErrorsFigure 4 shows a block diagram of a time-interleaved ADC with an extra flash ADC for timing calibration [11]. Each of the interleaved channels oper-ates at / ,f MS where M is the number of interleaved channels. The extra flash ADC operates at ,fS which is the output rate for all the interleaved channels in parallel. Timing errors in the interleaved channels are sensed by correlating the outputs of each channel with the outputs of the flash ADC. Digitally controlled analog delay lines adjust the sample time in each channel to maximize these correla-tions, eliminating the timing errors. An advantage of this calibration tech-nique is that the extra flash ADC only needs 1-bit resolution, which means that it can be built with just a single comparator, reducing power dissipa-tion. A disadvantage of this calibra-tion technique is that it is sensitive to the statistics of the input signal.

Another approach to background timing calibration stems from the fact that the correlation between in-put samples in an ADC is nonzero be-cause the input bandwidth is finite in practice. In particular, the correlation between the current input sample and both the previous sample as well as the next sample can be calculated. Assuming that decreasing the time

between two samples increases the correlation between those samples, the timing can be adjusted through negative feedback to equalize these two correlations [12]. A limitation of this technique is that aliasing causes it to fail in the second Nyquist zone ( /f 2S to fS ) because the current sam-ple is less correlated with the sample closer in time than with the more dis-tant sample in this case.

For example, Figure 5 shows two plots of a sinusoidal input versus time to a two-channel time-interleaved ADC. Each plot labels three samples that are uniformly spaced in time. The odd samples are taken by one channel, and the even samples are taken by the other. Suppose that the even samples are delayed by a timing error in one channel as shown by the arrow above sample 2 in each plot. In Figure 5(a), the input frequency fi is in the first Nyquist zone (close to but less than /f 2S ). In this case, delaying sample 2

makes this sample more correlated with sample 3 than with sample 1 as expected because the delay causes sample 2 to be closer in time to sample 3 than to sample 1. The timing loop described in [12] operates properly in this case. In Figure 5(b), the input frequency fi is in the second Nyquist zone (close to but greater than /f 2S ).

Vin+

Σ ADC ×+

Σ Dout

RNG

−

1-bit DAC

+

GD

GA

×−µ

Accum

G

Figure 3: A block diagram of gain calibration for one channel in a time-interleaved ADC.

Vin (t )

φ1

φ1

φM

φM

ADC1

ADCM

Mux Dout (nT)

Timing CalPhase Gen.ClkI

ClkI

ClkQ

fS

1-bitFlash ADC

Figure 4: A block diagram of a time-interleaved ADC with an extra flash ADC to back-ground calibrate the interleaved channels for timing errors.

1

2

3(a)

(b)1

2

3

Figure 5: Plots of a sinusoidal input versus time with three labeled samples each: (a)

/f f 2i S1 and (b) / .2f f fS i S1 1

64 summer 20 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

In this case, delaying sample 2 makes this sample more correlated with sam-ple 1 than with sample 3 even though the delay causes sample 2 to be closer in time to sample 3 than to sample 1. This characteristic reverses the polar-ity of the timing error estimate in [12], causing the timing calibration to fail because the feedback that con-trols the timing of the even samples becomes positive instead of nega-tive. Being able to adjust the timing correctly with inputs in any Nyquist zone would increase the flexibility of this timing calibration. This problem disappears between fS and /f3 2S but reappears between /f3 2S and ,f2 S and this pattern repeats as the input fre-quency increases.

Figure 6 shows a block diagram of an architecture that overcomes the sensitivity to aliasing and reduces the sensitivity to the statistics of the input signal [13]. Three ADCs are shown. The bottom ADC is one of the interleaved channels, and the top two ADCs are reference channels that can sample at the same time as any interleaved chan-nel. Let e represent the error created when the channel under calibration samples at the wrong time. Then

e D tD=- (1)

where D is the derivative of the input and tT is the sample time error. A digital estimate of e is found by sub-tracting the output of the channel under calibration from the output of .ADC0 The timing error is found adaptively with the least mean square (LMS) update equation:

[ ] [ ]t n t nd tde1

2! nD D

D+ = c m (2)

By the chain rule, / · · ( /de d t e de22 D = ) .d t e D2· ·D =- Also, if e and D are both

positive, (1) shows that tT is negative. So tT has to be increased to reduce .e Therefore,

[ ] [ ]t n t n e D1 2· · ·nD D+ = + (3)

The key point is that the timing error can be found adaptively if the deriv-ative of the input is known accurately enough so that the updates from the LMS algorithm move tT in the correct direction on average.

To estimate the input derivative, the top channel is used. It has an extra resistor RD in series with its sampling switch to reduce its sam-pling bandwidth. The transfer func-tion from Vin to the difference in the inputs of ADCt and ADC0 is

( ) ( )( ( ))D ssCR sC R R

sC R1 1 D

D=+ + +

(4)

where R is the resistance of the sam-pling switch. Since the right side has a zero at ,s 0= it is a measure of the input derivative for a wide range of frequencies from dc to about /(( ) )R R C1 D+ . A digital estimate of

D is found by subtracting the output of ADCt from the output of .ADC0

The back end of Figure 6 implements the LMS update. The accumulator oper-ates inside a negative feedback loop. Since the accumulator operates in the digital domain, it remembers its previ-ous output without loss. Therefore, the accumulator adjusts ,tT which is the timing error in the channel under cali-bration, to drive the average accumulator input ( / )de d t e D2· · · ·2n nD = to zero, which minimizes the mean-squared tim-ing error in the channel under calibration.

The range of input frequencies that can be handled by this technique is not limited by aliasing because the derivative of the input is estimated using the transfer functions of the sampling circuits in front of ADCt and

,ADC0 which are implemented in the analog domain. However, the input frequency range is limited by the two poles in (4).

Flash-Assisted Time-Interleaved ADC CalibrationFigure 7 shows a block diagram of a flash-assisted, time-interleaved ADC. Instead of using an extra parallel channel for calibration, this structure uses a hybrid ADC. The front end is a flash ADC, and the back end is a time-interleaved array of SAR ADCs. The flash ADC not only outputs the most significant bits (MSBs) but also can calibrate the interleaved array without an extra reference channel. An early example of this technique is described in [14]. It background calibrates offset errors in the flash ADC using an extra comparator and offset mismatches in the interleaved array using an extra interleaved channel. Another example is in [15]. It background calibrates timing errors in the interleaved ar-ray by minimizing the variance of

Vin (t )

∆R

∆t

φ0

φ0

φi

C

C

CADCi

ADCt

ADC0

−Σ

D× ×

µ

Accum

Delay

+

+Σ

e

−

Figure 6: A block diagram of one channel in a time-interleaved ADC with two reference channels to background calibrate for timing errors.

Another approach to background timing calibration stems from the fact that the correlation between input samples in an ADC is nonzero because the input bandwidth is finite in practice.

IEEE SOLID-STATE CIRCUITS MAGAZINE summer 20 18 65

the difference between the front- and back-end outputs. Also, it foreground calibrates offset mismatches in the in-terleaved array. A third example uses a folding flash ADC with two inter-leaved channels in the front end to re-duce the required power dissipation at high conversion rates and to increase the maximum conversion rate [16]. Also, offset and timing errors are both background calibrated in this project. Offset errors are handled as in [14]. However, the timing calibration used in [15] is not adequate here because the front end also needs timing cali-bration since it is time interleaved too. The timing calibration is done in the background by using an extra cycle in each channel to compare the timing of its sample clock to that of a reference clock and then making corrections in the analog domain.

Slice-Order ShufflingIn a conventional time-interleaved ADC, M channels are used to increase the conversion rate by a factor of .M If each channel operates at its maxi-mum conversion rate, only one chan-nel is ready to sample and digitize a new input when the time to begin processing that input arrives. In this case, the channels are always se-lected in the same order. Therefore, if the ADC input is periodic, the off-set, gain, and timing errors stemming from interleaving are periodic too. As a result, the errors appear at certain discrete output frequencies with a periodic input. This concentration of errors can limit the spurious-free dy-namic range (SFDR), which is impor-tant in communication applications, where interleaving artifacts from these errors with a strong signal can act as interference to the reception of a weak signal.

One way to overcome this problem is to increase the number of inter-leaved channels without increasing the overall sampling and conversion rate [17], [18]. With MD extra chan-nels, M 1D + channels are ready to sample and process a new input each time a new sampling instant arrives [18]. If one of the available channels is

randomly selected to process the new input, the interleaving artifacts arising with a periodic input are no longer periodic, spreading out the errors in the frequency domain, and improv-ing the SFDR. Also, extra channels are potentially useful for allowing calibra-tion to operate in the background [19] and for yield enhancement.

Disadvantages of slice-order shuf-fling are that the extra channels in-crease both the loading on the input buffer and the required die area. How-ever, if each channel is a successive-approximation-register ADC, its static power dissipation can be negligibly small, leading to little overhead in power dissipation with this technique except as follows. The input buffer dissipates extra power to maintain the

same bandwidth with an increased load. Also, the increase of loading on shared dynamic signals such as clocks increases the power dissipation. This technique has been used in commer-cial practice [20], [21].

First- or Front-Rank SHA Instead of Timing CalibrationFigure 8 shows a block diagram of a time-interleaved ADC with an SHA in front of the entire array. The input SHA is called a first- or front-rank SHA [22]. The main advantage of this structure is that it reduces the jit-ter in the input samples because the first-rank SHA samples all the inputs to be digitized by this ADC. How-ever, the main disadvantage is that the first-rank SHA has high power

Vin (t )

fS

fS /M

SHA

1

AnalogDemux

ADC1

ADC2

ADCMDigitalMux

fS = 1/T

Dout (nT)

Figure 8: A block diagram of a time-interleaved ADC with a first-rank SHA.

Vin (t )

φ1

φ1

φM

φ2

φ

φM

ADC2

ADC1

ADCM

Calib. Dout (nT)

fS

FlashADC O�set Corr.

Timing Corr.ClockGen

Figure 7: A block diagram of a flash-assisted, time-interleaved ADC.

BG calibration has enabled great improvements in the power and area efficiency of data converters, but it has created new challenges too.

66 summer 20 18 IEEE SOLID-STATE CIRCUITS MAGAZINE

dissipation to operate as fast as all the interleaved channels together. This technique has been used recent-ly in a very demanding application instead of calibration to overcome the effects of timing errors [10]. Since this technique is not a type of calibra-tion, the example in [10] shows that calibration does not always offer the best solution to overcome systematic ADC errors.

Analog Calibration of Offset, Gain, and Timing ErrorsFigure 9(a) shows a block diagram of one channel in a time-interleaved array with analog calibration of off-set, gain, and timing errors. Analog calibration has some important ad-vantages, stemming in part from the fact that the errors are corrected be-fore quantization. For example, off-set calibration in the analog domain does not reduce dynamic range, un-like offset calibration in the digital domain [19]. Also, extra bits are not required in each channel to reduce the error below 1 least significant bit (LSB), simplifying the interface to the calibration. In addition, the ana-log calibration of timing errors does not increase the latency because an-

alog timing corrections can be made without waiting to collect the out-puts from all the channels. Also, the analog calibration of timing errors can work both above and below the Nyquist bandwidth limit. However, analog calibration increases design and verification time and requires analog calibration signals to settle, which can make analog calibration slow compared to digital calibration (especially when power dissipation is low). Also, it requires that analog correction circuits are tightly inte-grated with sensitive analog circuits in the data converters under calibra-tion. Finally, moving analog calibra-tion techniques established in one process node to a new node is nor-mally difficult.

Digital Calibration of Offset, Gain, and Timing ErrorsFigure 9(b) shows a block diagram of one channel in a time-interleaved ar-ray with digital calibration of offset, gain, and timing errors. Digital cali-bration simplifies verification and portability to new process nodes. A lso, it reduces the number of changes that are needed in sensitive analog circuits to allow calibration,

and it can scale in advanced process-es. However, digital calibration reduc-es dynamic range. Also, it increases latency, which is a problem in commu-nications applications in which data converters operate in negative feed-back loops because increasing the delay inside a negative feedback loop decreases its phase margin. Finally, digital calibration for timing errors limits the input bandwidth to one Ny-quist zone.

Summary of Offset, Gain, and Timing CalibrationsTable 1 summarizes the type of off-set, gain, and timing calibrations in some time-interleaved ADCs. A trend in changing from analog to digital cali-bration techniques does not appear. In fact, the trend under timing calibra-tion is in the opposite direction, start-ing with the use of a first-rank SHA [22], then changing to analog [23], and then digital calibration [6]. However, most recently, analog calibration is be-ing used again to eliminate the need for complicated digital filters to make small timing corrections [15], [16], [26]. Similarly, a trend in changing from foreground (FG) calibration to background (BG) calibration does not appear in Table 1. This observation is surprising because BG calibration can track variations during normal opera-tion, unlike FG calibration. However, FG calibration is simpler and less ex-pensive than BG calibration. As a re-sult, FG calibration is preferred to overcome errors that are essentially independent of temperature and pow-er supply changes, such as capacitor matching, for example. Also, FG cali-bration is often used with BG calibra-tion to reduce the range over which errors need to be tracked. Finally, FG calibration can overcome the prob-lems considered next.

Challenges Created by Background CalibrationBG calibration has enabled great im-provements in the power and area ef-ficiency of data converters, but it has created new challenges too, described below. Challenges related to assumptions

Vin

Vin

+Σ × ADC Channel Dout

DAC

−Voff

DAC

G

Clock

∆t

(a)

(b)

ADC Channel+

Σ × Dig. Delay Dout

Clock

−

Voff

"

G

"

Voff

"

G

"

∆t

"

Figure 9: A block diagram of one channel in a time-interleaved ADC with (a) analog cali-bration of offset, gain, and timing errors and (b) digital calibration of these errors.

At first, calibration was done only in the analog domain, but now it is done in the analog domain, the digital domain, or both.

IEEE SOLID-STATE CIRCUITS MAGAZINE summer 20 18 67

about the input signal are considered first, followed by those related to the use of subtractive dither.

Challenges Related to Violations of Assumptions about the InputOne problem is that the tracking rates of coefficients adjusted by BG calibration are often dependent on the input signal. This characteristic is strongly disliked by customers. When customers use an ADC with BG calibra-tion, they expect it to operate the same way regardless of the input signal. In reality, many BG calibration algorithms make assumptions about the input sig-nal, which, if not true, can cause slow tracking or, even worse, misconver-gence. For example, many algorithms fail for a dc input signal or one that is mostly static, such as a step input or a slow non-return-to-zero input wave-form. In such cases, the key issue is that the variation in the input signal may not be enough to exercise all the paths in the ADC regularly. Subtractive dither can help solve this problem and is considered again below. A second example is in a time-interleaved ADC when the input has a periodic compo-nent at a multiple of the channel sam-pling rate. This component appears as a possibly different dc signal to each interleaved channel, causing miscon-vergence of some offset-mismatch calibrations unless random chopping is used too. A third example is an in-put that exceeds the full-scale range of an ADC. The resulting output is clipped and can cause miscalibration if it is used to update coefficients. Cali-bration subsystems can be designed to inform customers when these as-sumptions are violated so that user intervention can occur. In general, da-ta-converter designers need to inform customers about all the assumptions regarding the input so customers can design their systems to make sure that the assumptions are satisfied. Custom-ers are often unhappy with this kind of system-level requirement. In fact, some customers choose not to dis-close the characteristics of their input signal to designers for safety or secu-rity purposes.

Tracking Bandwidth with Subtractive DitherFigure 10 shows more details about subtractive dither. Figure 10(a) shows an ADC whose analog input without dither is · ,G Vin where G is the gain of an SHA. This ADC can be consid-ered to be either a stand-alone ADC or the back end of a multistage ADC. The RNG uses a shift register to generate the dither D [27], [28]. The dither is converted to the analog domain by the DAC and subtracted from .Vin Also, the digital output of the ADC is mul-tiplied by the output of an accumula-tor ,W and the dither is added to this product to produce the output Dout of this system. Assuming the DAC and ADC are ideal and ignoring quantiza-tion error,

[( ) · ] ·

· · ·

D V D G W D

V G W Dout in

in e

= - +

= +

(5)

where G W1 ·e = - is the fraction of the dither that remains after sub-tracting it in the analog domain and adding it in the digital domain. The digital output is multiplied by the

dither and scaled by a small scale factor .n The result is fed into an accumulator that operates in a nega-tive feedback loop and adjusts the parameter under calibration. This parameter is called W for the weight applied to the ADC output. The weight is adjusted according to this update equation

[ ] [ ] ( · ·

)

W n W n V G W

D D

1

· ·inn

e

+ = +

+

(6)

where n is a time index. If D is uncor-related with ,Vin the product of V D·in averages to zero. So the accumula-tor operates in an average sense on the last term in (6), which is .D· 2e To reduce this term, W is gradually adjusted as shown in Figure 10(b) to reduce e in .Dout Eventually, calibra-tion or convergence is reached. The time required to converge is .Tcon After convergence, the loop operates in steady state, and W seems to be constant in steady state. However, enlarging the part of the plot after convergence as in Figure 10(b) shows

TAble 1. TyPeS of CAlibrATionS in Some Time-inTerleAveD ADCS.

AuTHor yeAr offSeT GAin TiminG

Poulton [22] 1987 Analog FG Analog FG First-rank SHA

Dyer [19] 1998 Analog BG Analog BG First-rank SHA

Fu [8] 1998 Digital BG Digital BG First-rank SHA

Poulton [23] 2002 Digital FG Digital FG Analog FG

Jamal [6] 2002 Digital BG Digital BG Digital BG

Law [24] 2010 Digital FG Digital BG Digital FG

El-Chammas [11] 2011 Analog FG Analog FG Analog BG

Doris [20] 2011 Analog FG Analog FG NA

Stepanovic [13] 2013 Digital BG Digital BG Analog BG

Janssen [9] 2013 Analog + Digital BG

Analog BG NA

Setterberg [10] 2013 Digital BG Digital BG First-rank SHA

Le Dortz [25] 2014 Digital BG Digital BG Digital BG

Kull [26] 2014 Digital FG Analog FG Analog FG

Lee [15] 2014 Analog FG NA Analog BG

Sung [16] 2015 Analog BG NA Analog BG

NA: Not applicable

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that W is not constant in this region after all. Although the input times the dither is supposed to average to zero, it is not equal to zero all the time, and interference from the input causes the weight to move around in steady state. In steady state, the signal-to-noise ratio (SNR) turns out to be inversely proportional to n ig -noring other errors [29]. As a result, small n is required for high SNR.

Also, in steady state, the bandwidth over which the loop can track varia-tions in the error (arising from temper-ature or power supply variations for example) is inversely proportional to Tcon and proportional to .n In practice, the noise requirements of high-resolu-tion ADCs require n to be tiny, which means that the resulting tracking

bandwidth ends up being very small. To increase the tracking bandwidth, the input component in the signal used to update the accumulator output can be reduced, as described below.

Figure 11 shows a block diagram of an architecture that overcomes this problem by splitting the ADC to be calibrated into two identical halves [30], [31]. The two halves are driven by the same input, and the digital out-puts of the two halves are averaged to produce the overall output. On the other hand, the two halves are given different dither signals, D1 and .D2 The dither used in each half of the ADC can be processed subtractively (added in the analog domain and sub-tracted in the digital domain or vice versa). Also, D1 and D2 are uncor-related with each other and with the input. Then the two outputs are sub-tracted to produce ,Dd which is used to calibrate both halves of the ADC. The key point is that this subtraction significantly reduces the input compo-nent in ,Dd allowing the update step size n and the tracking bandwidth to be greatly increased.

The beauty of this idea is that it requires little extra power dissipation

if the ADC is noise limited. This re-sult stems from the fact that the noise requirements in each half of the ADC are less severe than for the entire ADC because the averaging at the out-put reduces the noise by 3 dB. As a re-sult, the capacitors in each half of the ADC can be two times smaller than the capacitors would have been in the entire ADC. Therefore, the power dissipated in each half of the ADC is approximately half of the power that would have been dissipated in the en-tire ADC without this technique.

Convergence of Coefficients with Subtractive DitherMany ADC calibration schemes use sub-tractive dither. For simplicity, the dither is often binary valued. Unfortunately, with binary-valued dither, the steady-state values to which the calibration coefficients converge depend on the input signal amplitude [32]–[36]. The problem stems from quantization error. In (5), quantization error was ignored. Including quantization error Q gives

· · ·D V G W D Qout in e= + + (7)

When this output is multiplied by the dither, the calibration is supposed to operate on the term .D· 2e In other words, the dither is the main input from the standpoint of the calibration because it is used to measure ADC er-rors. Therefore, measuring the dither amplitude accurately is central to the ability of the calibration to improve the ADC performance. Limited ADC resolution (quantization errors) can interfere with the measurement of the dither amplitude. Since the dither amplitude is normally a small frac-tion of the full-scale range in practice, this problem is worsened by the fact that most of the ADC input range is devoted to handling .Vin When Dout in (7) is multiplied by ,D this interfer-ence stems from the product .Q D· This term may not average to zero because Q is correlated with the ADC input, which includes .D As Vin changes, this term can change the steady-state value to which W in Fig-ure 10(b) converges.

Vin

ADC1

ADC2

D1

D2

+ Σ × Dout

0.5

+ Σ Dd−

+

Figure 11: A two-channel or split ADC architecture.

+Σ GVin ADC

DAC

−

RNG

D+

×+

Σ Dout

×

Accum

W

µ

(a)

(b)

W

n

Enlarge

Tcon

Figure 10: (a) A block diagram of an n-bit ADC with subtractive dither used for back-ground calibration, and (b) a plot of coefficient under calibration versus time index n.

IEEE SOLID-STATE CIRCUITS MAGAZINE summer 20 18 69

When ,V 0in - the dither is essen-tially the entire ADC input. If binary dither is used and the two dither am-plitudes are equally likely, then the average of the Q D· term is

( )/Q D Q D Q D 2· · ·1 1 2 2= + (8)

where D1 and D2 are the two ampli-tudes of the binary dither and Q1 and Q 2 are the corresponding quantiza-tion errors. For example, ·Q D 0= if the two quantization errors happen to be zero for the given D1 and .D2

On the other hand, Q1 and Q 2 could be anywhere between LSB/2! for two slightly different dither ampli-tudes. In contrast, when Vin is large and time varying but uncorrelated with ,D Vin acts to dither the dither signal, changing the sum in (8) to an integral that gives Q D· between these extremes. As a result, Q D· can experience significant variation as Vin changes in this case.

This variation can be reduced by using uniformly distributed dither whose peak-to-peak amplitude is big-ger than 1 LSB. In this case, the sum in (8) is again changed to an inte-gral even in the case when .V 0in - In practice, however, this solution is difficult to implement because using subtractive dither requires that the dither is known in both the analog and digital domains. As a result, mul-tilevel subtractive dither has been used as an approximation to uni-formly distributed dither [37]–[39]. To avoid the need to use a large num-ber of dither levels in any one stage of a pipelined ADC, the dither can be injected progressively in successive stages [38], [39]. Figure 12 shows a block diagram of a pipelined ADC with L1 dither levels injected before

the first stage, L2 levels before the second stage, and so on. In practice, an odd number of dither levels is used for each stage [38], [39], and the number of dither levels in each stage should be coprime to produce the maximum number of distinct dither levels in the back end of the ADC, which maximizes the benefit of this approach [38].

ConclusionAt first, calibration was done only in the analog domain, but now it is done in the analog domain, the digital domain, or both. Also, cali-bration has evolved from factory trimming to FG and then BG calibra-tion, sometimes along with dynamic element matching. This progression may seem to imply that digital BG calibration is the ultimate tool, but all of these techniques are important and in use today.

Without calibration, data-conver-sion architectures are mainly chosen to satisfy the speed and accuracy requirements of the applications while minimizing the power dissi-pation. With calibration, the selec-tion process has a new dimension, offering significant improvements in performance but coming with char-acteristics that make data-conver-sion customers uncomfortable. For example, the performance of data converters with BG calibration is not static but instead dynamic because they adapt and possibly readapt to new inputs.

The flexibility of general-purpose converters is important. However, application-specific specialization is inevitable, and more and more spe-cialized calibration techniques are likely to appear in the future.

AcknowledgmentWe are grateful to Prof. P.J. Hurst and Prof. B.C. Levy at the University of California, Davis, for helpful techni-cal discussions.

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Figure 12: A block diagram of a pipelined ADC with multilevel dither injected progressively in successive stages.

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About the AuthorsKenneth C. Dyer (kdyer@ieee.org) re -ceived the B.S., M.S., and Ph.D. de-grees in electrical engineering from the University of California, Davis, in 1990, 1993, and 1998, respectively. His doctoral research focused on error cor-rection for time-interleaved analog-to-digital converters. From 1998 through 2010, he worked with several commu-nications integrated circuit companies, including Level One, Intel, and Keyeye, designing circuits for CAT5/6 Ethernet

products in Sacramento, California. From 2010 to 2013, he worked on light sensor products at Intersil in Milpi-tas, California. In early 2013. he joined Semtech to develop high-speed data converters. In 2016, he joined Rambus in Sunnyvale, California, as a senior principal data converter architect.

John P. Keane (jpkeane@ieee.org) received the B.E. degree in electri-cal and electronic engineering from University College Dublin, Ireland, in 1998 and the M.S. and Ph.D. de-grees in electrical engineering from the University of California, Davis, in 2002 and 2004, respectively. Since 2004, he has been with Keysight Techno logies (formerly Agilent Tech-nologies), Santa Clara, California, where he is engaged in research on high-performance integrated circuits for measurement applications. His research interests include timing re-covery and adaptive equalization for high-speed serial transceivers and the design and calibration of high-resolution data converters.

Stephen H. Lewis (shlewis@ucdavis .edu) received the B.S. degree from Rutgers University, New Brunswick, New Jersey, in 1979, the M.S. degree from Stanford University, Stanford, California, in 1980, and the Ph.D. de-gree from the University of Califor-nia, Berkeley, in 1987, all in electrical engineering. From 1980 to 1982, he was with Bell Laboratories in Whip-pany, New Jersey, where he was in-volved in circuit design for magnetic recording. In 1988, he rejoined Bell Laboratories in Reading, Pennsylva-nia, where he concentrated on the de-sign of analog-to-digital converters. In 1991, he joined the Department of Electrical and Computer Engineer-ing, University of California, Davis, where he is now a professor. He is a coauthor of a college textbook on analog integrated circuits, and his research interests include data con-version, signal processing, and ana-log circuit design.