Low Current Electrochemical Low Current Electrochemical Measurement for Biotechnolgy Measurement for Biotechnolgy

ApplicationsApplications

Kevin W. GlassKevin W. Glass

Advisor: Dr. AlleeAdvisor: Dr. Allee

Co-Advisor: Dr. SongCo-Advisor: Dr. Song

AgendaAgenda

Electrochemical Measurement BasicsElectrochemical Measurement BasicsExample Low Current Measurement Example Low Current Measurement

SystemsSystemsA/D Converter SelectionA/D Converter SelectionOpamp SelectionOpamp SelectionReview of Current Opamp DesignsReview of Current Opamp DesignsSummarySummary

Electrochemical Electrochemical Measurement BasicsMeasurement Basics

Three Terminal Electrochemical Cell with Potentiostat Three Terminal Electrochemical Cell with Potentiostat for Current Measurement [3]. for Current Measurement [3].     

Counter/

Counter/

Potetentiostat and Cell Measurement BasicsPotetentiostat and Cell Measurement Basics

Working Electrode is the electrode where the potential is controlled and where the Working Electrode is the electrode where the potential is controlled and where the current is measured. It’s where the electrochemical reaction takes place.current is measured. It’s where the electrochemical reaction takes place.

The Reference Electrode is used in measuring the working electrode potential. A The Reference Electrode is used in measuring the working electrode potential. A reference electrode should have a constant electrochemical potential with no current reference electrode should have a constant electrochemical potential with no current flowing through it. flowing through it. 

The Counter (Auxiliary) Electrode is a conductor that completes the cell circuit. The The Counter (Auxiliary) Electrode is a conductor that completes the cell circuit. The current that flows into the solution via the Working Electrode leaves the solution via current that flows into the solution via the Working Electrode leaves the solution via the Counter Electrode.the Counter Electrode.

A potentiostat is an electronic circuit that controls the voltage difference between the A potentiostat is an electronic circuit that controls the voltage difference between the working electrode and the reference electrode. The potentiostat implements this working electrode and the reference electrode. The potentiostat implements this control by sourcing current into the cell through the counter electrode. In almost all control by sourcing current into the cell through the counter electrode. In almost all applications, the potentiostat measures the current flow between the working and applications, the potentiostat measures the current flow between the working and counter electrodes. The controlled variable in a potentiostat is the cell potential and counter electrodes. The controlled variable in a potentiostat is the cell potential and the measured variable is the cell current.the measured variable is the cell current.

The potentiostat becomes a galvanostat when the feedback is switched from a cell The potentiostat becomes a galvanostat when the feedback is switched from a cell voltage control amplifier input signal, to a working electrode cell current input signal. voltage control amplifier input signal, to a working electrode cell current input signal. The instrument then controls the cell current rather than the cell voltage. The The instrument then controls the cell current rather than the cell voltage. The electrometer output can still be used to measure the cell voltage.electrometer output can still be used to measure the cell voltage.

Coulometry is the complete electrolysis of a solution at an electrode and the Coulometry is the complete electrolysis of a solution at an electrode and the measure of the total Coulombs of change produced under Faraday’s Law.measure of the total Coulombs of change produced under Faraday’s Law.

AC small signal model of electrode solution interface [2].AC small signal model of electrode solution interface [2].

Example of process cross-section of a typical UME array device [4].

SEM images of typical micro-fabricated array designs. Left) A “honeycomb” pattern of 564 10um diameter UMEs. Center) A “ring” design with 40 10um diameter UMEs. Outer and inner rings are on-chip counter and reference electrodes, respectively. Right) A “bicycle” design of 20 10um diameter UMEs, each surrounded by a ring counter/reference electrode [4].

Example Low Current Example Low Current Measurement SystemsMeasurement Systems

System Diagrams of Potentiostat Chip Set Designed at Stanford.Left - Top level systems diagram of the electrochemical analysis system [11]. Right – More detailed top level diagram of the potentiostat [12].

Switch implementation approaches. Left – Conventional nMOS transfer gate switch [10]. Right – Low junction leakage alternative. pMOS used with n well tied to reference supply (Gnd) to Vcc/Vss.Inputs to be measured are maintained very close to Gnd, so the voltage from p+ source/drain to n well is ~0V with negligible leakage

Block Diagram of A/D converter integrator. Switches with dashes are low junction leakage p channels with n wells connected to gnd [10].

Iin = (T2 / T1 ) Iref

Left – Top level conceptual schematic of offset cancellation for dual input opamp [10]. Right – Circuit implementation of dual input opamp with dedicated offset cancellation input [11].

Standard single ended potentiostat circuit, fabricated with the new differential design in TSMC 0.18um. Designed at University of Michigan [8].     

New low voltage differential potentiostatcircuit, fabricated in TSMC 0.18um. Designed at University of Michigan [8].

Differential opamp used in new low voltage potentiostat circuit, fabricated in TSMC 0.18um. Constant gm biasing not shown. Device sizes in um. Designed at University of Michigan [8].

Burr Brown Precision Switched Integrator Transimpedance Amplifier. This can be used as a building block for an integrating A/D converter [13]

IC1 is a self-contained transimpedance amplifier with an internal feedback capacitor, a hold switch, a reset switch, and a precision op amp (laser trimmed to compensate for offset and drift errors). This amplifier forms the input block for along with the 30-pF internal capacitorThis capacitance, along with the integration time set by the 555 timer, scales theI/V output by the transfer equation, Vout=-Iin*Integration Time/Feedback Capacitance=-50mV/pA

Burr Brown Picoammeter Reference Design Board

A/D Converter SelectionA/D Converter Selection

A/D Converted SelectionA/D Converted Selection

Desired goal was to have a converter with 16 bits resolution. The application frequency range is very low, so conversion speed is not an issue. Low noise is a major issue since our goal is to measure currents possibly as low as 1pA, and if possible, 0.1pA

Typical resistive ladder, ratioed capacitor, or cyclic converters did not meet the requirements because of resolution limitations from component matching, and noise issues.

Sigma-Delta converters possibility - employed in some of the prior work reviewed. Resolution of these types of converters can be very high with large over sampling ratios. The application of Sigma-Delta converters can have issues for DC measurements. For signals that are not varying with time, they can develop output tones or instabilities. A low noise front end amplifier and low pass filter are still required.

Integrating A/D converters have been used for precision current measurement instruments, in particular, the dual slope A/D converter. This converter employs a low noise operational amplifier in an inverting configuration with a capacitor feeding from the output to the inverting input to form a miller integrator

The integrator in combination with the input signal forms a low pass filter, band The integrator in combination with the input signal forms a low pass filter, band limiting and attenuating higher frequency noise. limiting and attenuating higher frequency noise.

To adjust for different voltage or current ranges, the integration time can be varied. To adjust for different voltage or current ranges, the integration time can be varied. The lower the current range measured, the longer the integration time. For dual The lower the current range measured, the longer the integration time. For dual slope - Iin = (T2 / T1 ) Iref. slope - Iin = (T2 / T1 ) Iref.

Modifications can be made to the dual slope technique to account for opamp offset, Modifications can be made to the dual slope technique to account for opamp offset, switch charge injection and other non-idealities. switch charge injection and other non-idealities.

Integrating A/D can be viewed as integrate and dump matched filter - SNR=CVIntegrating A/D can be viewed as integrate and dump matched filter - SNR=CV 22 /N /N00

Left - Basic Auto Zero (AZ) amplifier block diagram [16]. Right - The effect of the AZ process on a first order low-pass filtered 1/f noise having a bandwidth 5 times larger than the sampling frequency [16].

High Level Block Diagram of Electrochemical Measurement System under development at ASU.

Opamp SelectionOpamp Selection

Opamp SelectionOpamp Selection

2 stage active load – noise from active loads, compensation2 stage active load – noise from active loads, compensation OTA (e.g. U of Utah) – noise from diode loaded input, low OTA (e.g. U of Utah) – noise from diode loaded input, low

gain first stagegain first stage Telescopic – noise from active loads, low output swingTelescopic – noise from active loads, low output swing Gain Boost – Possible to be added to current designsGain Boost – Possible to be added to current designs Lateral bipolar inputs - low beta causes high base currents, Lateral bipolar inputs - low beta causes high base currents,

which increases the base thermal noise. Higher 1/f noise which increases the base thermal noise. Higher 1/f noise because of the surface states. No device models existed for because of the surface states. No device models existed for process. process.

Chopper Stabilized – Too much complexity for 1Chopper Stabilized – Too much complexity for 1stst pass. Will pass. Will revisit because technically superior.revisit because technically superior.

Decided on folded cascode – high gain in 1 stage.Decided on folded cascode – high gain in 1 stage. Decided on some new design with resistor loads on input.Decided on some new design with resistor loads on input.

Left – Schematic of CMOS opamp using lateral PNP transistors [19].

Right- Layout of the lateral bipolar PNP input transistor [19].

Top – the chopper amplifier principal [16]. Bottom – Waveforms appearing along the chopper amplifier for a DC input and an amplifier bandwidth limited to twice the chopper frequency [16].

Left – Chopper Modulated white noise at zero frequency asa function of the original bandwidth [16].Right- Chopper output PSD for 1/f noise [16].

Crystal Semiconductors Chopper Stabilized Opamp [20]. Amplifier input stage simplified schematic.

Review of Current Opamp Review of Current Opamp DesignsDesigns

Actest1a AC test fixture with offset cancellation used for most of the AC simulations.

Cadence schematic with device sizes and values for the self biased folded cascode opamp (selfbfcascode)

Gain/Phase simulations of selfbfcascode opamp using testbench actest1a. Gain/Phase simulations of selfbfcascode opamp using testbench actest1a.

Overlaid plots of 7 corners: Nominal, 27Overlaid plots of 7 corners: Nominal, 27ooC (Vcc=2V, 2.5V,3V); Nominal, 27C (Vcc=2V, 2.5V,3V); Nominal, 27ooC C (R=+30%,-30%); Slow, 125(R=+30%,-30%); Slow, 125ooC; Fast -15C; Fast -15ooC. Cload=35pF, PM≈60C. Cload=35pF, PM≈60oo

Input referred noise voltage squared for selfbfcascode opamp usingtestbench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS),

Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=35pF, PM=60o.

Transient simulation of selfbfcascode opamp using trantest1test bench, +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC, Vcc=2.5V

Cadence schematic with device sizes and values for the low noise self biased folded cascode opamp (lnselfbfcascode). IP24=216uA, and IP3=105uA, IP2=212uA. Nominal process, temperature, and Vcc=2.5V.

Cadence schematic with device sizes and node voltages and for the self biased folded cascode opamp with compensation (selfbfcascodecmp).This is the output of lnselfbfcascode.This opamp is identical to selfbfcascode in Figure 21, with the addition of P20 (100u/20u*60) for a comp. cap. IP2=83.4uA, and IP3=IP4=82.0uA, nominal process and temperature, Vcc=2.5V.

Gain/Phase simulations of lnselfbfcascode opamp using testbench actest1a. Overlaid plots of 7 corners: Nominal, 27oC (Vcc=2V, 2.5V, 3V); Nominal, 27oC (R=+30%,-30%); Slow, 125oC; Fast -15oC. Cload=30pF, PM≈75o

Input referred noise voltage squared for lnselfbfcascode opamp using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=75o

Transient simulation of lnselfbfcascode opamp using trantest1 test bench. +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC, Vcc=2.5V. Includes internal nodes-vinvplus and vinvminus–output of diff. pair.

Cadence schematic with device sizes, values and node voltages for the high gain - low noise, opamp (hglnopaa). P31 and P26 are used as compensation capacitors with sizes of (100u/20u*24) and (100u/20u*38) respectively.IP4=48uA, and IP2=187uA, IN10=19uA, IP6=IP7=111uA, IP51=67uA. Nominal process, 27oC, and Vcc=2.5V.

Gain/Phase simulations of hglnoppa opamp using testbench actest1a. Overlaid plots of 9 corners: Nominal (-25oC, 27oC, 125oC), Vcc=2.5V; Nominal, 27oC, (Vcc=2V, 2.5V, 3V); Nominal, 27oC, (R=+30%,-30%); Slow, 27oC, Vcc=2.5V; Fast, 27oC, Vcc=2.5V. Cload=30pF, PM≈90o.

System level diagram for common mode System level diagram for common mode feedback circuit for hglnopaa opamp.feedback circuit for hglnopaa opamp.

Opamp hglnopaa common mode feedback loop magnitude response. Overlaid plots with and without capacitor CP44. Simulations using test bench similar to actest1a. Top blue curve - opamp gain response for reference. Second from top red curve – Differential input stage gain response. Third from top – vcommon gain response. Bottom curve - vcmfb gain response. Nominal process, 27oC, Vcc=2.5V.

Input referred noise voltage for hglnopaa opamp using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=90o.

Cadence schematic with device sizes and values for high gain - low noise, opamp withW for P0 and P1 input transistors increased to 2000u. (hglnopaa2). Compensation Source follower sizes increased 50% to W=150u for P50 and W=300u for P51. Associated current increased from 67uA to 100uA. P31 andP26 compensation capacitorsizes remain the same at (100u/20u*24) and (100u/20u*38) respectively.

Input referred noise voltage for hglnopaa2 opamp (W=2000u input transistor) using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=90o.

Gain/Phase simulations of hglnoppa2 opamp using test bench actest1a. Overlaid plots of 9 corners: Nominal, 27oC, (Vcc=2V, 2.5V, 3V), (R=+30%,-30%); Slow, 125oC, Vcc=2.5V; Fast, -25oC, Vcc=2.5V. Cload=30pF, PM≈65o.

Transient simulation of hglnopaa opamp using trantest1 test bench. +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC, Vcc=2.5V.Includes internal nodes-vinvplus and vinvminus–output of diff. pair.Also includes internal nodes of common mode feedback circuit – vcmfb,vdiffbias, and vcommon.

Summary of ResultsSummary of Results

Comparison of Opamp Input Referred Noise RelationsComparison of Opamp Input Referred Noise Relations

Self Biased Folded CascodeSelf Biased Folded Cascodevv22

totaltotal={4kT[(4/3)/g={4kT[(4/3)/gmP1mP1)+1/g)+1/gmP3mP3+1/g+1/gmN1mN1]+]+

[(2K[(2KfPfP+3K+3KfNfN)/6000u)/6000u22CC00](1/f )}∆f (36)](1/f )}∆f (36) Low Noise Self Biased Folded CascodeLow Noise Self Biased Folded Cascode

vv22totaltotal={4kT[(4/3/g={4kT[(4/3/gmP0LNmP0LN)+(1/g)+(1/g22

mP0LNmP0LNRR11)]+)]+

(K(KfPfP/20000u/20000u22CC00)(1/f)}∆f (63) )(1/f)}∆f (63) High Gain Low Noise High Gain Low Noise

vv22totaltotal={4kT[(4/3/g={4kT[(4/3/gmP0mP0)+(1/g)+(1/g22

mP0mP0RR11)]+)]+

(K(KfPfP/10000u/10000u22CC00)(1/f)}∆f (80) )(1/f)}∆f (80) High Gain Low Noise opa2High Gain Low Noise opa2

vv22totaltotal={4kT[(4/3/g={4kT[(4/3/gmP0mP0)+(1/g)+(1/g22

mP0mP0RR11)]+)]+

(K(KfPfP/20000u/20000u22CC00)(1/f)}∆f )(1/f)}∆f

Comaparison of Opamp CharateristicsComaparison of Opamp Charateristics

AV 1dB W PM I In off. In Offset 5%mm In Ref. Noise Volts Noise V @1kHzCMR

RPSR

R

dB MHz deg mA uV uV uVrms uV./sqrt(Hz) dB dB

selfbfcascode 95 4.40 55 0.25 0.470 10.2 100 1 85 95

lnselfbfcascode 117 2.25 75 0.78 0.278 11.5 7.12 0.1 86 112

hglnopaa 117 1.74 90 0.55 0.356 7.6 14 0.2 97 107

hglnopaa2 120 1.65 65 0.58 0.258 10.7 6 0.1 97 107

Future PlansFuture Plans

Verify Noise ModelVerify Noise Model Layout opampsLayout opamps Have Idea for one transistor opamp – exploreHave Idea for one transistor opamp – explore Design integrating A/DDesign integrating A/D Layout and tape out test chipLayout and tape out test chip Look at chopper stabilized amplifier and lock in amplifierLook at chopper stabilized amplifier and lock in amplifier

Low noise neural recording amplifier developed at the University of Utah. Low noise neural recording amplifier developed at the University of Utah. Left schematic shows the top level. Right schematic shows the OTA Left schematic shows the top level. Right schematic shows the OTA

opamp used in the design. Device is fabricated in AMI 1.6um technology opamp used in the design. Device is fabricated in AMI 1.6um technology [9].[9].