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Design RulesDesign Rules

Kuwait UniversityKuwait UniversityElectrical Engineer DepartmentElectrical Engineer Department

By Eng. Ahmad HaithamBy Eng. Ahmad Haitham

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L EditL-Edit

L-Edit is an Integrated Circuit Layout Tool used to draw the two dimensionalTool used to draw the two dimensional geometry of the masks or layers to fabricate an integrated circuit.

Different layers are represented y pby different colors and patterns.

Sample of Metal Mask

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p

L EditL-EditManufacturing constraints can be defined gin L-Edit as design rules.

L-Edit files are saved as file_name.tdb (Tanner Database).

L-Edit can import and export two industry standard mask layout formats (GDSII andstandard mask layout formats (GDSII and CIF).GSII:(Gerber Data Stream Information Interchange).CIF: (Caltech Interchange Format) 3

L Edit ModulesL-Edit ModulesL Edit Th l t ditL-Edit: The layout editor

L Edit ⁄ DRC Th d i l h kL-Edit ⁄ DRC: The design rule checker

L Edit ⁄ E t t Th l t t t tL-Edit ⁄ Extract: The layout extractor to SPICE

L-Edit ⁄ SPR: an automatic standard cell placement and routing package

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L-Edit WindowL Edit Window

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L-Edit Toolbars

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Layer PaletteLayer Palette

Graphical menu of the available layers Graphical menu of the available layers.

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Things to Know:Things to Know:

The most important scale or dimension in the layout is called lambda (λ)in the layout is called lambda (λ).

Lambda (λ) must equal half of (L), the channel length of the MOSFET, i.e, half channel length of the MOSFET, i.e, half the size of technology used.

L=2*λ8

L-Edit Window

You must set the length of the square to represent One lambda or one Locator Unit

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Design Parameters Setup(1- Technology)

F MFrom Menu >>Setup >> Design >>Technology

Create a name forfabrication process

This is the unit inThe technology.Select LambdaSelect Lambda

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Technology Parameters Setup* You need to know that when you export yourfile to DGSII. The default for GDSII is that one internal unit is 1 nm (1/1000 lambda)one internal unit is 1 nm (1/1000 lambda)

Or Lambda= 1000 internal unit

* The technology length L= 2* Lambda

L= 0.5 Microns 1 Lambda = 0.25 Micron

* (L-edit max size is from-536,870,912 to +536,870,912 internal units)

* Internal units are what is actually used in L-Edit to store information

* This is not what displayed to you.

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Design Parameters Setup(2 Grid)

From Menu >>Setup >>

(2- Grid)From Menu >>Setup >> Design >>Grid

These are jus the dots shown on the screen

Make the length of the Grid in the working area to be equal one Locator Unit

To set one locator Unit=lambda So one locator Unit=1000 internal units

•Its better to set the mouse snap grid 0.5 lambda, i.e 0.5 Locaor units

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CMOS Design gRulesRules

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In general, there are three main classes of design rule specifications These are rule specifications. These are

Minimum Width Which is the smallest Minimum Width. Which is the smallest dimension permitted for any layer in the layout drawing

Spacing. Which is the smallest distance itt d b t th d f t l permitted between the edges of two layers.

Surround This apply to layers placed within Surround. This apply to layers placed within larger ones (such as contacts).

Every layer has a minimum width and minimum spacing value in between all in terms of Lambda.

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NMOS Layout: NMOS Layout: Layers:Layers: Poly ActivePoly Active NselectNselect PselectPselect Metal Active ContactMetal Active ContactLayers: Layers: Poly, Active, Poly, Active, NselectNselect, , PselectPselect, Metal, Active Contact, Metal, Active Contact

22λλ22λλ(W)(W)

11λλ

22λλ(W)(W)

33λλ22λ (λ (L)L)

33λλ

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L must equal to L must equal to 22λλAll contacts must be All contacts must be 22λλxx22λλMinimum MetalMinimum Metal1 1 width =width =33λλ

Minimum spacing from Active to Nselect or Pselect is Minimum spacing from Active to Nselect or Pselect is 22λλMinimum Metal Minimum Metal 1 1 surround Contact is surround Contact is 11λλW must be greater than W must be greater than 33λλ

PMOS Layout: PMOS Layout: yyLayers: Layers: Poly, Active, Poly, Active, NselectNselect, , PselectPselect, Metal, Active Contact, , Metal, Active Contact, NWellNWell

33λλ

(W)(W)66λλ (W)(W)22λλ

22λλ

22λλ 11λλ

66λλ

22λλ

22λ (λ (L)L)1616

22λ (λ (L)L)

Minimum spacing from Active to Nwell edge is Minimum spacing from Active to Nwell edge is 66λλ

CMOS Layout Rules - NWell

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CMOS Layout Rules - Active

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CMOS Layout Rules - Poly

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CMOS Layout Rules – Select

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CMOS Layout Rules - Contact to Poly & Contact to Active

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CMOS Layout Rules - Metal1

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CMOS Layout Rules - Via

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CMOS Layout Rules - Metal2

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Layout Exampley pDraw the layout of a CMOS inverter given the following:L= 0.5µm, Wn= 1.0 µm, and Wp= 2.5 µm.

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Stick DiagramStick DiagramVdd = 5V

Stick DiagramStick Diagram

pMOS

Vin

N MOSN MOS

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R L EDIT Run L-EDIT by Double click on its iconby Double click on its icon

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Design SetupDesign SetupDesign SetupDesign Setup

2828As mentioned before from: From Menu >>Setup >> Design >>

• Draw a Vertical Ploy layer that t th t f th irepresent the gate of the opposing

PMOS & NMOS.

• The width of this poly must be• The width of this poly must beEqual to L=2λ.

• The vertical height should be fixed• The vertical height should be fixeddepends on The maximum spacing required to draw your Layout.

• Select this height= 70λ.

2λ

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4λ2λ

• Draw Metal1 layers for the VDD & VSS power supplies.

• The minimum width for Metal1=3λ, but to distinguish the power supply thanotherMetal1 wiring, make its width=4λ.

•Keep a 2λ extension of ploy as shown.

30304λ2λ

L= 0.5 µm, i.e. λ= 0.25 µmWn= 1.0 µm, i.e. Wn= 4λ

• Draw the NMOS as discussed before

4λ4λ

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•Click the home button to view thewhole layout

NMOSNMOS

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• Draw the PMOS as discussed before• Draw the PMOS as discussed before.

10λ

3333L= 0.5 µm, i.e. λ= 0.25 µmWp= 2.5 µm, i.e. Wn= 10λ

PMOSPMOS

NMOS

•Click the home button to view thewhole layout

NMOS

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Connect the drain ofPMOS to the drain ofNMOS by Metal1 layerNMOS by Metal1 layerof 3λ width3λ

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Make 6λ by 6λ Ploy4λ b 4λ M t l1

Why? To make extra Metal4λ by 4λ Metal12λ by 2λ Poly Contact

Connection to the gate.

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Do the same to the other end ofThe Poly

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Wh ?Why? To make extraconnection to the output to use itoutput to use it later.

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Naming The NodesNaming The NodesNaming The NodesNaming The Nodes

• Click to Port• Click the Metral1 of the object you j ywant to give a Name.

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L-Edit Design Rule CheckL-Edit Design Rule CheckYou have to run Design Rule Check (DRC) most of the time if yourYou have to run Design Rule Check (DRC) most of the time if yourare adding, removing or editing layers in the layout.

or from here

This action opens a dialog box that allows you to specify the format of the output

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the output.

L Edit ExtractorL-Edit ExtractorL-Edit can be used to generate SPICE-compatible circuit file listings using the Extract option in the setup window of the menu barmenu bar.

L Edit does not automatically identify the ground to 0 V orL-Edit does not automatically identify the ground to 0 V or power supply to 3 V. So the generated file must be edited to identify the corresponding voltages.y p g g

You should add the MOS MODEL parameters depending onYou should add the MOS MODEL parameters depending on the technology used before a SPICE simulation is performed.

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L Edit ExtractorL-Edit Extractor

Running the Extractor:

or from here

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L Edit ExtractorL-Edit Extractor

Enter the name of theextractor definition fileextractor definition file

Enter the name of theSPICE output file.• name.cir for PSPICE AD•name.sp for TSPICE

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L-Edit Extractor

Select

•Comments: Write Nodes Names

•Write Nodes as: Integers

i i i C i•Write Node parasitic Capacitance.

•Place device labels on layer: Metal1y

•Then Click Run

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L-Edit ExtractorL Edit ExtractorThe following window will appear:The following window will appear:

Click: Ignore All

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Run PSPICE ADRun PSPICE AD

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Run PSPICE ADRun PSPICE AD

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The generated SPICE file* NODE NAME ALIASES

The generated SPICE fileThe Nodes corresponding integers

* 1 = GND (33.499,-18.499)* 2 = VDD (0.999,43.5)* 3 = VOUT (40 999 51 5)

The generated parasitic capacitors 3 = VOUT (40.999,51.5)

* 4 = VIN (21.499,51.5)

Cpar1 2 0 7 800125f

The generated two MOSFETs

Cpar1 2 0 7.800125fCpar2 3 0 7.73725f

M3 3 4 2 2 PMOS L 0 5 W 2 5 AD 5 9375 PD 9 75 AS 6 25 PS 10M3 3 4 2 2 PMOS L=0.5u W=2.5u AD=5.9375p PD=9.75u AS=6.25p PS=10u M4 3 4 1 1 NMOS L=0.5u W=1u AD=3.25p PD=8u AS=3.25p PS=8u

* Total Nodes: 4* Total Elements: 4* Extract Elapsed Time: 0 secondsp.END

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The modified SPICE file* NODE NAME ALIASES* 1 = GND (33.499,-18.499)VG 1 0 DC 0VG 1 0 DC 0* 2 = VDD (0.999,43.5)VDD 2 0 DC 3* 3 = VOUT (40 999 51 5) 3 = VOUT (40.999,51.5)* 4 = VIN (21.499,51.5)VIN 4 0 DC 0DC VIN 0 3 0 1.DC VIN 0 3 0.1

.PROBECpar1 2 0 7.800125fCpar2 3 0 7 73725fCpar2 3 0 7.73725fM3 3 4 2 2 PMOS L=0.5u W=2.5u AD=5.9375p PD=9.75u AS=6.25p PS=10u M4 3 4 1 1 NMOS L=0.5u W=1u AD=3.25p PD=8u AS=3.25p PS=8u H P t th 0 5 d lHere Paste the 0.5u model* Total Nodes: 4* Total Elements: 4* E El d Ti 0 d

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* Extract Elapsed Time: 0 seconds.END

0.5 µm NMOS SPICE MODEL.MODEL NMOS NMOS ( LEVEL = 7+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.77269+K1 = 0.7297494 K2 = -0.0506893 K3 = 31.4631363+K3B = -11.2621866 W0 = 1E-8 NLX = 1E-9+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.806584 DVT1 = 0.4071509 DVT2 = -0.2695432+U0 = 530.4792998 UA = 2.711027E-13 UB = 3.086214E-18+UC = 6.526596E-11 VSAT = 9.92744E4 A0 = 0.5982151+AGS = 0.1815599 B0 = 1.260889E-6 B1 = 1.247614E-6+KETA = -9.95193E-3 A1 = 0 A2 = 1+RDSW = 2.265793E3 PRWG = -0.0421807 PRWB = 0.0840864+WR = 1 WINT = 2.28694E-7 LINT = 3.4243E-8+XL = 0 XW = 0 DWG = -2.179541E-8+DWB = -1.061163E-8 VOFF = -0.1276 NFACTOR = 1.601+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 0.02354 ETAB = -1.35983E-3+DSUB = 0.2295 PCLM = 1.4773229 PDIBLC1 = -0.3225681+PDIBLC2 = 3.242849E-3 PDIBLCB = 3.28937E-3 DROUT = 0.3630621+PSCBE1 = 5.88417E8 PSCBE2 = 1.020647E-4 PVAG = 0.3914131

DELTA 0 01 MOBMOD 1 PRT 0+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = 0 WWN = 1+WWL 0 LL 0 LLN 1+WWL = 0 LL = 0 LLN = 1+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 1.9E-10+CGSO = 1.9E-10 CGBO = 1E-11 CJ = 4.266435E-4+PB = 0.99 MJ = 0.4481178 CJSW = 3.152209E-10+PBSW = 0 5007282 MJSW = 0 1339493 )

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+PBSW = 0.5007282 MJSW = 0.1339493 )

MODEL PMOS PMOS ( LEVEL = 7

0.5 µm PMOS SPICE MODELMODEL PMOS PMOS ( LEVEL 7+VERSION = 3.1 TNOM = 27 TOX = 1.39E-8+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.972531+K1 = 0.5616782 K2 = 2.773863E-4 K3 = 12.7986171+K3B = -0.4723902 W0 = 1E-8 NLX = 1E-9+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.811011 DVT1 = 0.188458 DVT2 = -0.1862226+U0 = 364.2897131 UA = 6.556695E-9 UB = 2.005454E-19+UC = -5.21416E-12 VSAT = 1.805928E5 A0 = 0.6916524+AGS = 0.217888 B0 = 2.404098E-6 B1 = 5E-6+KETA = -3.409663E-3 A1 = 0 A2 = 1+RDSW = 2.846814E3 PRWG = -0.0499675 PRWB = -0.1304146+WR = 1 WINT = 2.508674E-7 LINT = 1.459153E-8+XL = 0 XW = 0 DWG = -2.24102E-8+DWB = 2.268096E-8 VOFF = -0.1446 NFACTOR = 0.9027+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 4.973E-3 ETAB = -3.342697E-3+DSUB = 0.1147 PCLM = 3.1538098 PDIBLC1 = 0.6370303+PDIBLC2 = 1.376041E-3 PDIBLCB = 0.2184 DROUT = 0.6256738+PSCBE1 = 1.235615E10 PSCBE2 = 1.210011E-9 PVAG = 7.1862598+DELTA = 0.01 MOBMOD = 1 PRT = 0+UTE = -1.5 KT1 = -0.11 KT1L = 0+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18+UC1 = -5.6E-11 AT = 3.3E4 WL = 0+WLN = 1 WW = 0 WWN = 1+WWL = 0 LL = 0 LLN = 1+LW 0 LWN 1 LWL 0+LW = 0 LWN = 1 LWL = 0+CAPMOD = 2 XPART = 0.4 CGDO = 2.42E-10+CGSO = 2.42E-10 CGBO = 1E-11 CJ = 7.303593E-4+PB = 0.9569 MJ = 0.5047944 CJSW = 2.120694E-10+PBSW = 0.8208359 MJSW = 0.1000002 )

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Voltage Transfer CharacteristicsVoltage Transfer Characteristics

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Power Dissipation versus VINPower Dissipation versus VIN

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Transient AnalysisTransient AnalysisTransient AnalysisTransient Analysis

Replace the DC source of VIN by a Replace the DC source of VIN by a pulse.pulse.pp

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Transient AnalysisTransient AnalysisIn the spice file, replaceIn the spice file, replace

VIN 4 0 DC 0.DC VIN 0 3 0.1

By:

VIN 4 0 Pulse ( 0 3 1p 1p 1p 0.5u 1u)TRAN 02u 2u.TRAN .02u 2u

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Transient AnalysisTransient Analysis

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Transient AnalysisTransient Analysis

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Homework AssignmentsHomework Assignments1- Redo the design of the layout for CMOS inverter given the

following: L= 0.5µm, Wn= 1.5 µm, and Wp= 2.5 µm. Extract to spice and plot the voltage transfer characteristics powerto spice and plot the voltage transfer characteristics, power dissipaion versus VIN, Vout and VIN versus time and the average power dissipation at 4 µs given the pulse of 1µs g p p µ g p µperiod.

2- In the same file but in a new cell, draw the layout of the 2_inputs NAND gate that has the same speed of the inverter. Extract to spice, apply two pulses as inputs, plot both inputs versus time and Vout versus time to prove that your layout really present 2 inputs NAND gatereally present 2_inputs NAND gate.

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Stick DiagramsStick DiagramsStick DiagramsStick DiagramsHint:Hint: VVDDDDHint:Hint:

OutOut

AA BB

NANDNAND22

GNDGND

NANDNAND226060