lab manual

Greg Tumbush, Chris Spear 2011 Page 0 of 14 Version 1.1

SystemVerilog Training

Tumbush, Greg 4/11/2014


Contents 1 Introduction .......................................................................................................................................... 1

1.1 Conventions .................................................................................................................................. 1

1.2 Directory layout and common files ............................................................................................... 2

1.3 Makefile usage .............................................................................................................................. 2

1.3.1 Using Makefile option ius_gui ............................................................................................... 2

2 Hello World example ............................................................................................................................ 3

3 Lab 1 ...................................................................................................................................................... 4

4 Lab 2 ...................................................................................................................................................... 5

5 Lab 3 ...................................................................................................................................................... 6

6 Lab 4 ...................................................................................................................................................... 0

7 Lab 1 Solution ........................................................................................................................................ 2

8 Lab 2 Solution ........................................................................................................................................ 3

9 Lab 3 Solution ........................................................................................................................................ 5

10 Lab 4 Solution .................................................................................................................................... 6

1 Introduction This document will describe the 4 labs developed for the SystemVerilog training at ASICentrum.

To complete each lab the following material must be covered:

Lab 1: Up to and including Section 2.5 Associative Arrays

Lab 2: Up to and including Chapter 4 Connecting the Testbench and Design

1.1 Conventions

Commands to be entered will be italicized.


1.2 Directory layout and common files

Each lab will be completed in its own directory under SV_training_AC/lab_x/lab_x_work where

x is the lab number.

A makefile common to all labs is provided in SV_training_AC/Makefile_common.

A makefile specific to each lab can be found in SV_training_AC/lab_x/lab_x_work/Makefile

Solutions can be found in SV_training_AC/lab_x/lab_x_solution

1.3 Makefile usage

The Makefile will be executed in the SV_training_AC/lab_x/lab_x_work directory typically with

the following options

make ius Execute the Cadence Incisive simulator in batch mode

make ius_gui Execute the Cadence Incisive simulator in gui mode

make clean Delete INCA_libs *shm .simvision *.log *.key

1.3.1 Using Makefile option ius_gui

The common makefile, Makefile_common, assumes a restore.tcl file is available to specify

signals to view in the waveform viewer. The restore.tcl file must be created when the simulator

is invoked for the first time for each lab.

To create a restore.tcl file:

1) Execute make ius_gui in SV_training_AC/lab_x/lab_x_work

2) The following Console window will appear:

3) In the Design Browser window select Windows->New->Waveform

4) In the Design Browser window select the signal you want to view, right click, and select

Send to Target->Waveform Window


5) In the Waveform window select File->Save Command Script

6) In the Save Command Script window click on OK.

7) Enter run in the Console window or quit the simulator and re-execute make ius_gui

2 Hello World example To ensure correct setup students may run the Hello World example in

SV_training_AC/hello_world/hello_world_work.

To run this example:

1) cd to SV_training_AC/hello_world/hello_world_work

2) execute make ius

3) Output similar to the following should be printed to the terminal.

lxwrx27: make ius

irun test.sv

irun: 12.20-s017: (c) Copyright 1995-2013 Cadence Design Systems, Inc.

file: test.sv

module worklib.test:sv

errors: 0, warnings: 0

Caching library 'worklib' ....... Done

Elaborating the design hierarchy:

Top level design units:

test

Building instance overlay tables: .................... Done

Generating native compiled code:

worklib.test:sv

streams: 1, words: 422

Loading native compiled code: .................... Done

Building instance specific data structures.

Design hierarchy summary:

Instances Unique

Modules: 1 1

Initial blocks: 1 1

Writing initial simulation snapshot: worklib.test:sv

Loading snapshot worklib.test:sv .................... Done

ncsim> source /apps/cadence/INCISIVE/12.2/linux/tools/inca/files/ncsimrc

ncsim> run

Hello World


ncsim: *W,RNQUIE: Simulation is complete.

ncsim> exit

3 Lab 1 The purpose of this lab is to:

1. Practice creating dynamic arrays, associative arrays, and queues 2. Practice using $random 3. Practice writing an easy to expand test-bench

This lab will test a synchronous 8-bit x64K (512kBit) RAM. The RAM will read on the positive

edge of the clock when input read =1 and write on the positive edge of the clock when input

write = 1. Even parity will be calculated on data written to the RAM and placed in the 9th bit of

the memory. The partially completed memory model is below.

`default_nettype none

module my_mem(

input var logic clk,

input var logic write,

input var logic read,

input var logic [7:0] data_in,

input var logic [15:0] address,

output logic [8:0] data_out

);

// Declare a 9-bit associative array mem_array using the logic data type

always @(posedge clk) begin

if (write)

mem_array[address] = {^data_in, data_in};

else if (read)

data_out = mem_array[address];

end

endmodule


Your testbench will:

1. Perform 6 writes of random data to random addresses followed by 6 reads to the same

addresses in reverse order. To do this:

a. Create a dynamic array of 6 random addresses to write called address_array

b. Create a dynamic array of 6 random data to write called data_to_write_array

c. Create an associative array of data expected to be read indexed by the address

read from called data_read_expect_assoc

d. Make your test-bench self checking by comparing the data read with the

data_read_expect_assoc array. Maintain an error counter and correct counter.

e. Create a queue of data read called data_read_queue

2. At the end of the test traverse the data_read_queue, print out the data read, print out

the error counter and print out the correct counter.

Deliverables:

1. Code for completed memory model and test-bench

2. Waveform showing at a minimum the I/O of the memory model and the error counter.

3. Copy of transcript window showing the print out of data_read_queue and the error

counter equaling 0.

4 Lab 2 The purpose of this lab is to practice using clocking blocks, programs, and assertions to improve

your solution for Lab 1. Expand on this solution by:

1. Use an interface in the I/O declaration for module my_mem and use the interface in the

testbench.

2. Add an assertion to the interface that fails if write and read are both 1.

3. Add a test to your testbench that tests the checker. NOTE: by default an assertion

failure will stop the simulation. To change this behavior enter set

assert_output_stop_level none in the Console window prior to running the simulation.

4. Add a function to the interface that calculates even parity and use this function in

module my_mem. Pass the arguments to the parity function by name, not position.

5. Add a clocking block to your interface for all of the I/O of module my_mem and use this

clocking block to drive/observe these signals in your testbench. The testbench should


only drive/observe signals to/from the DUT through the clocking block. Do not put the

clocking block in the modport to the DUT. Do not use the clocking block in the DUT.

6. The clock domain for your clocking block is posedge clk since the DUTs flip-flops are

positive edge triggered.

7. Separate your testbench into a program block that provides stimulus and checks results

and a top level that instantiates the DUT, interface, and program similar to Figure 1.

Your top level should also create the clock.

program test module my_mem

module top

interface mem_if

Figure 1: Testbench hierarchy

8. Ensure that your testbench will work for both 0-delay my_mem model as well a non-0

delay my_mem model by replacing the following line in my_mem.sv

mem_bus.data_out = mem_array[mem_bus.address]; // 0-delay

with

mem_bus.data_out = #75ns mem_array[mem_bus.address]; // non-0 delay

9. The clock created in your testbench shall be 10MHz.

10. Your testbench should only perform the minimum number of reads necessary (i.e. 6).

Deliverables:

1. Code for the interface, my_mem, module top, and program test.

2. Waveform showing at a minimum the I/O of the memory model, error counter, and

assertion for a 0 delay my_mem model and transcript file reporting 0 memory read

errors and at least 1 assertion failure.

3. Waveform showing at a minimum the I/O of the memory model, error counter, and

assertion for a non-0 delay my_mem model and transcript file reporting 0 memory read

errors and at least 1 assertion failure

5 Lab 3 The purpose of Lab 3 is to begin to develop a hierarchical testbench and practice using

synchronized mailboxes to pass transactions. The device under test is the memory model from

Lab 1 and Lab 2.


Design a hierarchical testbench for the my_mem DUT as depicted in Figure 2. For Lab 3 only

design the Generator, Agent, and Driver and connect the DUT (i.e. the my_mem design). The

Generator will create random memory transactions. The Agent does nothing at this time

except pass a transaction from the Generator to the Driver. The Driver converts the transaction

to the pin level interface of the DUT. The testbench will not be self-checking but you should

visually verify accuracy.

Driver MonitorAssertions

DUT

Command

Signal

Agent CheckerScoreboardFunctional

Scenario GeneratorEnvironment

Figure 2: Hierarchical Testbench

The minimum requirements are:

1. Create a separate class to encapsulate the Generator, Agent, and Driver.

2. Use mailboxes to pass transactions between the Generator, Agent, and Driver.

3. The Generator and Agent operate only at the Transaction level.

4. The Generator randomly creates 10 random transactions with the following constraints:

a. Allowed addresses are 0-4.

b. Read=1 and write=1 in the same cycle is not allowed.

5. The mailboxes must be synchronized as described in sections 7.6.4-7.6.7 of the book.

Deliverables:

1. All of your code

2. Waveform clearly showing the 10 transactions, i.e. the I/O of the memory model.


6 Lab 4 The purpose of Lab 4 is to improve on Lab 3 in three ways:

1) Put all the classes separate packages (eliminating the need for `include)

2) Use a virtual interface to mem_bus in the driver (instead of a hierarchical reference which is not allowed in a package).

3) Create a monitor class which will

a. Also use a virtual interface to mem_bus

b. Will collect coverage on the transactions on mem_bus and call $finish when addresses 0-4 have been both written

and read.

The Lab 4 testbench will contain all green blocks in Figure 3.

To examine coverage using IMC (Incisive Metrics Center) you will need to add to Makefile_common the options:

coverage functional covoverwrite

Note, you do not need to add these options to collect coverage.


Driver MonitorAssertions

DUT

Command

Signal

Agent CheckerScoreboardFunctional

Scenario GeneratorEnvironment

Figure 3: Hierarchical Testbench for Lab 4

The minimum requirements are:

1. Create a separate class to encapsulate the Generator, Agent, Driver, and Monitor

2. Use mailboxes to pass transactions between the Generator, Agent, and Driver.

3. The Generator and Agent operate only at the Transaction level.

4. All run tasks will execute forever.

5. The mailboxes must be synchronized as described in sections 7.6.4-7.6.7 of the book.

Deliverables:

1. All of your code


2. Waveform clearly showing the transactions required to achieve the coverage criteria.

7 Lab 1 Solution See SV_training_AC/lab_1/lab_1_solution for solution code

The waveform is below. Actual values for data_in, address, and order of read are random.

Below is the transcript window. Actual values and order of read are random.

# Read a 0x63

# Read a 0x8d

# Read a 0x81

# Read a 0x13d

# Read a 0x10d

# Read a 0x12

# 1400: At end of test error = 0, correct = 6



The waveform for the 0-delay my_mem model is below. Actual values for data_in, address, and order of read are random.


850: Pass: Read from address 0x998d and got 0x13d

950: Pass: Read from address 0x7b0d and got 0x176

1050: Pass: Read from address 0x5663 and got 0x10d

1150: Pass: Read from address 0xd609 and got 0x101

1250: Pass: Read from address 0x5e81 and got 0x12

1350: Pass: Read from address 0x3524 and got 0x65

Elements in data_read_queue are:

13d


176

10d

101

012

065

1350: At end of test error = 0d0 and correct = 0d6

ncsim: *E,ASRTST (./mem_if.sv,27): (time 1450 NS) Assertion top.mem_bus.write_read_assert has failed

1650: At end of test error = 0 and correct = 6

Simulation complete via $finish(1) at time 1650 NS + 2

The waveform for the 75ns delay my_mem model is below. Actual values for data_in, address, and order of read are random.


850: Pass: Read from address 0x998d and got 0x13d

950: Pass: Read from address 0x7b0d and got 0x176

1050: Pass: Read from address 0x5663 and got 0x10d

1150: Pass: Read from address 0xd609 and got 0x101


1250: Pass: Read from address 0x5e81 and got 0x12

1350: Pass: Read from address 0x3524 and got 0x65

Elements in data_read_queue are:

13d

176

10d

101

012

065

1350: At end of test error = 0d0 and correct = 0d6

ncsim: *E,ASRTST (./mem_if.sv,27): (time 1450 NS) Assertion top.mem_bus.write_read_assert has failed

1650: At end of test error = 0 and correct = 6

Simulation complete via $finish(1) at time 1650 NS + 2


The waveform is below. Actual values for data_in, address, and order of read are random.


10 Lab 4 Solution

See SV_training_AC/lab_4/lab_4_solution for solution code

The resulting waveform spans many pages to achieve 100% coverage. To see the waveform, execute the solution code.

lab manual

Documents

lab number

associative arrays lab

makefile common

systemverilog training

greg tumbush

makefile usage

makefile specific

chris spear