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Latches and
Registers
VLSI Design
1
Introduction to Latch
A device which can receive and hold
an input bit
Symbol and diagram is shown
Latch is transparent as change can be
seen on outputs 𝑄 𝑎𝑛𝑑 ഥ𝑄
The output is transferred after circuit
delay
2
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
D-Latch Symbol D-Latch Logic Diagram
Verilog Model
module d_latch (q, q_bar, d);
output q, q_bar;
input d;
always @ (d)
begin
#(t_d) q = d;
#(t_d) q_bar = ~d;
end
endmodule
Verilog Model
module d_latch_gates (q, q_bar, d);
output q, q_bar;
input d;
wire d_not;
not (d_not, d);
nor #(t_bor) g1 (q_bar, q, d);
nor #(t_bor) g2 (q, q_bar, not_d);
endmodule
Combinational Logic Design
CMOS circuit can be constructed using logic diagram or structural
description
Construct using
2 NOR Gates
1 NOT Gate
Add interconnect wiring
Custom layout would consume less area
3
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
D-Latch with Enable Control
D-Latch can be controlled by adding Enable signal
Route inputs through AND gates as shown
When En = 0
Inputs are blocked
AND outputs are ‘0’
SR Latch into a hold state
When En = 1, then inputs 𝐷 and ഥ𝐷 are admitted
4
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Behavioral Model
module d_latch ( q, q_bar,
d, enable);
output reg q, q_bar;
input d, enable;
always @ (d)
begin
#(t_d) q = d;
#(t_d) q_bar = ~d;
end
endmodule
D-Latch with Enable Control
D-Latch can be controlled by addingEnable signal
Route inputs through AND gates asshown
When En = 0
Inputs are blocked
AND outputs are ‘0’
SR Latch into a hold state
When En = 1, then inputs 𝐷 and ഥ𝐷 areadmitted
5
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Behavioral Model
module aoi_21 ( out, a, b, c);
output out;
input a, b, c;
wire w1;
and (w1, a, b);
nor (out, w1, c);
endmodule
module dlatch (q, q_bar, d, enable);
output q, q_bar;
input d, enable;
wire d_bar;
not (d_bar, d);
aoi_21 A1 (q_bar, d,
enable, q);
aoi_21 A2 (q, enable,
d_bar, q_bar);
endmodule
a
b
c
w1
D-Latch with Enable Control
D-Latch with enable can be designed as
Two AOI networks
One NOT gate
6
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Q
D
En
Q-
Registers
A group of circuits which is used to
store a word as a unit entity
Registers are very important in
designing
Sequential Circuits
State Machines
1-bit register represents a single flip-
flop
N-bit register loads and holds an n-bit
word
7
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Static Multi-Output Registers
The basic circuit has
Two-inverter storage circuit
Access transistors
An output driver
Writing process is controlled with WE signal
Two read enable signals (RE_a and RE_b) are used to demultiplex
the output to Qa and Qb
8
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Static Multi-Output Registers
Inverter 1:
The design should be sensitive to the input
reasonable drive strength for quick response
Relatively Large
Inverter 3:
Quick response to the change
Relatively Large Transistor
9
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Static Multi-Output Registers
Inverter 2:
Resists changes a input
Slow response is desired
it should be a weak transistor
10
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
What needs to be changed/added, if the clock is to
be added in this circuit
Separate Video Session for Layout Designing of this circuit
Static Multiport Register11
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Static Multi-Output Registers
An n-bit circuit is designed
using multiple of one bit circuits
No clock is used with this design
No power dissipation due to
clocking
May be useful for designs
where data is to be held for
longer time
Can be use to build register file
12
Dr. Sohaib Ayyaz QaziCOMSATS University Islamabad
Design 8-bit Register File in
Microwind whose block diagram is
shown herr