latw2011 - politecnica.pucrs.brsisc/latw/invitedtalks.pdf · incredible challenges regarding emc,...

LATW201112th IEEE Latin-American Test WorkshopInvited Talks in Special Sessions

Porto de Galinhas (PE), Brazil, March 27th - 30th, 2011

LATW201112th IEEE Latin-American Test Workshop


LOW-POWER AND THERMAL-AWARE DESIGN AND TEST ENRICO MACII, POLITECNICO DI TORINO – ITALYLETÍCIA MARIA BOLZANI PÖHLS, PUCRS - BRAZIL

3D Thermal-Aware Floorplanner for Many-Core Single-Chip SystemsDavid CUESTA*, Jose RISCO-MARTIN*, Jose AYALA* (speaker), David ATIENZA***Universidad Complutense de Madrid, Spain**EPFL, Switzerland

Heat removal and power density distribution delivery have become two major reliability concerns

include: (1) a novel multi-objective formulation to consider the thermal and performance constraints in

modelling of the architecture. The experimental work is conducted for two realistic many-core single-chip architectures: an homogeneous system resembling Intel’s SCC, and an improved heterogeneous setup. The results show promising improvements of the mean, peak temperature and the thermal gradient, with a reduced overhead in the wire length of the system.

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CHAIR:

Talk: Invited Speaker:

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INVITED TALKS IN SPECIAL SESSIONS

Test Technology Technical Council

IEEEComputer Society

Catholic University (PUCRS) - Brazil

Freescale Semiconductors, Inc.

Brazilian Microeletronics Society



RADIATION EFFECTS ON ICS FRÉDERIC SAIGNÉ / FRÉDÉRIC WROBEL, UNIV. OF MONTPELLIER II – FRANCE

Radiation Effects at Ground Level Antoine Touboul Université Montpellier 2, France

emitters contamination during technological process. From the device point of view, this constraint can

destructive effects affecting analog devices such as LDMOS,VDMOS, IGBTs, Op-Amp, etc.

of real life experiments dedicated to neutron counting and even, in some low noise environments, to

this talk about the different ways for end-users and founders to integrate the ground level radiative constraint.


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ANALOG AND MIXED-SIGNAL TEST AND DIAGNOSISFLORENCE AZAIS, LIRMM – FRANCE

Signature Based Test, Validation and Tuning of Mixed-Signal/RF SystemsAbhijit Chaterjee Georgia Tech, USA

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS

algorithms and support infrastructure need to be developed to allow low cost manufacture of complex SoCs. A novel signature-based test, validation and tuning paradigm is presented that allows rapid and

in test mechanisms as well as facilitates post-silicon validation of complex AMS/RF systems. A further

challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test truly self-healing systems in the future.




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DESIGN & TEST OF RELIABLE SOFTWARE FOR EMBEDDED SYSTEMSCRISTINE GUSMÃO, UFPE – BRAZIL

Comparing Different Test Structures in a Company Cidinha Gouveia GOTEST Consultoria e Treinamento em Tecnologia LTDA, Brazil

Rapid advances in technology have brought to the market the need of having more critical software developed in a short period of time. Delivering high-quality software on- onbudget in this

involved in adopt each test structure deal with them. This paper will report an experience deploying three organizational structures C.E.S.A.R �s project (Recife Center for Advanced Studies and Systems): Independent Integrated Test Teams and Outsourcing, telling how each structure was implemented,




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DESIGN OF ICS FOR ELECTROMAGNETIC ROBUSTNESSSONIA BEN DHIA, INSA / TOULOUSE – FRANCE

VLSI Internal Testing: a Solution to Survive CAD Less Situation for High-Reliability Devices Invited Philippe Perdu CNES – Toulouse, France

Space, aerospace, energy, defense and other professional electronic actors are facing incredible challenges regarding EMC, EOS, ESD, radiation and all the other environmental constraints their systems are under. Mass markets are driving microelectronics industry, leading to cost and performance tradeoffs far away the high and long term reliability targets needed for professional electronic applications. Lowering supply power voltage, shrinking technology and increasing integration intrinsically reduce the margins in up to date Integrated Circuits. Professional electronic applications are often running in quite harsh environment and this environment is remaining the same. High reliability and long term reliability are questioning. What can we predict on VLSI behavior after years of services? EMC, EOS, ESD and radiation robustness are appreciated at component level by testing after environmental stress. Unfortunately, we do not know potential combined effect of ageing and environmental stress on VLSI [1] even if preliminary results are encouraging [2]. Interesting solutions

One of the key issues is related to the use of commercial complex VLSI in critical applications. Microprocessors, FPGAs, Graphic chips and other DSP are considered as black box by the users: we know what is outside; we do not know what is inside. This lack of knowledge can trigger dramatic consequences: Are the tests we perform really adapted to our potential issues? Are we sure to understand how

performance management like graceful redundancy, smart power management and others let us blind?

external information about internal redundancies how can we measure redundancy consumption? Opening the dark box is possible, even for people without any CAD information. This “CAD less” approach is mostly based on internal testing techniques. Dynamic optical mapping by laser stimulation,




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First we will demonstrate how it is possible to perform full internal logic and state analysis of a VLSI, even for up to date technologies [4]. We have named this approach functional analysis as it allow us to understand the internal behavior of the device. This kind of information is not only valuable for Failure Analysis purpose, it is also a solution to check if what you ask for (ASIC) is what you get without any spy or embedded software bomb or to be sure your secured data are properly hidden. Another new technique, Laser Voltage Imaging (LVI), still under development, should allow signal tracking inside the device [5] In addition to functional analysis, we could have to localize soft defects or parametric variation. In these cases, thermal or photo electric static and dynamic laser stimulation offer a wide range of techniques to monitor slight changes inside a device under test [6], offering CAD less solution to track marginal changes inside the device [7]. We will review these laser stimulation techniques and underline how we can use them for reliability study purpose. The maturity of this technique allows unusual applications: functional Analysis has been recently performed by laser stimulation [8] This embedded tutorial will review this set of techniques that allows VLSI Internal testing without CAD when this internal information is needed. It helps to improve the previous blind situation of critical users for high quality, high security, high reliability and long term reliability VLSI.

[1] “Lifetime issues, Robustness Consequences and Reliability Challenges for Very Deep Sub Micron

2010, Beijing, China [2] “Impact of NBTI on EMC Behaviours of CMOS Inverter “, R. Fernandez et al., 2010 on Electromagnetic Compatibility (APEMC), 12 - 16 April, 2010, Beijing, China [3] “Noise Reduction in Nanometre CMOS”, M. Coenen et al., 2010 Compatibility (APEMC), 12 - 16 April, 2010, Beijing, China [4] “VLSI functional analysis by dynamic emission microscopy”, P. Perdu, J. DiBattista, Microelectronics Reliability, Volume 50, Issues 9-11, September-November 2010, Pages 1431-1435 [5] “Scan chain failure analysis using laser voltage imaging”, J. Y. Liaoa et al., Microelectronics Reliability, Volume 50, Issues 9-11, September-November 2010, Pages 1422-1426 [6] “Fault localization by Dynamic Laser Stimulation extended testing”, P. Perdu, Proceedings of 16th IEEE Symposium on Physical and Failure Analysis of Integrated Circuits, (IPFA 2009), pp 182 – 190, Suzhou, Jiangsu, China

A. Deyine et al., Proceedings of IEEE International Reliability Physics Symposium (IRPS 2009), pp 260 – 265, 26-30 April 2009, Montreal, QC, Canada [8] “Dynamic power analysis under laser stimulation:a new Dynamic Laser Simulation approach”, A. Deyine et al., to be published in ISTFA 2010 proceedings









DESIGN VERIFICATION/VALIDATION METHODS AND TOOLSUWE KURT MELCHER, UFCG – BRAZIL

Claudionor N. Coelho Jr*, Antonio Otavio Fernandes***VP of Engineering, Jasper Design Automation / Computer Science Dept., UFMG**Computer Science Department / UFMG

of time of the overall design cycle. Validation starts nowadays with architecture validation, and it ends in post-silicon debugging. Although simulation is still the main tool used in design validation nowadays,




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latw2011 - politecnica.pucrs.brsisc/latw/invitedtalks.pdf · incredible challenges regarding emc,...

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