lec 5 _ hdl-based digital design

7/31/2019 Lec 5 _ HDL-Based Digital Design

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INTRODUCTIONTO

Digital Design Using HDL(Hardware Descriptive

Language.)

2012/10/18


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How to tackle a 'million-gates' design?

De-emphasis of hand design methods - useEDA tools

o Behavioural Synthesis, Logic synthesis

o Software prototyping

Software simulator replaces thebreadboard

o Hardware design begins to carry out like

software


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Digital logic design is a 'a day to learn, a lifetimeto master'.

Technology:

o SSI MSILSIVLSIULSI

You can utilize different types of implementationtechnology (e.g. ASIC, Programmable LogicDevice) with provision up to few 'million' gates.

o What challenges are faced by modern digital

designers?o How do you tackle such a 'million-gates'

design?


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In the digital design community, the term RTLdesign is commonly used fora combination of

dataflow modeling and behavioural modeling.

Modern definition of a RTL code

o any code that is synthesizable is called RTLcode.


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DSP(Digital Signal Processing Card)

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Design Ideas

Behavioral Design

Data Path Design

Logic Design

Physical Design

Manufacturing

Flow Chart, Pseudo Code,

Bus & Register Structure

Gate Wirelist, Netlist

Transistor List, Layout,..

Chip or Board

INTRODUCTION

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Emergence of HDLs - What is a HDL?

A high-level programming language offeringspecial constructs to model microelectronic

circuits

o Describe the operation of a circuit at various

levels of abstractionBehaviour

Function

Structureo Describe the timing characteristics of a circuit

o Express the concurrency of circuit operation


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NO OTHER CHOICE (Why?)

it is very difficult to design directly on transistor-

or gate-level hardware

o for complex system, gate-level design is dead

mixed-level modeling and simulation

easier to explore different design options

reduce time and cost

Why Use the HDLs?


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HDL(Hardware Description Language)

Characteristics of digital hardware

Connections of parts

Concurrent operations

Concept of propagation delay and timing

Characteristics cannot be captured by traditional PLs

Require new language: HDL


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Specify Capture Verify Formalize Implement

HDL supportsSpecify (for design specification)

Capture (for design entry)

Verify (for design simulation)

Formalize (for documentation)

Implement (for logic synthesis)

Main Design Phases in a Development Cycle


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advantages compared to traditional schematic-based design

o design with RTL description + logic synthesistools

different levels of abstractioneasier and cheaper to explore different

design options with the aid of a logicsynthesis tool

HDL offers the mechanism to describe, testand synthesize such complex design

design reuse

Advantages of HDLs


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o functional verification can be done early

optimized to meet the desired functionality

o analogous to computer programming textual description and comments

Advantages of HDLs


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Design Entry Test Development

Synthesis Functional Simulation

Device

Fitting/Mapping Timing Simulation

Device

HDLs can be used for both

d e s i g n e n t r y a n d t e s t

development .

HDL makes it easy to build,

use and reuse lib raries of

circuit elements.

2 Main Roles of a HDL in Digital Design


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Two HDLs Used Today

VHDL and Verilog

Syntax and appearance of the two language are very different

Capabilities and scopes are quite similar

Both are industrial standards and are supported by most

software tools

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VHDL Vs Verilog HDL

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VHDL

Verilog

open standard (originated by USADoD)

oriented to system-level design orspecification

probably better for designverification tasks, but

less technology support for ASICimplementation

complex syntax and abstract steep learning curve

demanding good programmingbackground Good but too demanding for new

learners, like you

open standard (initiated by OVI)

oriented to digital circuit design

well support from EDA and ASIC

vendors C-like syntax and more intuitive

students should have some

prior programming experience

on C

shallow learning curve than

VHDL Future compatibility to Digital IC

Design modules


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Genesis of VHDL

VHDL is a language for describing digital hardware used by industry

worldwide

Multiple design entry methods and hardware description languages in use

No or limited portability of designs between CAD tools from different

vendors

Objective: shortening the time from a design concept to implementation

from 18 months to 6 months

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What is VHDL?

VHDL is the VHSIC ( Very High Speed Integrated Circuit ) Hardware

Descriptive Language.

A Simulation Modeling Language.

A Design Entity Language.

A standard Language.

A Netlist Language.

2012/10/18


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Features of VHDL Support for concurrent statements ( All elements are active

simultaneously).

Library support (user defined and system predefined ).

Sequential statements (gives software-like sequential control (e.g. case, if-then-else, loop, ).

Support for design hierarchy.

Generic design (configurable for size, physicsl characteristics, timing, loading,).

Use of subprograms.

Type declaration and usage.

- Not limited to Bit or Boolean types

- Allow integers, floating point types, as well as user defined types.

- Possibility to define new operators for the new types ).

Timing control.

Technology independent.


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Gate

Algorithmic

Behaviour

Data Flow

System

Switch

{

RTL {{

Different Levels of Abstractionof a Typical Digital System


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Levels of Abstraction

Two basic ways of representing a digital circuito Structure

primitives and connectivity

tools: schematic diagram

o Behaviour

I/O functions vs time

tools : Equations, Timing Waveforms, HDL


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Abstraction

LevelStructure Behaviour

Switchtransistors, resistors,

capacitors,

I-V diagrams,

differential equations

Gate gates, latches, flip-flops

Boolean equations, truth

tables, state diagrams, timing

diagrams

Register

adders, comparators,multiplexers, registers,

counters, queues,

datapaths, memories

flowcharts, algorihtms,

generailized FSMs

ProcessorCPU, memories, buses,

ASICs

executable specifications,

programs

Structural and Behavioural Representationat Different Levels of Abstraction


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Physical/Switch/Transistor Levelo a model that describes layout of the wires,

resistors, capacitors and transistors and

interconnections between them on an IC chip

Gate-levelo a circuit is described in terms of logic

primitives (such as AND, OR, XOR, NAND,

NOR, .), flip-flops, interconnections, logic

levels and timing properties (e.g. gate delay)


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Register Transfer Level (Dataflow)o a type of behavioural description that

describes the flow of data between registers

and how a design processes these data

o defines signal values with respect to a clocko RTL (Register Transfer Level) is frequently

used for the Verilog description with the

combination ofbehavioural and dataflow

constructs which is acceptable to logic

synthesis tools


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Behavioural Modelingo highest level of abstraction

o a component is described by its design

algorithms and/or input/output responses

o without implying any hardware details ofimplementation

o behaviour is implied by the functional

definitions of the components

o synthesis tools accept only a limited subset of

these high-level constructs



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Behaviour

RTL

Gate

Layout

CLK

QD Logic

CLK

QD

F

A

BC

D

BlackBox

F

Different Levels of Abstraction


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Behaviour

RTL

Logic

Layout

Functional timing behaviour

e.g. "after 10ns, signal Aswitches to 1"

Describe clock, dataflow,functions and events

Gate types, connections

and gate delays

Shape, dimensions, pathdelays

less

precise

more

precise

fast

simulation

slow

simulation

Information Contents

Behavioural Synthesis

Logic Synthesis

Placement & Routing

Automation Tools

Human-oriented

Machine-

oriented

Tools and Information Contents forDifferent Levels of Abstraction


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Digital Design Flow

Essential steps:o Design Entry

o RTL Simulation

o Logic Synthesis

o Verification

o Placement and Routing

o Configuration


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Design Entry

RTLHDL

FunctionalSimulation

LogicSynthesis

Fitting /Place & Route

LayoutData

TimingExtraction

Post-layoutSImulation

TestBench

SimulationLibrary

TestBench

Post-synthesisSimulation

TestBench

DesignConstraints

Gate-levelNetlist

Technology-independent

Technology-dependent

TechnologyLibrary

Modern Digital Design Flow


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DesignVerification

DesignEntry

DesignImplementation

Schematic Diagram Text-based Entry

e.g. ABEL, Verilog,VHDL

Functional andTiming Simulation

Static TimingAnalysis

In-circuit Verification

Download to a TargetPLD Device

FunctionalSimulation

Back-annotation

Optimization FPGA

- Mapping, Placement,Routing

CPLD- Fitting

Bit Stream Generation

Digital Design Flow(with a PLD as

target)


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Synthesis

Translation of a high-level design to a lower-level form

o Map a more abstract representation to an

optimized and more physical form

BehaviouralSynthesis

LogicSynthesis

Synthesis Tools Used in Modern Digital design


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Synthesis

Logic Synthesis the predominate synthesistechnology in use today

o a design is specified at the RTL level

o capable of optimizing a design with respect to

various constraints, such as area, timing,power

o an optimized gate-level implementation that is

targeted to a particular technology

o requiring a technology library to specify the

components to be used in the design


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AreaConstraints

TimingConstraints

PowerConstraints

Reports allconstraintsmet ?Technology

Libraries

Logic Synthesis Tools

HDL Description

Gate-level Netlist (Optimized)

Technology-independent

Technology-dependent

DesignConstraints

A

B

FSEL

x

y

s

_

always @(state)

begin

hwy = GREEN;

cntry = RED;

if (clear)

Q


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Synthesis

Behavioural synthesiso an emerging technology that allows a more

algorithmic specification of the system to be

synthesized

exploring design alternativesConsideration to betaken when carrying out a HDL-based design for

logic synthesis:

o synthesizable subset

o synthesis policy

o modeling style

o functionally identical vs functionally equivalent


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Circuit Description

module FA (SUM, CO, A, B CIN)

output SUM, COUT,

input A, B, CIN;

. . .. . .

endmodule

Testfixture

module testFixture;

reg A, B;

. . .

. . .. . .

endmodule

Verilog Simulator

Verilog Parser

Simulator EngineUser Interface

Graphical SimulationResults

Text ModeSimulation Results

The Verilog Simulation


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All rights transferred for Verilog

HDL to OVI

Analog Verilog ?

Publication of IEEE Standard

1364

Gateway Design Automation introduced

Verilog-XL Simulator and its proprietory HDL

Cadence acquired Gateway and its

Verilog-XL

Verilog HDL placed in the public

domain (Why ?)

1989

1985

1990

1995

The future

1991

There were numerous proprieory HDLs in the

academic and industrial sectors1980's

Developmental History of Verilog HDL


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What is Verilog HDL ?

Hardware Description Language

Mixed level modeling

o Behavioural Dataflow Structural

Switch

Single language for design and simulation Concurrency

Built-in primitives and logic functions

User-defined primitives

Built-in data types

High-level programming constructs


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What is Verilog HDL ?

Programming Language Interface Hierarchial structure and instantiation

Verilog modeling range

o From switch/transistor to

processor levelo Our main focus will be on RTL

(RegisterTransferLevel)

Gate

Algorithmic

Behaviour

Data Flow

System

Switch

{

RTL {{


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General Design Process

Understand problem and generate blockdiagram of solution

Code block diagram in Verilog HDL

Create verification script to test design

Synthesize Verilog Run static timing tool to check all thing is met

Design is mapped, placed and routed

Bitstream (*.bit) file is generated anddownloaded to target devices (e.g. FPGA or

CPLD)


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Digital Design Technologies

DigitalDesign

Methodologies

Full Custom IC Semi Custom IC

Field ProgrammableLogic

GateArray

StandardCell

Field ProgrammableGate Array

(FPGA)

Simple/ComplexPLD

(S/CPLD)

Digital Design Technologies


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Ease of Use

PLDs

FPGAs,

Gate Arrays

Standard

Cells

Full-custom

ICs

* Nonrecurring engineering cost* Design Complexity* Process complexity* Logic Density* Speed

*MarketVolumetoAmortiz

e

*TimetoPrototype

Characteristics of variousDigital Design Technologies


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No.ofLog

icGates/Ch

ip

Design Cycle / Man-Days

10 100 1,000

FPGA

GateArray/Std.Cell

ASICs

PLD

10

100

1,000

10,000

100,000

Logic Density vs Design Cycle


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TotalCost

Volume

PLDS

Gate Arrays

Fixed

Cost

Breakeven

Qty

Cost Comparison of PLDs and Gate Arrays


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Classification

Programmable Logic Device (PLD) or FieldProgrammable Logic Device (FPLD)

o a generic term that refers to any integratedcircuit used for implementing digital hardware,

where the chip can be configured by the enduser to realize different designs

o fixed architecture but functionalityprogrammable for a specific application


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PLA, PALSPLD

CPLD FPGA

PROM PROMs are not classified asPLDs since they are mainly used

for storage and special-purposeapplications.

The Evolution of the PLD Technology


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3 categories of PLDs:

1. SPLD (Simple Programmable Logic Device)

PLA(Programmable Logic Array)

PAL (Programmable Array Logic)

Registered PAL

2. CPLD (Complex Programmable Logic Device)3. FPGA(Field Programmable Gate Array)


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3 basic characteristics distinguish PLDs from eachother :

o architecture of basic functional unitso programmable interconnections

o programming technology


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Architecture of PLDs

n x p

AND Array

(Programmable)

p x m

OR Array

(Programmable)

P[0]

P[1]

P[p-1]

in[0]

in[1]

in[n-1]

out[0]

out[1]

out[p-1]

:

:

:

::

:

m outputs

p product terms

fromed from inputs

n inputs

Generic Architecture of PLDs


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PLA

o Two programmable planes:AND &ORplanes

o Any combinations of ANDs / ORs

o Sharing of AND terms across multiple ORs

o High logic density

o High fuse counto Slower than PALs

o Higher power dissipation than PALs


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Outputs

Inputs

ProgrammableAND Plane

ProgrammableOR Plane

Programmable Element(e.g. Metallic Fuse, UV

EPROM Cell)

The PLA Architecture


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PAL

o ProgrammableAND plane / Fixed ORplane

o Finite combination of ANDs / ORs

o Medium logic density

o Low fuse count

o Faster than PLAs


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Outputs

Inputs

ProgrammableAND Plane

Fixed OR Plane

Programmable Element

(e.g. Metallic Fuse, UV EPROM Cell)

The PAL Architecture


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Inputs

Fixed OR Plane

D

CLK

Q

D

CLK

Q

Programm

ableANDPlane

Clock

D or T

Flip-flops

The Registered PAL Architecture


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CPLD

o Each basic logic block is constructed from

registered PLDso Central, global interconnects

o Simple and deterministic timing

o Easily routedo PLD tools add only interconnects

o Wide, fast complex gating

o Clock speed > 300MHz


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PLD PLD PLD

PLD PLD PLD

Programmable

Interconnect

The CPLD Architecture


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LogicArray

ProductTerm

SharingArray

OutputLogic

Macrocells* Registers

Inputs

Clock

Dedicated

Inputs

Outputs

Basic PLD Block of a CPLD


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FPGA

o a regular structure of configurable logic blocks

(or modules) and interconnectso Channel-based routing

o Fine-grained configurable logic block

o Post-layout timing analysis requiredo Tools more complex than CPLDs

o Fast register pipelining


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Configurable Logic Blocks

I/OPads

Horizontal Channel

VerticalChannel Channel

Configurable Logic Blocks

Channel

Channel

Row 1

Row 2

Row 3

Row 4

(a) Matrix-based Architecture(e.g. Xilinx and QuickLogic devices)

(b) Row-based Architecture(e.g. Actel devices)

The FPGA Architecture


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Size of Logic Block

InterconnectDelay

BlockDelay

Both Interconnect Delay and Block Delay aredependent on the FPGA architecture


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FPGA

o 2 basic types of FPGAs:

o Reprogrammable (SRAM-based)

o SRAM determines interconnects

o

SRAM defines logic in Look UpTableo OTP (One-time Programmable)

o Interconnect is anti-fuseo Logic is traditional gates


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Show how the PLD shown in the Figure can be

used to implement typical 2-input logic functions:AND, OR, NAND, NOR, XORand XNOR.

Example:


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Uses of Programmable Logic Devices

3 main uses of PLDs:o Replacement ofglue logic (random logic)

o Implementing dedicated controller circuits

o Implementing finite state machines (FSM)


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o Dedicated logic functionsE.g. Flip-flop types, I/O buffers, macrocells

o Timing characteristics & speed requirementsTpd, Tsetup, Thold, .

o Power dissipationo Voltage requirements

E.g. 2.5V, 3.3V, 5V

o I/O pins availableo Packageso Special features

E.g. In-system Programmability/Testability

o CAD tools and vendor-supplied libraries


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PLD Design Flow & Tools

Design Capture

- schematics- HDL-based file

Synthesis

Device Fitting

DeviceProgramming/Downloading

Functional

SImulation

TimingSimulation

In-circuitTesting

Typical PLD Design Flow


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PLD Design Flow and Tools

CAD Tools are crucial to implementing digitalcircuits in PLDs.

PLD vendors usually offer series offree or low-cost CAD tools for users.

o Examples: ISE Webpack from Xilinx

MAX Plusfrom Altera

ispLEVERfrom Lattice SemiconductorWarpfrom Cypress

Idea


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SchematicsECS

HDL State MachineStateCAD

Design Entry

Synthesis

FittingCPLD Fitter MappingMAP/PAR

EstimationXPower

ProgrammingIMPACT Programmer

TestBenchHDL

Bencher

SimulateModelSim

XE

TranslateNGDBuild

Xilinx Synthesis Technology (XST)

CPLD FPGA

The Xilinx ISE Design Environment


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A sequential circuit is implemented into a PLD

as in the following figure

(a) Identify the architecture of the PLD device.

i) architectural type

ii) no. of inputs

iii) no. of outputs

iv) maximum number of product termsavailable for each output

(b) Write a logic equation for each output.

Example:

R'


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Q1

Q2

Q3

R

S

O4

O5

D

D

D

CLK

CLK

CLK

Q

Q

Q

Q

Q

Q

CLOCK

R

S'

S

Q2'

Q2

Q1

Q1'


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Sample Design Process

*Problem:

Design a single bit half adder with carry & enable.

*Specification:

- Passes results only on enable high.

- Passes zero on enable low.

- Result get x plus y .

- Carry gets any carry of x plus y .

Half Adder

x

yenable

carryresult

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Behavioral Design

Starting with algorithm, a high level description of the adder is created.

Half Adderxy

enable

carryresult

IF enable=1 THEN

result = x XOR y

carry = x AND y

ELSE

carry = 0

result = 0

*The model can now be simulated at this high level description to

verify correct under standing of the problem.

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Data Flow Design

With the high level description confirmed, logic equations describing the

data flow are then created.

(x AND y) AND enable

(xy OR xy ) AND enable

xy

enable

carryresult

carry = (x AND y) AND enable

result = (xy OR xy ) AND enable

*Again, the model can be simulated at this level to confirm the

logic equations

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Logic Design

Finally, the structural description is created at the gate level

*These gates can be pulled from a library of parts

x

y

xy

enablecarry

result

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o USA DoD:United States Department ofDefenseo RTL:register-transfer levelo EDA or ECAD:Electronicdesign automation is a category of

software tools for .... Logic simulation digital-simulation ofan RTL or gate-netlist's digital (boolean ...
http://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnnghttp://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnnghttp://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnnghttp://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnnghttp://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnnghttp://www.google.com.eg/url?sa=t&rct=j&q=DoD&source=web&cd=1&cad=rja&ved=0CB4QFjAA&url=http%3A%2F%2Fwww.defense.gov%2F&ei=zfqGUPi2MYXSsgaqwoGgDA&usg=AFQjCNHvKvPkmHYKerfPVK7fjuOQYdgnng

lec 5 _ hdl-based digital design

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