lect2 up110 (100324)

Lecture 110 – Linear Circuit Models (3/24/10) 10-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 110 – LINEAR CIRCUIT MODELSLECTURE ORGANIZATION

Outline• Frequency independent small signal transistor models• Frequency dependent small signal transistor model• Noise models• Passive component models• Interconnects• Substrate interference• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 86-91 and new material

Lecture 110 – Linear Circuit Models (3/24/10) Page 110-2


FREQUENCY INDEPENDENT SMALL SIGNAL TRANSISTOR MODELSWhat is a Small Signal Model?The small signal model is a linear approximation of a nonlinear model.Mathematically:

iD = 2 (vGS - VT)2 id = gmvgs

Graphically:

The large signal curve at point Q has beenapproximated with a small signal model goingthrough the point Q and having a slope of gm.

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iD = β(vGS-VT)2

id = gmvgs

vGSVGS

iD

IDQ

VT

id

vgs

Large Signal to Small Signal



Why Small Signal Models?The small signal model is a linear approximation to the large signal behavior.1.) The transistor is biased at given DC operating point (Point Q above)2.) Voltage changes are made about the operating point.3.) Current changes result from the voltage changes.If the designer is interested in only the current changes and not the DC value, then thesmall signal model is a fast and simple way to find the current changes given the voltagechanges.

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id = gmvgs

ΔiDʼ

ΔVGS

Q

id

vgs

Large SignalModel

ΔiD



How Good is the Small Signal Model?It depends on how large are the changes and how nonlinear is the large signal model.• The parameters of the small signal model will depend on the values of the large signal

model.• The model is a tradeoff in complexity versus accuracy (we will choose simplicity and

give up accuracy).• What does a simulator do? Exactly the same thing when it makes an ac analysis (i.e.

frequency response)• Regardless of the approximate nature of the small signal model, it is the primary model

used to predict the signal performance of an analog circuit.



Small-Signal Model for the Saturation RegionThe small-signal model is a linearization of the large signal model about a quiescent oroperating point.Consider the large-signal MOSFET in the saturation region (vDS vGS – VT) :

iD = WμoCox

2L (vGS - VT) 2 (1 + vDS)

The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,id gmvgs + gmbsvbs + gds vds

where

gm diD

dvGS |Q = (VGS-VT) = 2 ID

gds diD

dvDS |Q =

ID1 + VDS

IDand

gmbs d DdvBS

|Q =

diDdvGS

dvGSdvBS

|Q = -

diDdVT

dVTdvBS

|Q=

gm

2 2| F| - VBS = gm



Small-Signal Model – ContinuedComplete schematicmodel:

where

gm diD

dvGS |Q =

(VGS-VT) = 2 ID gds diD

dvDS |Q =

iD1 + vDS

iD

and

gmbs = D

vBS |Q =

iDvGS

vGS

vBS

|Q = -

iDvT

vT

vBS

|Q=

gm

2 2| F| - VBS = gm

Simplified schematic model:

A very useful assumption:gm 10gmbs 100gds

rds

G

S

gmvgsvgs

+

-gmbsvbs

vds

+

-

id

Fig. 120-0

B

vbs

+

-

G

S

B

D

G

S

B

D

S

D



Small-Signal Model for other RegionsActive region:

gm = iDvGS

|Q =

K’WVDSL (1+ VDS)

K’WL VDS gmbs =

iDvBS

|Q =

K’W VDS

2L 2 F - VBS

gds = iD

vDS |Q =

K’WL ( VGS - VT - VDS)(1+ VDS) +

ID1+ VDS

K’WL (VGS - VT - VDS)

Note:While the small-signal model analysis is independent of the region of operation, theevaluation of the small-signal performance is not.

Weak inversion region:If vDS > 0, then

iD = It WL exp

vGS-VTnVt

1 +vDSVA

Small-signal model:

gm = diDdvGS

|Q = It

WL

ItnVt

expvGS-VT

nVt1 +

vDSVA

= IDnVt

= qIDnkT =

IDVt

Cox

Cox+Cjs

gds = diDdvDS

|Q

IDVA



FREQUENCY DEPENDENT SMALL SIGNAL MODELSmall-Signal Frequency Dependent ModelThe depletion capacitors are found by evaluating the large signal capacitors at the DCoperating point.

The charge storage capacitors are constant for a specific region of operation.



Gain-bandwidth of the MOSFET (fT)

The short-circuit current gain is measure of the frequency capability of the MOSFET.Small signal model:

Small signal analysisgives,

iout = gmvgs –

sCgdvgs and vgs = iin

s(Cgs + Cgd)Therefore,

ioutiin =

gm-sCgds(Cgs + Cgd)

gms(Cgs + Cgd)

Assume VSB = 0 and the MOSFET is in saturation,

fT = 12

gmCgs + Cgd

12

gmCgs

Recalling that

Cgs 23 CoxWL and gm = μoCox

WL (VGS-VT) fT =

34

μoL2 (VGS-VT)

For velocity saturation, fT 1/L.

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iin

iout

VDDiin

iout

+

−vgs

Cgs

gmvgs

Cgd

Cbdrds



NOISE MODELSDerivation of the Thermal Noise ModelThe noise model for the MOSFET is developed for the active region as follows:In the active region, the channel resistance of the MOSFET is given from the simple largesignal model as,

Rchannel = 1

iDvDS

|Q

= 1

K’WL (VGS - VT - VDS)

1

K’WL (VGS - VT)

= 1

gm(sat)

In the saturation region, approximate the channel resistance as 2/3 the value in the activeregion giving,

Rchannel(sat) = 2

3gm(sat) = 2

3gmWe know the current thermal noise spectral density of a resistor of value R is given as

in2 = 4kTR (A2/Hz)

Substituting R by Rchannel(sat) gives the drain current MOSFET thermal noise model as,

in2 = 8kTgm

3 (A2/Hz)

Translating this drain current noise to the gate voltage noise by dividing by gm2 gives

en2 =

8kT3gm

(V2/Hz)



The Influence of the Back Gate on Thermal NoiseUsing the derivation above, we can include the influence of the bulk-source voltage on thethermal noise as follows

Rchannel(sat) = 2

3gm(eff) = 2

3(gm + gmbs) = 2

3gm(1 + )

where

= gmbs

gm

Substituting R with Rchannel(sat) gives the voltage and current noise spectral densities as,

en2 =

8kT3(gm + gmbs) (V

2/Hz) = 8kT

3gm(1 + ) (V2/Hz)

or

in2 = 8kT(gm + gmbs)

3 (A2/Hz) = 8kTgm(1 + )

3 (A2/Hz)



1/f Noise ModelAnother significant noise contribution to MOSFETs is a noise that is typically inverselyproportional to frequency called the 1/f noise.This 1/f noise spectral density is given as,

en2 =

KF2fSCoxWL K’ or in

2 = KF ID

fSCoxL2

whereKF = Flicker noise coefficientS = Slope factor of the 1/f noise

Although we do not have a good explanation for the reason why, the value of KF for aPMOS transistor is smaller than the value of KF for a NMOS transistor with the samecurrent and W/L. The current will also influence the comparative 1/f noise of the NMOSand PMOS.



MOS Device Noise at Low Frequencies

D

B

S

G

D

S

in2

B

G

NoiseFreeMOSFET

D

S

BG

NoiseFreeMOSFET

eN2

*

where

in2 =

8kTgm(1+ )3 +

KF ID

fSCoxL2 (amperes2/Hz)

= gmbs

gm

k = Boltzmann’s constantKF = Flicker noise coefficientS = Slope factor of the 1/f noise



Reflecting the MOSFET Noise to the GateDividing in

2 by gm2 gives the voltage noise spectral density as

en2 =

in2

gm2 =

8kT3gm(1+ ) +

KF2fCoxWL K’ (volts2/Hz)

It will be convenient to use B = KF

2CoxK’ to simplify the notation.

Frequency response of MOSFET noise:

060311-06

Noise SpectralDensity

log10 ffCorner

1/f noise

Thermal noise

The 1/f corner frequency is:

8kT3gm(1+ ) =

KF2fCoxWL K’ fcorner

3gmB8kTWL if gmbs = 0



MOSFET Noise Model at High FrequenciesAt high frequencies, the source resistance can no longer be assumed to be small.

Therefore, a noise current generator at the input results.MOSFET Noise Models:

G D

S S

gmvgsCgs

Cgd

rds in2 io2vin

Circuit 1: Frequency Dependent Noise Model

G D

S S

gmvgsCgs

Cgd

rdsii2 io2vin

Circuit 2: Input-referenced Noise Model

ei2

vgs

vgs

*



MOSFET Noise Model at High Frequencies – ContinuedTo find ei

2 and ii2, we will perform the following calculations:

ei2:

Short-circuit the input and find io2 of both models and equate to get ei

2 .

Ckt. 1: io2 = in

2

Ckt. 2: io2 = gm

2 ei2+ ( Cgd)2ei

2

ii2:

Open-circuit the input and find io2 of both models and equate to get ii

2 .

Ckt. 1: io2 = in

2

Ckt. 2: io2 =

(1/Cgs)(1/Cds) + (1/Cgs) 2 ii

2 + gm

2ii2

2(Cgs+Cds)2

gm

2

2Cgs2 in

2 if Cgd < Cgs ii2 =

2Cgs2

gm2 in

2

ei2 =

in2

gm2 + ( Cgd)2



PASSIVE COMPONENT MODELSResistor Models

1.) Large signal

2.) Small signalv = Ri

3.) Noise

en2 = 4kTR or in2 = 4kTG

060315-01

R(v)+ −i

v

Cp

R(v)+ −i

v

Cp1 Cp2

Distributed Model Lumped Model

060311-01

i

v

i = vR

Conductivitymodulation



Capacitor Models

1.) Large signal

2.) Small signal

q = Cv i = C(dv/dt)

3.) Do capacitors have noise? See next page.

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C(v)

Rp

Cp Cp

+ −v

i

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C

v

Linear

Nonlinear

One of the parasitic capacitorsis the top plate and the otheris associated with the bottomplate.



Switched Capacitor Circuits - kT/C NoiseCapacitors and switches generate an inherent thermal noise given by kT/C. This noise isverified as follows.An equivalent circuit for a switchedcapacitor:

The noise voltage spectral density of switched capacitor above is given as

e 2Ron = 4kTRon Volts2/Hz =

2kTRon

Volt2/Rad./sec.The rms noise voltage is found by integrating this spectral density from 0 to to give

v 2Ron =

2kTRon

0

12d

12+ 2 =

2kTRon 1

2 = kTC Volts(rms)2

where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of

fsw = 1

4RonC Hz

which is found by dividing the second relationship by the first.

060315-05

vin voutC vin voutC

Ron



Inductor ModelsR = losses of the inductorCp = parasitic capacitance to ground

Rp = losses due to eddy currents caused by magnetic flux

1.) Large Signal

2.) Small signal

= Liddt = v = L

di

dt3.) Mutual inductance

v1 = L1di1dt + M

di2dt

v2 = Mdi1dt + L2

di2dt

060316-04

L

i

Linear

Nonlinear

060316-05

+

−v1

i1 i2

+

−v2

+

−v1

i1 i2

+

−v2

L1-M

L1 L2

L2-M

M

M

k = ML1L2

Lecture 110 – Linear Circuit Models (3/24/10) 0-21


INTERCONNECTSTypes of “Wires”1.) Metal

Many layers are available in today’s technologies:- Lower level metals have more resistance (70 m /sq.)- Upper level metal has the less resistance because it is thicker (50 m /sq.)

2.) PolysiliconBetter resistor than conductor (unpolysicided) (135 /sq.)Silicided polysilicon has a lower resistance (5 /sq.)

3.) DiffusionReasonable for connections if silicided (5 /sq.)Unsilicided (55 /sq.)

4.) ViasVias are vertical metal (tungsten plugs or aluminum)

- Connect metal layer to metal layer (3.5 /via)- Connect metal to silicon or polysilicon contact resistance (5 /contact)



Ohmic Contact ResistanceThe metal to silicon contact generates resistance because of the presence of a potentialbarrier between the metal and the silicon.

Contact and Via Resistance:

Contact SystemContact

Resistance( /μm2)

Al-Cu-Si to 160 /sq. base 750

Al-Cu-Si to 5 /sq. emitter 40

Al-Cu/Ti-W/PtSi to160 /sq. base

1250

Al-Cu/Al-Cu (Via) 5Al-Cu/Ti-W/Al-Cu (Via) 5

050319-02

Metal 1

Metal 2

Metal 3

TungstenPlugs

AluminumVias

Transistors



Capacitance of WiresSelf, fringing and coupling capacitances:

CCoupling

CFringeCSelf

CCoupling

CFringeGround plane

Wide Spacing Minimum Spacing

050319-03

Capacitance Typical Value UnitsMetal to diffusion, Self capacitance 33 aF/μm2

Metal to diffusion, Fringe capacitance, minimum spacing 7 aF/μmMetal to diffusion, Fringe capacitance, wide spacing 40 aF/μmMetal to metal, Coupling capacitance, minimum spacing 85 aF/μmMetal to substrate, Self capacitance 28 aF/μm2

Metal to substrate, Fringe capacitance, minimum spacing 4 aF/μmMetal to substrate, Fringe capacitance, wide spacing 39 aF/μm



ElectromigrationElectromigration occurs if the current density is too large and the pressure of carriercollisions on the metal atoms causes a slow displacement of the metal.Black’s law:

MTF = 1

AJ 2 e(Ea/kTj)

WhereA = rate constant (cm4/A2/hr)J = current density (A/cm2)Ea = activation energy in electron volts (0.5eV for Al and 0.7eV for Cu doped Al)

k = Boltzmann’s constant (8.6x10-5 eV/K)Electromigration leads to a maximum current density,Jmax. Jmax for copper dopedaluminum is 5x105 A/cm2 at 85°C.

If t = 10,000 Angstroms and Jmax = 5x105 A/cm2, then a 10μm wide lead can conduct nomore than 50mA at 85°C.

Metal050304-04



Where is AC Ground on the Chip?AC grounds on the chip are any area tied to a fixed potential. This includes the substrateand the wells. All parasitic capacitances are in reference to these points.

p+ p p- MetalSaliciden- n n+Oxide

n-well p-well

Poly

ShallowTrench

Isolation

SidewallSpacers Polycide

Top Metal

SecondLevel Metal

FirstLevelMetal

Tungsten Plugs

Protective Insulator Layer

Substrate

Inter-mediateOxideLayers

060405-05

Metal Vias Metal Via

p+

Polycide

TungstenPlugs

Gate Ox

Salicide Salicide SalicideSalicide

TungstenPlugs

TungstenPlug

n+ n+p+ p+

ShallowTrench

Isolation

ShallowTrench

Isolation

p+n+

DC and AC GroundAC Ground

DC Ground

VDD GRD

GRD



Grounds that are Not GroundsBecause of the resistance of “wires”, current flowing through a wire can cause a voltagedrop.An example of good and badpractice: Circuit

A

Bad:

IA IA+IB IA+IB+IC

R R R

Better:

CircuitB

CircuitC

CircuitA

IAIB

IC

3R2R

R

CircuitB

CircuitC

Best:

CircuitA

R

CircuitB

CircuitC

IA R RIB IC

050305-04



Kelvin ConnectionsAvoid unnecessary ohmic drops.

A B A B

Kelvin ConnectionOhmic Connection 041223-12

X Y

In the left-hand connection, an IR drop is experienced between X and Y causing thepotentials at A and B to be slightly different.For example, let the current be 100μA and the metal be 30m /sq. Suppose that thedistance between X and Y is 100 squares. Therefore, the IR drop is

100μA x 30m /sq. x 100sq. = 0.3mV



SUBSTRATE NOISE INTERFERENCEMethods of Substrate Injection

• Hot carrier

• Leakage

• Minority Carrier

• Displacement Current (large devices)



Other Methods of Substrate Injection



Illustration of Noise Interference Mechanism – No Epi



Illustration of Noise Interference Mechanism – With Epi



How is Noise Injected into Components?MOSFETs:Injection occurs by the bulk effect on thethreshold and across the depletioncapacitance.

BJTs:Injection primarily across the depletioncapacitance.

Passives:



Isolation TechniquesIsolation techniques include both layout and circuit approaches to isolating quiet fromnoisy circuits.

ISOLATION TECHNIQUES



Isolation Techniques – Guard Rings• Collect the majority/minority carriers in the substrate• Connect the guard rings to external potentials through conductors with

- Minimum resistance

- Minimum inductance v = Ldidt



Isolation Techniques - LayoutSeparation:

Physical separation – works well for non-epi, less for epiTrenches:

Good if filled with a dielectric, not good if filled with aconductor.

Layout:Common centroid geometry doesnot help.Keep contact and via resistance to aminimum.Wells help to isolate (deep n-well)



Isolation Techniques - Noise Insensitive Circuit Design• Design for high power supply rejection ratio (PSRR)• Correlated sampling techniques – eliminate low frequency noise• Use “quiet” digital logic (power supply current remains constant)• Use differential signal processing techniques.Example of a 4th order Sigma Delta modulator using differential circuits:

CIRCUIT TECHNIQUES



Noise Isolation Techniques - Reduction of Package Parasitics• Keep the lead

inductance to aminimum (multiplebond wires)

• Package selection

Leadless lead frame: Micro surface mount device:

Still hasbond wires Minimum

inductancepackage



Summary of Substrate Interference• Methods to reduce substrate noise

1.) Physical separation2.) Guard rings placed close to the sensitive circuits with dedicated package pins.3.) Reduce the inductance in power supply and ground leads (best method)4.) Connect regions of constant potential (wells and substrate) to metal with as

many contacts as possible.• Noise Insensitive Circuit Design Techniques

1.) Design for a high power supply rejection ratio (PSRR)2.) Use multiple devices spatially distinct and average the signal and noise.3.) Use “quiet” digital logic (power supply current remains constant)4.) Use differential signal processing techniques.

• Some references1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques forSubstrate Noise in Mixed-Signal IC’s,” J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-430.2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, “Voltage-Comparator-BasedMeasurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs,” J. of Solid-StateCircuits, vol. 31, No. 5, May 1996, pp. 726-731.3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.



SUMMARY• Small signal models are a linear representation of the transistor electrical behavior• Including the transistor capacitors in the small signal model gives frequency dependence• Noise models include thermal and 1/f noise voltage or current spectral density models• Passive component models include the nonlinearity, small signal and noise models• Interconnects include metal, polysilicon, diffusion and vias• Electromigration occurs if the current density is too large causing a displacement of

metal• Substrate interference is due to interaction between various parts of an integrated circuit

via the substrate• Method to reduce substrate interference include:

- Physical separation- Guard rings- Reduced inductance in the power supply and ground leads- Appropriate contacts to the regions of constant potential- Reduce the source of interfering noise- Use differential signal processing techniques

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