lect2 up360 (100329)

Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) Page 360-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 360 – CHARACTERIZATION OF ADCS AND SAMPLEAND HOLD CIRCUITSLECTURE ORGANIZATION

Outline• Introduction to ADCs• Static characterization of ADCs• Dynamic characteristics of ADCs• Sample and hold circuits• Design of a sample and hold• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 652-665



INTRODUCTIONGeneral Block Diagram of an Analog-Digital Converter

DigitalProcessor

Prefilter Sample/Hold Quantizer Encoder

x(t) y(kTN)

Fig.10.5-1

• Prefilter - Avoids the aliasing of high frequency signals back into the baseband of theADC

• Sample-and-hold - Maintains the input analog signal constant during conversion• Quantizer - Finds the subrange that corresponds to the sampled analog input• Encoder - Encoding of the digital bits corresponding to the subrange



Nyquist Frequency Analog-Digital ConvertersThe sampled nature of the ADC places a practical limit on the bandwidth of the input

signal. If the sampling frequency is fS, and fB is the bandwidth of the input signal, thenfB < 0.5fS

which is simply the Nyquistrelationship which states thatto avoid aliasing, thesampling frequency must begreater than twice thehighest signal frequency.

fB-fB 0 f

fB-fB 0 fSfS-fB fS+fB 2fS2fS-fB 2fS+fBf

-fB 0 fS 2fSf

AntialiasingFilter

fS2

fB-fB 0f

fS2

fS2

fS

fS

Continuous time frequency response of the analog input signal.

Sampled data equivalent frequency response where fB < 0.5fS.

Case where fB > 0.5fS causing aliasing.

Use of an antialiasing filter to avoid aliasing.

Fig. 10.5-



Classification of Analog-Digital ConvertersAnalog-digital converters can be classified by the relationship of fB and 0.5fS and by theirconversion rate.• Nyquist ADCs - ADCs that have fB as close to 0.5fS as possible.• Oversampling ADCs - ADCs that have fB much less than 0.5fS.

Classification of Analog-to-Digital Converter Architectures

ConversionRate Nyquist ADCs Oversampled ADCs

Slow Integrating (Serial) Very high resolution <14-16 bits

MediumSuccessive

Approximation1-bitPipeline Algorithmic

Moderate resolution <10-12 bits

FastFlash Multiple-bit

Pipeline Folding andinterpolating

Low resolution < 6-8 bits

Lecture 360 – Characterization of ADCs and Sample and Hold Circuits (3/29/10) 60-5


STATIC CHARACTERIZATION OF ANALOG-TO-DIGITAL CONVERTERSDigital Output Codes

Digital Output Codes used for ADCs

Decimal Binary Thermometer Gray Two’sComplement

0 000 0000000 000 0001 001 0000001 001 1112 010 0000011 011 1103 011 0000111 010 1014 100 0001111 110 1005 101 0011111 111 0116 110 0111111 101 0107 111 1111111 100 001



Input-Output CharacteristicsIdeal input-output characteristics of a 3-bit ADC

Analog Input Value Normalized to VREF

000

001

010

011

100

101

110

111

Dig

ital O

utpu

t Cod

e

Ideal 3-bitCharacteristic

Figure 10.5-3 Ideal input-output characteristics of a 3-bit ADC.

Infinite ResolutionCharacteristic

1 LSB

18

28

38

48

58

68

08

78

1 LSB

vinVREF

0.5

1.0

0.0-0.5Q

uant

izat

ion

Noi

se L

SBs

88



Definitions• The dynamic range, signal-to-noise ratio (SNR), and the effective number of bits

(ENOB) of the ADC are the same as for the DAC• Resolution of the ADC is the smallest analog change that distinguishable by an ADC.• Quantization Noise is the ±0.5LSB uncertainty between the infinite resolution

characteristic and the actual characteristic.• Offset Error is the difference between the ideal finite resolution characteristic and

actual finite resolution characteristic• Gain Error is the

difference betweenthe ideal finiteresolution charact-eristic and actualfinite resolutioncharacteristicmeasured at full-scale input. Thisdifference isproportional to theanalog inputvoltage.

000

001

010

011

100

101

110

111

vinVREF

Dig

ital O

utpu

t Cod

e

Offset = 1.5 LSBs

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

Dig

ital O

utpu

t Cod

e

Gain Error = 1.5LSBs

(a.) (b.)Figure 10.5-4 - (a.) Example of offset error for a 3-bit ADC. (b.) Example of gainerror for a 3-bit ADC.

IdealCharacteristic

IdealCharacteristic

08

18

28

38

48

58

68

78

88

ActualCharacteristic



Integral and Differential NonlinearityThe integral and differential nonlinearity of the ADC are referenced to the vertical

(digital) axis of the transfer characteristic.• Integral Nonlinearity (INL) is the maximum difference between the actual finite

resolution characteristic and the ideal finite resolution characteristic measured vertically(% or LSB)

• Differential Nonlinearity (DNL) is a measure of the separation between adjacent levelsmeasured at each vertical step (% or LSB).

DNL = (Dcx - 1) LSBs

where Dcx is the size of the actual vertical step in LSBs.

Note that INL and DNL of an analog-digital converter will be in terms of integers incontrast to the INL and DNL of the digital-analog converter. As the resolution of theADC increases, this restriction becomes insignificant.



Example of INL and DNL

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

Dig

ital O

utpu

t Cod

e

Example of INL and DNL for a 3-bit ADC.) Fig.10.5-5

IdealCharacteristic


INL =+1LSB

INL =-1LSB

DNL =+1LSB

DNL =0 LSB

Note that the DNL and INL errors can be specified over some range of the analog input.



MonotonicityA monotonic ADC has all vertical jumps positive. Note that monotonicity can only bedetected by DNL.Example of a nonmonotonic ADC:

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

Dig

ital O

utpu

t Cod

e

DNL =-2 LSB


IdealCharacteristic

Fig. 10.5-6LIf a vertical jump is 2LSB or greater, missing output codes may result.If a vertical jump is -1LSB or less, the ADC is not monotonic.



Example 360-1 - INL and DNL of a 3-bit ADC

Find the INL and DNL for the 3-bit ADC shown on the previous slide.SolutionWith respect to the digital axis:1.) The largest value of INL for this 3-bit ADC occurs between 3/16 to 5/16 or 7/16 to

9/16 and is 1LSB. 2.) The smallest value of INL occurs

between 11/16 to 12/16 and is-2LSB.

3.) The largest value of DNL occurs at3/16 or 6/8 and is +1LSB.

4.) The smallest value of DNL occursat 9/16 and is -2LSB which iswhere the converter becomesnonmonotonic.

000

001

010

011

100

101

110

111

08

18

28

38

48

58

68

78

88

vinVREF

Dig

ital O

utpu

t Cod

e

DNL =-2 LSB


IdealCharacteristic

Fig. 10.5-6DL

INL =+1LSB

INL =-2LSB

DNL =+1 LSB



DYNAMIC CHARACTERISTICS OF ADCsWhat are the Important Dynamic Characteristics for ADCs?

The dynamic characteristics of ADCs are influenced by:• Comparators

- Linear response- Slew response

• Sample-hold circuits• Circuit parasitics• Logic propagation delay



ComparatorThe comparator is the quantizing unit of ADCs.

Open-loop model:

+

-Av(s)ViVi

VOS

Ri

RoVo

V1

V2Comparator Fig.10.5-7Nonideal aspects:• Input offset voltage, VOS (a static characteristic)

• Propagation time delay- Bandwidth (linear)

Av(s) = Av(0)s

c+ 1

= Av(0)

s c + 1

- Slew rate (nonlinear)

T = C· V

I (I constant) = V

Slew Rate



SAMPLE AND HOLD CIRCUITSRequirements of a Sample and Hold CircuitThe objective of the sample and hold circuit is to sample the unknown analog signal andhold that sample while the ADC decodes the digital equivalent output.The sample and hold circuit must:

1.) Have the accuracy required for the ADC resolution, i.e. accuracy = 100%

2N

2.) The sample and hold circuit must be fast enough to work in a two-phase clock. For anADC with a 100 Megasample/second sample rate, this means that the sample and holdmust perform its function within 5 nanoseconds.3.) Precisely sample the analog signal at the same time for each clock. An advantage ofthe sample and hold circuit is that it removes the precise timing requirements from theADC itself.4.) The power dissipation of the sample and hold circuit must be small. Unfortunately,the above requirements for accuracy and speed will mean that the power must beincreased as the bits are increased and/or the clock period reduced.



Sample-and-Hold CircuitWaveforms of a sample-and-holdcircuit:

Definitions:• Acquisition time (ta) = time requiredto acquire the analog voltage• Settling time (ts) = time required tosettle to the final held voltage to withinan accuracy tolerance

Tsample = ta + ts Maximum sample rate = fsample(max) = 1

Tsample

Other consideratons:• Aperture time= the time required for the sampling switch to open after the S/Hcommand is initiated• Aperture jitter = variation in the aperture time due to clock variations and noiseTypes of S/H circuits:• No feedback - faster, less accurate• Feedback - slower, more accurate

ta ts

Hold Sample HoldS/H Command

vin*(t)

vin*(t)vin(t)

vin(t)

Time

Am

plitu

de

Fig.10.5-9

Output of S/Hvalid for ADC

conversion



Open-Loop, Buffered S/H CircuitCircuit:

+-

φvin(t)vout(t)

CHSwitchClosed

(sample)

SwitchOpen(hold)

SwitchClosed

(sample)

vin(t)vout(t)

vin(t), vout(t) vin(t), vout(t)

Time

Am

plitu

de

Fig.10.5-10

Attributes:• Fast, open-loop• Requires current from the input to charge CH

• DC voltage offset of the op amp and the charge feedthrough of the switch will create dcerrors



Settling TimeAssume the op amp has a dominant pole at - a and a second pole at -GB.

The unity-gain response can be approximated as, A(s) GB2

s2 + GB·s + GB2

The resulting step response is, vout(t) = 1 - 43 e-0.5GB·t sin

34 GB·t +

Defining the error as the difference between the final normalized value and vout(t), gives,

Error(t) = = 1 - vout(t) = 43 e-0.5GB·t

In most ADCs, the error is equal to ±0.5LSB. Since the voltage is normalized,1

2N+1 = 43 e-0.5GB·ts e-0.5GB·ts =

43 2N

Solving for the time, ts, required to settle with ±0.5LSB from the above equation gives

ts = 2

GB ln43 2N =

1GB [1.3863N + 1.6740]

Thus as the resolution of the ADC increases, the settling time for any unity-gain bufferamplifiers will increase. For example, if we are using the open-loop, buffered S/H circuitin a 10 bit ADC, the amount of time required for the unity-gain buffer with a GB of 1MHzto settle to within 10 bit accuracy is 2.473μs.



Open-Loop, Switched-Capacitor S/H CircuitCircuit:

+-

φ1dφ1φ2

vin(t) vout (t)C

+-

φ1dφ1φ2

vin(t) vout (t)

C

+-

C

φ2 φ1

φ1d

+

-

+

-

Fig.10.5-11

Switched capacitor S/H circuit. Differential switched-capacitor S/H

• Delayed clock used to remove input dependent feedthrough.• Differential version has lower PSRR, cancellation of even harmonics, and reduction of

charge injection and clock feedthrough



Open-Loop, Diode Bridge S/H CircuitDiode bridge S/H circuit:

VDD

060927-01

vIN(t) vOUT(t)

CH

IBClock

IBClock

vIN(t) vOUT(t)

CH

rd rd

rd rdRON = rd

Sample phase - diodesforward biased.

vIN(t) vOUT(t)

CHROFF = ∞

Hold phase - diodesreversed biased.

D1 D2

D3 D4

Blowthru Capacitor

MOS diode bridge S/H circuit:VDD

060927-02

vIN(t) vOUT(t)

CH

IBClock

IBClock

vIN(t) vOUT(t)

CH

gm

RON = 1/gm

Sample phase - MOSdiodes forward biased.

vIN(t) vOUT(t)

CHROFF = ∞

Hold phase - MOSdiodes reversed biased.

1gm1

gm1

gm1

M1 M2 M3 M4

Blowthru Capacitor



Practical Implementation of the Diode Bridge S/H Circuit

060927-03

IB IB

VDD

VSS

CH

vout(t)vin(t)

D1 D2

D3 D4 +-

2IB

D5

D6SampleHold

M1 M2

Practical implementation of the diode bridge sample and hold (sample mode).

IB IB

VDD

VSS

CH

vout(t)vin(t)

D1 D2

D3 D4 +-

2IB

D5

D6SampleHold

M1 M2

2IB

IB

IB

Hold mode.

IB2

IB2

During the hold mode, the diodes D5 and D6 become forward biased and clamp the upperand lower nodes of the sampling bridge to the sampled voltage.



Closed-Loop S/H CircuitCircuit:

+-

+-

φ1

φ1

φ2

CH

vout(t)

vin(t)

+- +

-φ1

φ2

CH

vout(t)vin(t)

Fig.10.5-13

Closed-loop S/H circuit. φ1 is the sample phase and φ2 is the hold phase.

An improved version.

Attributes:• Accurate• First circuit has signal-dependent feedthrough• Slower because of the op amp feedback loop



Closed-Loop, Switched Capacitor S/H CircuitsCircuit:

+- vout(t)vin(t) φ1d

φ1

φ2

CH +-

φ2

φ1 φ2dφ1d

φ2 φ1d

φ2d

φ1d

φ2d

φ1d φ2

φ1

φ2φ1

CH

CH

CH

CH

CH

CH

vout(t)vin(t)

+

-

+

-

φ1 φ2d

-+

070616-02

Switched capacitor S/H circuitwhich autozeroes the op ampinput offset voltage.

A differential version that avoids large changes at the op amp output

New charge (φ2)

Old charge (φ2)

New charge (φ2)

Old charge (φ2)

Attributes:• Accurate• Signal-dependent feedthrough eliminated by a delayed clock• Differential circuit keeps the output of the op amps constant during the 1 phase

avoiding slew rate limits



Current-Mode S/H CircuitCircuit:

VDD

IB

CH

φ1φ1

φ2

iin iout

Fig.10.5-15Attributes:• Fast• Requires current in and out• Good for low voltage implementations



Aperature Jitter in S/H CircuitsIllustration:

If we assume that vin(t) =Vpsin t, then themaximum slope is equal to

Vp.

Therefore, the value of Vis given as

V = dvindt t = Vp t .

The rms value of this noise is given as

V(rms) = dvindt t =

Vp t

2 .

The aperature jitter can lead to a limitation in the desired dynamic range of an ADC. Forexample, if the aperature jitter of the clock is 100ps, and the input signal is a full scalepeak-to-peak sinusoid at 1MHz, the rms value of noise due to this aperature jitter is111μV(rms) if the value of VREF = 1V.

Analog-DigitalConverter

Clock

AnalogInput

DigitalOutput ΔV

t

vin

Aperature Jitter = ΔtFigure10.5-14 - Illustration of aperature jitter in an ADC.

vin(to)

to



DESIGN OF A SAMPLE AND HOLD AMPLIFIERSpecificationsAccuracy = 10 bitsClock frequency is 10 MHzPower dissipation 1mWSignal level is from 0 to 1VSlew rate 100V/μs with CL = 1pFUse 0.25μm CMOS

Technology Parameters (Cox = 60.6x10-4 F/m2):

Typical Parameter ValueParameter

SymbolParameter Description

N-Channel P-Channel

Units

VT0Threshold Voltage(VBS = 0)

0.5± 0.15 -0.5 ± 0.15 V

K' Transconductance Para-meter (insaturation)

120.0 ± 10% 25.0 ± 10% μA/V2

Bulk thresholdparameter

0.4 0.6 (V)1/2

Channel lengthmodulation parameter

0.32 (L=Lmin)0.06 (L 2Lmin)

0.56 (L=Lmin)0.08 (L 2Lmin)

(V)-1

2| F| Surface potential at strong inversion 0.7 0.8 V



Op Amp DesignGain:

Gain error = 1

1+Loop Gain 0.5 LSB = 1

211

Therefore, the op amp gain 211 = 2048 V/VChoose the op amp gain as 5000 V/V

Gainbandwidth:For a dominant pole op amp with unity-gain feedback, the relationship between the

gain-bandwidth (GB), accuracy (N) and speed (ts) is

ts = N+1GB ln(2) = 0.693

N+1GB

Therefore, if ts 0.5 Tclock = 50 ns (choose ts = 10 ns). For N = 10, the gain-bandwidthis

GB = 0.762x109 = 120 MHzDominant pole is 24 kHz and with an output capacitance of 1pF this means the outputresistance of the op amp must be 6.6 M .



Op Amp Design – ContinuedThe previous specifications suggest a

self-compensated op amp. The gain andoutput resistance should be easy to achievewith a cascaded output. A folded-cascodeop amp is proposed for the design. Inorder to have the 0-1V signal range, a p-channel, differential input is selected. Thiswill give the input 0-1V range. The outputwill effectively be 0-1V with the unity gainfeedback around the op amp.

Bias Currents:The 100V/μs slew rate requires I3 = 100μA. Setting I4 = I5 = 125μA gives a powerdissipation of 0.875mW with VDD = 2.5V.

061021-01

VNB1

M4 M5

I6

VPB2

I4 I5

VDD = 2.5V

I7M6 M7

VNB2

M8 M9

M10 M11

+

−vIN vOUT

VPB1

I1 I2

M1 M2

M3

I3

CL



Op Amp Design – ContinuedTransistor sizes:Design M4-M7 to give a saturation voltage of 0.1V with 125μA.

W4L4 =

W5L5 =

W6L6 =

W7L7 =

2IDKn'·VDS(sat)2 =

2·125120·0.01 200

Since the upper swing is not as important, choose a saturation voltage of 0.25 for M8 –M11.

W8L8 =

W9L9 =

W10L10 =

W11L11 =

2IDKp'·VDS(sat)2 =

2·12525·0.0625 = 160

To get the GB of 120 MHz, this implies the gm of M1 and M2 is

gm = GB·CL = (120x106·2 )(10-12) = 762 μS

W1L1 =

W2L2 =

gm2

2IDKp' = 762·7622·25·50 = 232

Let the upper input common mode voltage be 1.5V which gives the W/L of M3 as,

1V = VSG1 + VSD3 = 0.631 + VSD3 VSD3 = 0.369V W3L3 60



Op Amp Design – ContinuedWe now need to check the output resistance and the gain to make sure the specificationsare satisfied. Let us choose twice minimum channel length to keep the capacitiveparasitics minimized and not have the output resistance too small. Therefore at quiescentconditions,

rds5 = 133k , rds7 = 222k , gm7 = 1.935mS and rds2 = 250k

Routdown (rds5||rds2)gm7rds7 = 37.29M

rds9 =rds11 = 167k , and gm11 = 1.697mS

Routup rds11gm9rds9 = 47.33M

Rout 20.86M

The low frequency gain is,Av gm1Rout

= 762μS·20.86M = 15,886 V/VThe frequency response will be as shown:

061023-02

log10f

15,886

Gain

5,000

24kHz 120MHz

7.55kHz1



Op Amp Bias VoltagesWe also need to design the bias voltages VNB1, VNB2, VPB1 and VPB2. This can be doneusing the following circuit:Note, the W/L of M3, M4 and M7 will be 6 so thata current of 10μA gives 100μA in M3 of the opamp. Also, W/L of M1 and M5 will be 16 so acurrent of 10μA gives 125μA in M4 and M5 of theop amp.If M2 is 4 times larger than M1, which gives a W/Lof 64 for M2. Under these conditions,

I2 = I1 = 1

2ß1R2 R = 106

2·120·16·10 = 5.1k

The extra 40 A brings the power dissipation to

0.975mW which is still in specification.

The W/L of M6 and M8 are designed as follows:

VGS8 = VT + 2VON VGS8 - VT = 0.2V = 2·10

120·(W8/L8) W8L8 = 4.167

VSG6 = |VT| + 2VON VSG6 - |VT| = 0.5V = 2·10

25·(W6/L6) W6L6 = 3.20

061021-02

VDD

VPB1

VPB2

VNB2

VNB1

M1 M2

M3 M4

M5

M6M7

M8

R

10µA 10µA10µA

10µA



Switch and Hold Capacitor DesignSwitch:

Since the signal amplitude is from 0 to 1V, a single NMOS switch should besatisfactory. The resistance of a minimum size NMOS switch is,

RON(worst case) 1

Kn'(W/L)(VGS-VT) = 106

120(1)(1.5-0.5) = 8.33k

For a CH = 1pf, the time constant is 8 ns. This is too close to the 50 ns so let us increasethe switch size to 0.5μm/0.25μm which gives a time constant of 4ns.Therefore, the W/L ratio of the NMOS switch is 0.5μm/0.25μm and the hold capacitor is1pf.Check the error due to channel injection and clock feedthrough-If we assume the clock that rises and falls in 1ns, then a 0.5μm/0.25μm switch works inthe fast transition region. The channel/clock error can be calculated as:

Verror = -W·CGDO +

Cchannel

2CL

VHT -V

3HT

6U·CL -

W·CGDOCL

(VS+2VT -VL)



Switch and Hold Capacitor Design – Continued

Assuming CGDO is 200x10-12 F/m we can calculate VHT as 0.8131V. Thus,Verror =

-100x10-18+0.5(7.57x10-16)

1x10-12 0.8131-0.105x10-3

15x10-3 - 100x10-18

1x10-12 (1+1-0) = -0.586mV

For a 1volt signal with 10 bit accuracy, the error must be less than 1LSB which is0.967mV. The channel/clock error is close to this value and one may have to considerusing a CMOS switch or a dummy switch to reduce the error.



Design SummaryAt this point, the analog designer understands the weaknesses and strengths of thedesign. The next steps will not be done but are listed below:1.) Simulation to confirm and explore the hand-calculated performance2.) Layout of the op amp, hold capacitor and switch.3.) Verification of the layout4.) Extraction of the parasitics from the layout5.) Resimulation of the design.6.) Check for sensitivity to ESD and latchup.7.) Select package and include package parasitics in simulation.



SUMMARY• An ADC is by nature a sampled data circuit (cannot continuously convert analog into

digital)• Two basic types of ADCs are:

- Nyquist – analog bandwidth is as close to the Nyquist frequency as possible- Oversampled – analog bandwidth is much smaller than the Nyquist frequency

• The active components in an ADC are the comparator and the sample and hold circuit

• A sample and hold circuit must have at least the accuracy of 100%/2N

• Sample and hold circuits are divided into two types:- Open loop which are fast but not as accurate- Close loop which are slower but more accurate

• An example of designing a sample and hold amplifier was given to illustrate theelectrical design process for CMOS analog circuits

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