lecture 21.pdf

8/10/2019 lecture 21.pdf

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The Five Classic Components of a

Computer

Input (mouse, keyboard, )

Output (display, printer, )

Memory

main (DRAM), cache (SRAM) secondary (disk,

CD, DVD, )

Datapath

Control

Input

Processor

Control

Datapath

Output

Memory10010100101100000010100101010001

1111011101100110

1001010010110000

1001010010110000

1001010010110000

Processor

(CPU)


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CPU Operations

Fetch a word from Memory

Store a word into memory

Reg Transfers

Performing an ALU function


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A CISC PROCESSOR

Larger instructions with variable formats(16-64 bits/ instruction)

Larger Addressing Modes (12- 24)

Few Registers

Most Microcoded with control Memory

Close to high level language


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Reduced Instruction Set Computer

LOAD- STORE Architecture

Fewer Addressing ModesFixed Length Instructions

More Registers

Designed for Pipeline Efficiency

Hardwired Control Unit


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Instruction Cycle

Two steps:

Fetch

Execute


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Functional Blocks in a Processor


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REG SET

ALU

CLU

CENTRAL PROCESSING UNIT


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ARITHMETIC LOGIC UNIT

F1 F2

MUX

A B

SEL LINES

CONTROL

LINES

R


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Instruction set Summary

Instruction Formats

Operations

Addressing Modes

Programmers Registers


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A TYPICAL INSTRUCTION

- ADD R1, D2(B2)

(R1, B2 - Registers ), D2- displacement

(R1) + (Memory) (R1) ; (B2) + D2 Memory

5A R1 B2 D20 15 16 31


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Steps in Execution of an Instruction

CPU fetches instruction from Main Memory

CPU Decodes the Instruction Op-code

Depending on Op-code

- Fetches another operand

- Execute instruction via register to register transfer

- Write the results in M- Write the results in I/O

Repeat steps


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Steps for executing instruction

- Fetch the first instruction half-word

- Find ADD control sequence

- Fetch the remaining instruction half-word

- Calculate the operand address

- Fetch the operand

- Add

- Store the result


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Instruction Decoder

IR

PC

MAR

MDR

R0

Rn-1

Y

ALU

Z

Address Bus

Data Bus

CPUBu

s

A BControl Lines

Clear Y


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Register Transfer:

R2 R1

To enable data transfer between various

Blocks connected to common bus provideInput output gating.


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R

Rin

Rout


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R

Rin

Rout

Control Signals for

R1 R2

R 2OUT , R 1in


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Example Microinstructions:

Open/.Close a gate from Reg to a bus

Transfer data along a bus

Send timing signals

Test bits within a register


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Fetching a word from memory:

i. MAR (R1)

ii. Read Signal

iii. Wait for Memory-function-complete

(MFC) signal

iv. R2 (MDR)


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Storing a word into Memory:

i. MAR (R1)ii. MDR (R2)

iii. Memory write signal

iv. Wait for MFC


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Instruction Decoder

IR

PC

MAR

MDR

R0

Rn-1

Y

ALU

Z

Address Bus

Data Bus

CPUBu

s

A BControl Lines

Clear Y


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R

Rin

Rout

ALU

Y

Z

Zout

Zin

Yin

Control Signals for

R1 R2

R 2OUT , R 1in


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Performing an Arithmetic or Logic

Operation:

i. R1out, Yin

ii. R2out, Add, Zin

iii. Zout, R3in

R

Rin

Rout

ALU

Y

Z

Zin

Yin


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Ex: Add contents of a memorylocation to register R1

(Address of Memory location is in part

of the instruction )


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Step RTL Control Sequence

T1 MAR

PC; PC PC+1 PCout, MARin, Clear Y, Set

Carryin of ALU, ADD, Zin,

READ

Ex: Add contents of a memory

location to register R1


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T4 MAR IR Addr-field of IRout, MARin,

READ

T5 Y R1 R1out, Yin, Wait for MFC

T6 Z Y + M[MAR] MDRout, ADD, Zin

T7 R1 Z Zout, R1in, END

Ex: Add contents of a memory

location to register R1


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T1 MARPC; PCPC+1 PCout, MARin, Clear Y, Set

Carryin of ALU, ADD, Zin,

READ

T2 Wait Zout, PCin, Wait for MFC

T3 IRMDR MDRout, IRin

T4 YPC PCout, Yin

T5 Z

Y + [x of IR] ADD, ZinAddr-field of IRout

T6 PCZ Zout, PCin, END

Ex: Branch by an offset x

lecture 21.pdf

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