lecture 9 combinational automatic test- pattern...

Lecture 9Combinational Automatic Test-

Pattern Generation (ATPG) Basics• Algorithms and representations• Structural vs. functional test• Definitions• Search spaces• Completeness• Algebras• Types of Algorithms

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 1

Origins of Stuck-Faults

• Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer

• Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faults

• Seshu & Freeman (1962) – Use of stuck-faults for parallel fault simulation

• Poage (1963) – Theoretical analysis of stuck-at faults


Functional vs. Structural ATPG


Carry Circuit


Functional vs. Structural(Continued)

• Functional ATPG – generate complete set of tests for circuit input-output combinations– 129 inputs, 65 outputs:– 2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns– Using 1 GHz ATE, would take 2.15 x 1022 years

• Structural test:– No redundant adder hardware, 64 bit slices– Each with 27 faults (using fault equivalence)– At most 64 x 27 = 1088 faults (tests)– Takes 0.000001088 s on 1 GHz ATE

• Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ %


Definition of Automatic Test-Pattern Generator

• Operations on digital hardware:– Inject fault into circuit modeled in computer– Use various ways to activate and propagate fault effect through hardware

to circuit output– Output flips from expected to faulty signal

• Electron-beam (E-beam) test observes internal signals – “picture” of nodes charged to 0 and 1 in different colors– Too expensive

• Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode– Can shift state in, scan state out– Widely used – makes sequential test combinational– Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence


Circuit and Binary Decision Tree


Binary Decision Diagram• BDD – Follow path from source to sink node –

product of literals along path gives Boolean value at sink

• Rightmost path: A B C = 1• Problem: Size varies greatly

with variable order


Algorithm Completeness

• Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test

• Untestable fault – no test for it even after entire tree searched

• Combinational circuits only – untestablefaults are redundant, showing the presence of unnecessary hardware


Algebras: Roth’s 5-Valued and Muth’s 9-Valued

SymbolDD01X

G0G1F0F1


Meaning1/00/10/01/1X/X0/X1/XX/0X/1

FailingMachine

0101XXX01

GoodMachine

1001X01XX

Roth’sAlgebra

Muth’sAdditions

Roth’s and Muth’s Higher-Order Algebras

• Represent two machines, which are simulated simultaneously by a computer program:– Good circuit machine (1st value)– Bad circuit machine (2nd value)

• Better to represent both in the algebra:– Need only 1 pass of ATPG to solve both– Good machine values that preclude bad machine values become obvious

sooner & vice versa• Needed for complete ATPG:

– Combinational: Multi-path sensitization, Roth Algebra– Sequential: Muth Algebra -- good and bad machines may have different

initial values due to fault


Exhaustive Algorithm

• For n-input circuit, generate all 2n input patterns

• Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs– Perform exhaustive ATPG for each cone– Misses faults that require specific activation

patterns for multiple cones to be tested


≤

Detecting Stuck-at Faults

A

BZ

Inputs Fault Free Faulty Responses

AB Response A/0 B/0 Z/0 A/1 B/1 Z/1

00 0 0 0 0 0 0 1

01 0 0 0 0 1 0 1

10 0 0 0 0 0 1 1

11 1 0 0 0 1 1 1

13

Sequential Circuit

R

S

QA

2

1

Inputs FF Faulty Response

SR Response A/0 S/0 R/0 A/1 S/1 R/1

01 0 0 0 X 0 0 1

00 0 1 0 X 1 0 1

10 1 1 0 1 0 1 1

11 0 0 0 1 1 1 1 14

Types ofTesting

15

Types of Tests

• The exhaustive test used to detect the faults on a 2-input AND gate is not practical for circuits with 20 or more primary inputs

• Pseudo-exhaustive: exhaustive for components in the circuits– segmentation or partitioning

• A random test is also viable to detect faults, but pseudo-exhaustive tests are more realistic for Stuck-at Faults

• Deterministic or fault oriented tests

16

Functional Testing

Exhaustive & pseudo-exhaustive testing :

Partial dependence circuits:-a circuit in which primary outputs (PO) depend on all the primary inputs (PI)

- each output tested using 2ni

inputs (ni < n shows inputs affecting PO)

17

Functional Testing

Example :

Exhaustive & pseudo-exhaustive testing

Exhaustive test for each gate

x y

18

Functional Testing

• the circuit is partitioned into segments such that each segment has small number of inputs

• each segment is tested exhaustively• usually inputs & output of each segment are not PIs

or POs so we need to control segment inputs using PIs and observe its outputs using PO - this lead to sensitizing partitioning

Exhaustive & pseudo-exhaustive testing Partitioning technique :

19

Functional Testing

Example : Consider the following circuit :

20

Functional Testing

Example: the following shows 8 input vectors to test exhaustively h.

21

Functional Testing

Example: Add vectors 5 - 8 to test exhaustively g and 9 -10 to test exhaustively y

22

Functional Testing

Example: Add missing combinations to vectors 4 and 9 to test exhaustively x

23

17: Design for Testability Slide 24

Test Pattern Generation

• Manufacturing test ideally would check every node in the circuit to prove it is not stuck.

• Apply the smallest sequence of test vectors necessary to prove each node is not stuck.

• Good observability and controllability reduces number of test vectors required for manufacturing test.– Reduces the cost of testing– Motivates design-for-test


Test ExampleSA1 SA0

• A3

• A2

• A1

• A0

• n1• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2

• A1

• A0

• n1• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1

• A0

• n1• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0

• n1• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0 {0110} {0111}• n1• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0 {0110} {0111}• n1 {1110} {0110}• n2• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0 {0110} {0111}• n1 {1110} {0110}• n2 {0110} {0100}• n3• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0 {0110} {0111}• n1 {1110} {0110}• n2 {0110} {0100}• n3 {0101} {0110}• Y

A3A2

A1

A0

Y

n1

n2 n3


Test ExampleSA1 SA0

• A3 {0110} {1110}• A2 {1010} {1110}• A1 {0100} {0110}• A0 {0110} {0111}• n1 {1110} {0110}• n2 {0110} {0100}• n3 {0101} {0110}• Y {0110} {1110}• Minimum set: {0100, 0101, 0110, 0111, 1010,

1110}

A3A2

A1

A0

Y

n1

n2 n3

Random-Pattern Generation

• Flow chart for method

• Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest


Boolean Difference Symbolic Method (Sellers et al.)

g = G (X1, X2, …, Xn) for the fault sitefj = Fj (g, X1, X2, …, Xn)

1 j mXi = 0 or 1 for 1 i n


≤≤ ≤

≤

Boolean Difference (Sellers, Hsiao, Bearnson)

• Shannon’s Expansion Theorem:F (X1, X2, …, Xn) = X2 F (X1, 1, …, Xn) + X2 F (X1, 0, …, Xn)

• Boolean Difference (partial derivative):Fjg

• Fault Detection Requirements for g s-a-0 output fj as:G (X1, X2, …, Xn) = 1Fjg


= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn)

= Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1

••

∂∂ ⊕

∂∂ ⊕

۱۱week Fauult-Tolerant digital System Design ۳۷

۱۱week Fauult-Tolerant digital System Design ۳۸

For xi s-a-0

۱۱week Fauult-Tolerant digital System Design ۳۹

xi s-a-0 xi s-a-1

۱۱week Fauult-Tolerant digital System Design ٤۰

Example 1: x1 s-a-0, T(x1 / 0 ) = ?

۱۱week Fauult-Tolerant digital System Design ٤۱

۱۱week Fauult-Tolerant digital System Design ٤۲

Example 2: h s-a-0, h s-a-1, T(h / 0) = ?, T(h / 1) =? x

۱۱week Fauult-Tolerant digital System Design ٤۳

۱۱week Fauult-Tolerant digital System Design ٤٤

۱۱week Fauult-Tolerant digital System Design ٤٥

Proof (3)

۱۱week Fauult-Tolerant digital System Design ٤٦

i i

۱۱week Fauult-Tolerant digital System Design ٤۷

۱۱week Fauult-Tolerant digital System Design ٤۸

T(G/0) = ?

۱۱week Fauult-Tolerant digital System Design ٤۹

2 2 2 2 25

56

6

۱۱week Fauult-Tolerant digital System Design ٥۰

۱۱week Fauult-Tolerant digital System Design ٥۱

x x

,

Path Sensitization Method Circuit Example

1 Fault Sensitization2 Fault Propagation3 Line Justification



Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i


10

D

D1

1

1DD

D

1≠ D


Try simultaneous paths f – h – k – L andg – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears


1

DD D

DD

1

1

1


Final try: path g – i – j – k – L – test found!


0

D D D

1 DD

1

0

1

Irredundant Hardware and Test Patterns

• Combinational ATPG can find redundant (unnecessary) hardware

• Fault Testa sa1, b sa0 A = 1a sa0, b sa1 A = 0

• Therefore, these faults are not redundantCopyright 2001, Agrawal & Bushnell VLSI Test: Lecture 10 56

Redundant Hardware and Simplification


Redundant Fault q sa1


0

Multiple Fault Masking• f sa0 tested when fault q sa1 not there


Multiple Fault MaskingPart II

• f sa0 masked when fault q sa1 also present


Intentional Redundant Implicant BC

• Eliminates hazards in circuit output


Algorithm 7.1Redundancy Removal

Repeat until there are no more redundant faults:{

Use ATPG to find all redundant faults;Remove all redundant faults with non-

overlapping fault cone areas;}


History of Algorithm Speedups


Algorithm

D-ALGPODEMFANTOPSSOCRATESWaicukauski et al.ESTTRANRecursive learningTafertshofer et al.

Est. speedup over D-ALG(normalized to D-ALG time)17232921574 ATPG System2189 ATPG System8765 ATPG System3005 ATPG System48525057

Year

1966198119831987198819901991199319951997

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