lecture xilinx iseand fpgas

8/2/2019 Lecture Xilinx Iseand FPGAs

1/57

XilinxISE

Xilinxtutorial

Examples

UCF

Synthesis,Mapping

Translation

ProgrammingFile

Downloading

SynthesisOptions

RTLSchematic


2/57

OriginofFPGAs


3/57

Typesof

Programmable

Logic

Devices


4/57


5/57


6/57


7/57

TypesofASICs


8/57

TypesofChanneledGateArrays


9/57

ExamplesofStructuredASICTiles


10/57

GenericStructuredASICs


11/57


12/57

ASICsEnd


13/57


14/57

KeyElements

Forming

Simple

ProgrammingLogicBlocks


15/57

ConfiguringaLUT


16/57

TopDown

View

of

FPGA

Architecture


17/57

FPGAASICHybrid


18/57

FPGAandFPAAVendors


19/57

FulltimeEDAVendors


20/57

GeneralTypesofFPGAs

Anti

fuse

based

FPGAs SRAMbasedFPGAs


21/57

AntifuseBasedFPGAs

In

the

case

of

antifuse

based

FPGAs,

the

antifuse

cells

canbevisualizedasscatteredacrossthefaceofthedeviceatstrategiclocations.

Thedeviceisplacedinaspecialdeviceprogrammer,the

configuration

(bit)

file

is

uploaded

into

the

device

programmerfromthehostcomputer,andthedeviceprogrammerusesthisfiletoguideitinapplying

pulsesof

relatively

high

voltage

and

current

to

selectedpinstogroweachantifuseinturn.


22/57

Once

all

of

the

fuses

have

been

grown,

the

FPGA

is removedfromthedeviceprogrammerandattachedto

acircuitboard.

Antifuse

based

devices

are,

of

course,

one

time

programmable(OTP)


23/57

SRAMbasedFPGAs

Remember

that

these

devices

are

volatile,

which

meansthattheyhavetobeprogrammedinsystem(onthecircuitboard),andtheyalwaysneedtobereprogrammedwhenpowerisfirstappliedtothe

system. Fromtheoutsideworld,wecanvisualizeallofthe

SRAMconfigurationcellsascomprisingasingle

(long)shift

register.


24/57

VisualizingSRAM

Based

FPGAs

as

alongchainofshiftregisters


25/57


26/57

FPGAConfigurationModes


27/57

SerialLoadWithFPGAasMaster


28/57

DaisyChainingFPGAs


29/57

ParallelLoadwithFPGAasMaster


30/57

JTAGBoundaryScan


31/57

JTAGFPGAs Likemanyothermoderndevices,todaysFPGAsare

equippedwithaJTAGport.StandingfortheJointTestActionGroupandofficiallyknowntoengineersbyitsIEEE1149.1specificationdesignator

JTAGwas

originally

designed

to

implement

the

boundaryscantechniquefortestingcircuit

boardsandICs.


32/57

JTAGContinued FPGAhasanumberofpinsthatareusedasaJTAG

port.

OneofthesepinsisusedtoinputJTAGdata,andanotherisusedtooutputthatdata.

EachoftheFPGAsremainingI/OpinshasanassociatedJTAGregister(aflipflop),wheretheseregistersaredaisychained

together


33/57

JTAG


34/57

XilinxLogicCell


35/57

Slice


36/57

CLBsandLABs


37/57

EmbeddedRAMs


38/57

EmbeddedMACs


39/57

EmbeddedMAC


40/57

EmbeddedMACs

Similarly,

some

FPGAs

offer

dedicated

adder

blocks.

OneoperationthatisverycommoninDSPtypeapplicationsiscalledamultiplyandaccumulate


41/57

Logic

Partitioning

in

terms

of

Speed Picosecondandnanosecondlogic:

Thishas

to

run

insanely

fast,

which

mandates

that

it

be

implemented

inhardware(intheFPGAfabric). Microsecondlogic: Thisisreasonablyfastandcanbeimplementedeitherinhardwareor

software(thistypeoflogiciswhereyouspendthebulkofyour time

decidingwhich

way

to

go).

Millisecondlogic: Thisisthelogicusedtoimplementinterfacessuchasreadingswitch

positionsandflashinglightemittingdiodes(LEDs).Itsapainslowingthehardwaredowntoimplementthissortoffunction(usinghuge

countersto

generate

delays,

for

example).

Thus,itsoftenbettertoimplementthesetasksasmicroprocessor

code(becauseprocessorsgiveyoulousyspeedcomparedtodedicated

hardwarebutfantasticcomplexity).


42/57

Untilrecentlytheseslowspeedlogicappearedonseparate

devices

(discrete

chips

)on

PCBs


43/57

HardMicroprocessorCore

HardmicroprocessorcoresAhardmicroprocessorcoreisimplementedasadedicated,predefinedblock.


44/57

HardIParrangementasStripe


45/57

Chips

Embedded

in

the

main

FPGA

Fabric


46/57

SoftProcessorCores Asopposedtoembeddingamicroprocessorphysically

intothe

fabric

of

the

chip,

it

is

possible

to

configure

a

groupofprogrammable logicblockstoactasamicroprocessor.

Theseare

typically

called

soft

cores,

but

they

may

be

morepreciselycategorizedaseithersoft orfirmdependingonthewayinwhichthemicroprocessors

functionality

is

mapped

onto

the

logic

blocks


47/57

AdvantagesofSoftCores Softcoresaresimpler(moreprimitive)andslower

thantheir

hard

core

counterparts.

However,theyhavetheadvantage thatyouonlyneedtoimplementacoreifyouneeditandalsothatyou

caninstantiate

as

many

cores

as

you

require

until

you

runoutofresourcesintheformofprogrammablelogicblocks.


48/57

ClockTrees


49/57

NeedforClockTrees AllofthesynchronouselementsinsideanFPGAfor

example,the

registers

configured

to

act

as

flip

flops

insidetheprogrammablelogicblocksneedtobedrivenbyaclocksignal.

Suchaclock

signal

typically

originates

in

the

outside

world,comesintotheFPGAviaaspecialclockinputpin,andisthenroutedthroughthedeviceand

connected

to

the

appropriate

registers.


50/57

ClockTreesFunctionality Thisiscalledaclocktree becausethemainclocksignalbranchesagainand

again(theflipflopscanbeconsider,tobetheleaves ontheendofthebranches).

Thisstructureisusedtoensurethatalloftheflipflopsseetheirversionsoftheclock

signalasclosetogetheraspossible. Iftheclockweredistributedasasinglelongtrackdrivingall oftheflipflops

oneafter

another,thentheflipflopclosesttotheclockpinwouldseetheclocksignalmuchsoonerthantheoneattheendofthechain.Thisisreferredtoasskew,anditcancauseallsortsofproblems(evenwhenusingaclocktree,therewillbeacertainamountofskewbetweentheregistersonabranchandalsobetweenbranches).

Theclock

tree

is

implemented

using

special

tracks

and

is

separate

from

the

generalpurposeprogrammableinterconnect. Inreality,multipleclockpinsareavailable(unusedclockpins canbe

employedasgeneralpurposeI/Opins),andtherearemultipleclockdomains(clocktrees)insidethedevice.


51/57

ClockManagers Insteadofconfiguringaclockpintoconnectdirectly

intoan

internal

clock

tree,

that

pin

can

be

used

to

driveaspecialhardwiredfunction(block)calledaclockmanagerthatgeneratesanumberofdaughter

clocks


52/57

JittersinClock


53/57

ClockManagersasJitterRemovers


54/57

Clock

Managers

as

Frequency

Synthesizers


55/57

GPI/Os Theproblemisthatthereisawidevarietyofsuch

standards,and

it

would

be

painful

to

have

to

create

specialFPGAstoaccommodateeachvariation.

Forthisreason,anFPGAsgeneralpurposeI/Ocanbe

configuredto

accept

and

generate

signals

conforming

towhicheverstandardisrequired.

ThesegeneralpurposeI/Osignalswillbesplitintoa

numberof

bankswell

assume

eight

such

banks

numberedfrom0to7


56/57


57/57

SupplyVoltagesversusTechnology

lecture xilinx iseand fpgas

Documents