lecture1 ee720 intro
DESCRIPTION
ECEN720: High-Speed Links Circuits and Systems Spring 2013Lecture 1: IntroductionTRANSCRIPT
Sam Palermo Analog & Mixed-Signal Center
Texas A&M University
ECEN720: High-Speed Links Circuits and Systems
Spring 2013
Lecture 1: Introduction
Class Topics
• System and design issues relevant to high-speed electrical (and optical) signaling
• Channel properties • Modeling, measurements, communication techniques
• High-Speed link circuits • Drivers, receivers, equalizers, timing systems
• Link system design • Modeling and performance metrics
• Link system examples
2
Administrative
• Instructor: • Sam Palermo • 315E WERC Bldg., 845-4114, [email protected] • Office hours: MW 2:00pm-3:30pm
• Lectures: MW 4:10pm-5:25pm, ZACH 223A
• Lab: M 5:45pm-7:35pm, ZACH 203 • Lab begins third week
• Class web page • http://www.ece.tamu.edu/~spalermo/ecen720.html
3
Class Material
• Textbook: Class Notes and Technical Papers
• Key References • Digital Systems Engineering, W. Dally and J. Poulton, Cambridge
University Press, 1998. • Advanced Signal Integrity for High-Speed Digital Designs, S. H.
Hall and H. L. Heck, John Wiley & Sons, 2009. • High-Speed Digital Design: A Handbook of Black Magic, H.
Johnson & M. Graham, Prentice Hall, 1993. • Design of Integrated Circuits for Optical Communications, B.
Razavi, McGraw-Hill, 2003.
• Class notes • Will hand out hard copies in class
4
Grading
• Exams (50%) • Two midterm exams (25% each)
• Homework & Labs (25%) • Labs (Prelab + Report) and homeworks weighted equally • Collaboration is allowed, but independent simulations and write-ups • Need to setup CADENCE simulation environment • Due at beginning of class • No late homework will be graded
• Final Project (25%) • Groups of 1-2 students • Report and PowerPoint presentation required
5
Prerequisites
• This is a circuits AND systems class • Circuits
• ECEN474 or approval of instructor • Basic knowledge of CMOS gates, flops, etc… • Circuit simulation experience (HSPICE, Spectre)
• Systems • Basic knowledge of s- and z-transforms • Basic digital communication knowledge • MATLAB experience
6
Simulation Tools
• Matlab
• Stateye (Statistical BER link analysis)
• Cadence
• 90nm CMOS device models • Can use other technology models if they are a
90nm or more advanced CMOS node
• Other tools, schematic, layout, etc… are optional
7
Desktop Computer I/O Architecture
• Many high-speed I/O interfaces
• Key bandwidth bottleneck points are memory (FSB) and graphics interfaces (PCIe)
• Near-term architectures ̶ Integrated memory controller with
serial I/O (>5Gb/s) to memory ̶ Increasing PCIe from 2.5Gb/s (Gen1)
to 8Gb/s (Gen3)
• Other serial I/O systems ̶ Multi-processor systems ̶ Routers
8
Serial Link Applications • Processor-to-memory
• RDRAM (1.6Gbps), XDR DRAM (7.2Gbps), XDR2 DRAM (12.8Gbps)
• Processor-to-peripheral • PCIe (2.5, 5, 8Gbps), Infiniband (10Gbps), USB3 (4.8Gbps)
• Processor-to-processor • Intel QPI (6.4Gbps), AMD Hypertransport (6.4Gbps)
• Storage • SATA (6Gbps), Fibre Channel (20Gbps)
• Networks • LAN: Ethernet (1, 10Gbps) • WAN: SONET (2.5, 10, 40Gbps) • Backplane Routers: (2.5 – 12.5Gbps)
9
Chip-to-Chip Signaling Trends Decade Speeds Transceiver Features 1980’s >10Mb/s Inverter out, inverter in
1990’s >100Mb/s Termination Source-synchronous clk.
2000’s >1 Gb/s Pt-to-pt serial streams Pre-emphasis equalization
Future >10 Gb/s Adaptive Equalization, Advanced low power clk. Alternate channel materials
Lumped capacitance
… Transmission line
Lossy transmission line
h(t) Σ
Channel noise Sampler Slicer RX
Equalizer Transmit
Filter
CDR
Slide Courtesy of Frank O’Mahony & Brian Casper, Intel 10
Increasing I/O Bandwidth Demand
Single ⇒ Multi ⇒ Many-Core µProcessors
Tera-scale many-core processors will aggressively drive aggregate I/O rates
*2006 International Technology Roadmap for Semiconductors
ITRS Projections* Intel Teraflop Research Chip
• 80 processor cores • On-die mesh
interconnect network w/ >2Tb/s aggregate bandwidth
• 100 million transistors • 275mm2
S. Vangal et al, “An 80-Tile Sub-100W TeraFLOPS Processor in 65nm CMOS," JSSC, 2008.
11
High-Speed Electrical Link System
TX
ChannelTX
data
Seria
lizer
PLLref clk
RX
Des
eria
lizer
RXdata
TX clk RX clk
D[n+1]D[n] D[n+2] D[n+3]TX data
TX clk
RX clk
CDR
12
13
Electrical Backplane Channel
Line card trace(dispersion)
Backplane via(major reflections)
Backplane trace(dispersion)
Backplane connector(crosstalk)
Package via(reflections)
On-chip termination(reflections)
Chip package(crosstalk)
Line card via(reflections)
• Frequency dependent loss ̶ Dispersion & reflections
• Co-channel interference ̶ Far-end (FEXT) & near-end (NEXT) crosstalk
14
Channel Performance Impact
15
Channel Performance Impact
A 10Gb/s 5-tap DFE / 4-Tap FFE Transceiver in 90nm CMOS Technology
Mounir Meghelli, Sergey Rylov, John Bulzacchelli, Woogeun Rhee, Alexander Rylyakov, Herschel Ainspan, Ben Parker, Michael Beakes, Aichin Chung, Troy Beukema, Petar Pepeljugoski, Lei Shan, Young Kwark, Sudhir Gowda and Dan Friedman
IBM T. J. Watson Research Center, Yorktown Heights, NY
Backplane Link Example
16
Transmission Channel Impairments
The Channel Tx IC
Pkg Line card trace
Edge connector
Backplane 16” trace
Edge connector
Line card trace
Rx IC
Pkg
Edge connector
Packaged SerDes
Line card trace
Backplane trace
Via stub
-100ps 100ps-50ps 0ps 50ps-500mV
500mV
-400mV
-300mV
-200mV
-100mV
-0.0mV
100mV
200mV
300mV
400mV
500mVEye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk
Time
Sign
al A
mpl
itude
Vpd
DATA = RAND Tx 600mVpd AGC Gain -5.48dBXTALK = NONE AGC 5.0GHz 0.00dBPKG=0/0 TERM = 5050/5050 IC = 3/3
HSSCDR = 2.3.2-pre2 IBM ConfidentialDate = Sat 01/21/2006 12:00 PMPLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00usFFE = [1.000, 0.000]
-100ps 100ps-50ps 0ps 50ps-500mV
500mV
-400mV
-300mV
-200mV
-100mV
-0.0mV
100mV
200mV
300mV
400mV
500mVEye FFE1 10.0Gb/s [OPEN,1e-8] No Xtalk
Time
Sign
al A
mpl
itude
Vpd
DATA = RAND Tx 600mVpd AGC Gain -6.02dBXTALK = NONE AGC 5.0GHz 0.00dBPKG=0/0 TERM = 5050/5050 IC = 3/3
HSSCDR = 2.3.2-pre2 IBM ConfidentialDate = Sat 01/21/2006 12:01 PMPLL=0F1V0S0,C16,N32,O1,L80 FREQ=0.00ppm/0.00usFFE = [1.000, 0.000]
INPUT
OUTPUT
0Hz 10GHz2.0GHz 4.0GHz 6.0GHz 8.0GHz-90
10
-80
-70
-60
-50
-40
-30
-20
-10
0
10[OPEN,1e-8] Channel Response
Frequency
|SDD
21|
-40
60
-30
-20
-10
0
10
20
30
40
50
60
|S11
|,|S2
2|
S21
-24.6dB @ 5GHz
17 [Meghelli (IBM) ISSCC 2006]
10Gb/s SerDes Main Features
Tx with 1 baud-spaced 4-tap FFE
Rx with 5-tap adaptive DFE and digital clock recovery
LC-VCO based PLL for low noise clock generation
90nm CMOS technology
18 [Meghelli (IBM) ISSCC 2006]
Transmitter Architecture
“A Low Power 10Gb/s Serial Link Transmitter in 90-nm CMOS” A. Rylyakov et al., CSICS 2005
L
L L
L
L
L
L
L
L
1x 4x 2x 1x
1/4 1 1/2 1/4 IDACs
& Bias
Control
sgn-1 sgn0 sgn1 sgn2
50Ω
Out-P
Out-N
4:2 MUX
2
2
2
2 1
D0
D1
D2
D3
VDDA=1.2V VDD=1.0V
VDDIO=1.0V
VDDA=1.2V
1
1
1
C2 (5GHz) From on-chip PLL
2
(2.5
Gb/
s)
(10Gb/s)
(5Gb/s)
ESD
Key Features: - Half-rate CML design - 4-tap FFE - Tap polarity control - ESD protection - 70mW (24mA main tap, no FFE)
FFE Taps Full Scale DAC bits
Pre-cursor 25% 4
Cursor 100% 6
1st Post-cursor 50% 5
2nd Post-cursor 25% 4
19 [Meghelli (IBM) ISSCC 2006]
20
Tx Output Eye Diagram @ 10Gb/s
No FFE, 24mA on main tap
Simulated Measured
FFE 4=[0, 85%, -15%, 0, 0]
1 0 0 p s0 p s 0 p s 5 0 p s
e F F E 4 1 0 .0 G b /s [O P E N ,1 e -8 ] N o X ta lk
T im e
8 0 0 m V p dA G C G a in -6 .0 2 d B E A G C 5 .0 G H z 0 .0 0 d B
R M = 5 0 5 0 /5 0 5 0 IC = 3 /0
2 .4 IB M C o n f id e n tia l 3 2E Q O F S = 0 .0 0 p p m /0 .0 0 u sD /E O F S T 1 0 .8 6 3 , -0 .1 3 7 , 0 .0 0 0 ]
100 ps50ps 0ps 50p s
ye F F E 1 10 .0G b /s [O P E N ,1 e -8 ] N o X ta lk
T im e
Dx 600m V pdA G C G a in -6 .02d B N E A G C 5 .0G H z 0 .00 dB
R M = 5 050 /5050 IC = 3 /0 % U I
2 .4 IB M C on fiden tia l N 32R E Q O F S = 0 .00ppm /0 .00 us 0 .000 ]
[Meghelli (IBM) ISSCC 2006]
Receiver Architecture
Key Features: - Half-rate design - 5-tap continuously adaptive DFE - Variable gain amplifier - Digital CDR - ESD protection (HBM & CDM) - 130mW (with DFE and CDR logic)
T-Coil Compensation Network
50Ω
In_P In_N
(10G
b/s)
ESD
VGA
Vcm
PI PI
Phase rotator
2:8 DMUX
8:16 DMUX
CDR logic
I-Clock control
Q-Clock control I Q
DFE logic
Tap weights
C2-I C2-Q
Edge
Data Amp
From on-chip PLL (5GHz)
CML CMOS logic VDDA=1.2V
8
2
D0
D1
D2
D3
2
2
2
(2.5
Gb/
s)
1
1
1
1 VDDIO=1V
DFE Block
Phase detector
VDD=1.0V
Data Amp Edge Clock
21 [Meghelli (IBM) ISSCC 2006]
DFE Approach
Key Features: - Half-rate DFE with H1 speculation and dynamic H2-H5 feedback allows 2UI for settling - DFE algorithm maximizes vertical eye opening at the data slicing instant - Offset adjustment at all the slicer inputs
Received eye ISI
Σ L L L
Σ L L L
Tap-feedback and weighting H1-5
Tap weights Data
I
I
I
I I I I
I I I
Σ I
Offset
Deven
Dodd
Amplitude
On-chip DFE Logic
(+H1)
(-H1)
(+H1)
(-H1)
DFE Taps Resolution
H1 6 bits
H2 5 bits
H3, H4, H5 4 bits
22 [Meghelli (IBM) ISSCC 2006]
CDR Loop
Data Z-1
Z-1
DMUX XORs
D
E
D
E
Early
Late
Digital Filter
I Rotator Control
Q Rotator Control
PI D/A
PI D/A C2-I
C2-Q
From
on-
chip
PLL
Data Clock
Edge Clock
Key Features: - Fully digital loop - Can handle up to +/- 4000ppm frequency offset - Independent I,Q control
Jitter Tolerance
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09
Modulation Frequency
Sine
Jitt
er (U
I pp)
Receiver Jitter tolerance curve ( BER<1e-9)
Tracking bandwidth ~9MHz
23 [Meghelli (IBM) ISSCC 2006]
24
Chip-to-Chip Link Experiments
Trace Length
5GHz losses (Tx module + board trace + Rx module)
Number of vias 3.8mm via stub / 1.8mm via stub / 1.8mm via through
10” (#1) 12dB 2 / 0 / 0 10” (#2) 10dB 0 / 2 / 0 15” 25dB 4 / 2 / 0 20” 15dB 0 / 0 / 2
Module Module
SerDes1 SerDes2
Board
Trace Via stub
SerDes1
SerDes2
Trace
[Meghelli (IBM) ISSCC 2006]
25
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
10" (#1) 10" (#2) 15" 20" Link
Hor
izon
tal E
ye O
peni
ng (1
e-9
BER
)
DFE+FFE DFE FFE
Chip-to-Chip Measurement Results Trace Length
5GHz losses
(Tx module + board trace + Rx module)
Number of vias
3.8mm via stub / 1.8mm via stub / 1.8mm via through
10” (#1) 12dB 2 / 0 / 0
10” (#2) 10dB 0 / 2 / 0
15” 25dB 4 / 2 / 0
20” 15dB 0 / 0 / 2
DFE
+ F
FE
DFE
+ F
FE
DFE
+ F
FE
DFE
+ F
FE
DFE
ON
LY
DFE
ON
LY
FFE
ON
LY
FFE
ON
LY
Horizontal eye opening of the equalized eye at the receiver slicer input
[Meghelli (IBM) ISSCC 2006]
26
Preliminary Schedule
• Dates may change with reasonable notice
Next Time
• Channels • Components
• Chip packages, PCBs, Wires, Connectors
• Modeling • Wires, Transmission Lines
27