lecture21 timing

8/12/2019 Lecture21 Timing

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EE241 - Spring 2004Advanced Digital Integrated Circuits

Borivoje Nikoli

Lecture 21

Timing

2

Announcements

Homework #4 due next Tuesday


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Overview

Synchronization Approaches

Synchronous Systems

Timing methodologies

Latching elements

Clock distribution

Clock generation

Asynchronous Systems

27

References

Chapter 11 Clocked storage elements, by H. Partovi

High-speed CMOS design styles, Bernstein, et al,

Kluwer 1998.

Unger/Tan IEEE Trans. Comp. 10/86

Harris/Horowitz JSSC 11/97

Messerschmitt JSAC 10/90

Stojanovi/Oklobdija JSSC 4/99


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Issues in Timing

D. Messerschmitt, Oct 1990

Boolean signal - stream of 0s and 1s, generated by saturating

circuits and bistable memory elements

but

finite rise and fall times inter-symbol interference

metastability leads to non-deterministic behavior

signal transitions are crucial

typically defined with respect to slicer/sampler

associated clock with uniformly spaced transitions

0 1 0 0 0 0 0 01 1 1 1 1 1 1 1 1

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Boolean signalBoolean signal

Isochronousf + f = constant

Anisochronousf + f constant

SingleSingle

Clock signal :

f + f average frequency

d/dt instantaneous frequency deviation

Issues in Timing

equal not equal


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Issues in Timing

Synchronousf + f identical(t) = 0 (or known)

Asynchronous

Mesochronous(t) variable(but bounded)

PlesiochronousAverage Frequencyalmost the same

HeterochronousNominallyDifferent freq

together not together

near

middle different

Two Boolean SignalsTwo Boolean Signals

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Some Definitions

Signals that can only transition at predetermined times with

respect to a signal clock are called

{syn,meso,plesio}chronous

An asynchronous signal can transition at any arbitrary

time.


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Some Definitions (contd)

Synchronous Signal: exactly the same frequency as local clock, andfixed phase offset to that clock.

Mesochronous Signal: exactly the same frequency as local clock,

but unknown phase offset.

Plesiochronous Signal: frequency nominally the same as local clock,

but slightly different

Mesochronous and plesiochronous concepts are very useful for the

design of systems with long interconnections, and/or multipleclock domains

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Mesochronous Interconnect

clock

synchronous

island

Data synchronous

island

Phase Generator

Select

Phase

Detect

Data

R1 R2

Clock

Local Synchronization

samples in certaintyperiod of signal

(local)


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Mesochronous Communication

R1Interconnect

R2

ClkA

D2Block A

Delay Block B

ClkB

D4

Control

D1

D3

VariableDelay Line

Timing Recovery

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Plesiochronous Communication

Originating Receiving

FIFO

TimingClock C1

Clock C 2

Module Module

Recovery

C3

Does only marginally deal with fast variations in data delay


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Anisochronous Interconnect

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Synchronous Pipelined Datapath

In

tpd,reg tpd1

D

R1

Q

CLK

LogicBlock #1

tpd2

D

R2

QLogic

Block #2

tpd3

D

R3

Q D

R4

QLogic

Block #3


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Latch versus Flip-Flop

Lat ch

st or es dat a when

cl ock i s l ow (hi gh)

D

Cl k

Q D

Cl k

Q

Flip-Flop (or Register)

stores data when

clock rises (falls)

Cl k Cl k

D D

Q Q

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Latch Parameters

D

Cl k

Q

D

Q

Cl k

TClk-Q

TH

PWmTSU

TD-Q

Delays can be different for rising and falling data transitions

Unger and Tan

Trans. on Comp.

10/86


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Flip-Flop (Register) Parameters

D

Cl k

Q

D

Q

Cl k

TClk-Q

TH

PWm

TSU

Delays can be different for rising and falling data transitions

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Example Clock System

Courtesy of IEEE Press, New York. 2000


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Clock Nonidealities

Clock skew

Spatial variation in temporally equivalent clock edges; deterministic + random,tSK

Clock jitter

Temporal variations in consecutive edges of the clock signal; modulation +

random noise

Cycle-to-cycle (short-term) tJS

Long term tJL

Variation of the pulse width

for level sensitive clocking

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Clock Skew and Jitter

Both skew and jitter affect the effective cycle time

Only skew affects the race margin

Cl k

Cl k

tSK

tJS


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Clock Uncertainties

2

4

3

Power Supply

Interconnect

5 Temperature

6 Capacitive Load

7 Coupling to Adjacent Lines

1 Clock Generation

Devices

Sources of clock uncertainty

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Clock Skew

# of registers

Clk delayInsertion delay

Max Clk skew

Earliest occurrenceof Clk edgeNominal /2

Latest occurrenceof Clk edge

Nominal + /2


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Positive and Negative Skew

R1In

(a) Positive skew

CombinationalLogic

D Q

tCLK1CLK

delay

tCLK2

R2

D Q Combinational

Logic

tCLK3

R3

D Q

delay

R1In

(b) Negative skew

CombinationalLogic

D Q

tCLK1

delay

tCLK2

R2

D Q Combinational

Logic

tCLK3

R3

D Q

delay CLK

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Positive Skew

CLK1

CLK2

TCLK

TCLK+

+th

2

1

4

3

Launching edge arrives before the receiving edge


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Negative Skew

CLK1

CLK2

TCLK

TCLK+

2

1

4

3

Receiving edge arrives before the launching edge

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onges og c a n

Edge-Triggered Systems

Cl k

P

TSU+ Tsk+ TJS

TClk-QTLM

Latest point

of launchingEarliest arrival

of next cycle

Unger and Tan

Trans. on Comp.

10/86


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oc ons ra n s n

Edge-Triggered Systems

JSskSULMQMclk TTTTTP ++++

LMQMclkSUJSsk TTTTTP ++

If launching edge is late and receiving edge is early, the data will not be too late if:

Minimum cycle time is determined by the maximum delays through the logic

Double-sided definitions of setup and jitter

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Shortest Path

Cl kTClk-Q TLm

Earliest point

of launching

Data must not arrive

before this time

Cl kTH

Nominal

clock edge


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oc ons ra n s

in Edge-Triggered Systems

Minimum logic delay

If launching edge is early and receiving edge is late:

HskLmQmclk TTTT ++

QmclkHskLm TTTT +

Jitter does not really play as this concerns the same clock edge

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oc ons ra n s

in Edge-Triggered Systems

Courtesy of IEEE Press, New York. 2000


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Flip-Flop Based Timing

Flip

-flop

Logic

= 1 = 0

Flip-flopdelay

Skew

Logic delay

TSUTClk-Q

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Flip-Flops and Dynamic Logic

= 1 = 0

Logic delay

TSUTClk-Q

= 1 = 0

Logic delay

TSUTClk-Q

PrechargeEvaluateEvaluatePrecharge

Flip-flops are used only with static logic

No way to hide the precharge overhead

lecture21 timing

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