linear digital ics

7/29/2019 Linear Digital ICs

1/22

EE2603-10 1

10. Linear Digital ICs(17.1 17.4)

! Comparator IC! DAC , ADC

! 555 timer IC


2/22

EE2603-10 2

Comparator IC Comparator IC = Two inputs of the IC are compared to each other as below:

WhenV+ismorepositivethanV-OutputVowillgohighto +VCC( = V-ismorenegativethanV+)

WhenV-ismorepositivethanV+OutputVowillgolowtoVCC( = V+ismorenegativethanV-)

+VCC

VO

-VCC

V-

V+

+10

VO=+10V

-10

0

+0.1

+10

VO=-10V

-10

0

+0.1 +10

VO=+10V

-10

+0.1

+0.5

Output is digital either +10 or -10


3/22

EE2603-10 3

WhenV+ismorepositivethan0OutputVowillgohighto +VCCWhen

V+

is

more

negative

than

0Output

Vowill

go

low

to

VCC

WhenV-ismorepositivethan0OutputVowillgolowto-VCCWhenV-ismorenegativethan0 OutputVowillgohighto+VCC

+10

VO

-10

+1

-1

+10

-10

When Reference is 0V(Zero-crossing Comparator)Reference

Input

+10

VO

-10

+10

-10

+1

-1

Reference

InputOutput is digital either +10 or -10

Output is digital either +10 or -10


4/22

EE2603-10 4

+10

VO

-10

+5

-5

-4

R1

R2

WhenV-ismorepositivethanVref-4OutputVowillgolowto-VCCWhenV-ismorenegativethanVref-4OutputVowillgohighto+VCC

When Reference is Non-0V

(Reference-crossing Comparator)

+10-5

-4

0

+5

-10

Output isdigital


5/22

EE2603-10 5

Comparator IC

Some improvements such as faster switching of output levels, preventingoscillation while crossing reference, and its output capable of driving a

variety of loads are incorporated in IC Comparators such as 311-ICWhen Strobed (pin 6= high) theoutput will follow the input

When Pause (pin 6=low) the outputwill always be high regardless of the

input

Open-Collector Outputtofacilitate any output voltage

level when the output is high

Outputwillgolowtoref= -VCC or 0according to connection of pin 1

Outputvoltage polarity is the

reverse of input voltage polarity

Outputvoltage polarity is the

same as input voltage polarity

+ VCC

- VCC

output refere

nce 1

311 - IC

4

2 non-inv input

8

3 inv input

7output

5 Balance

6 Balance/strobe


6/22

EE2603-10 6

1

311 - IC

4

2

8

3

7

6 strobe

+10

-10

When Strobed (pin 6= high)the output will follow the input

Outputvoltage polarity is thesame as input voltage polarity

Reference

Input+1-1

+10

0

Outputwillgolowtoref = 0

output voltage level is +10when the output is high

Example: Sketch the output waveform for the following 311 ICComparator Circuit


7/22

EE2603-10 7

1

311 - IC

4

2

8

37

+10

-10-10

Low=0

High=Strobe

6

When Strobed (pin 6= high)the output will follow the input

Outputvoltage polarity is thesame as input voltage polarity

Reference

Input+1-1

Outputwillgolowtoref = -10

output voltage level is +10when the output is high

Example: Sketch the output waveform for the following 311 ICComparator Circuit

+10

-10

Output


8/22

EE2603-10 8

339 IC

Four units of 311-IC wit common V+ (pin 3) and V- (pin 12) (output low ispin 12 voltage) Pull-up resistor needed at the output pins (1,2,13.14) to

obtain output high.

12

13

14

1

2

3

5

4

7

6

9

8

11

10

12

13

14

1

2

3

5

4

7

6

9

8

11

10

+10

+1

-1

+1

-1

+10

0

+10

0

output2

output1input1

input2

ref1

ref2


9/22

EE2603-10 9

Window Detector (Comparator with threshold inputs)

12

13

14

1

2

3

5

4

7

6

9

8

11

10

+10

+1

+10

+5

+10 +1

+5

0

+10

5.1kW

0

+9+1

+5

0

input Comp.1 Comp.2 OutputVin > +5V high low low

+5 > Vin > +1V high high highVin < +1V low high low

Vin

Output

Output high

Output low

Output low+1V+5V

Comp.1

Comp.2


10/22

EE2603-10 10

Digital to Analog Converters

D / A Converter

LSDigitLogic1 (5V)Logic1 (5V)

Logic1 (5V)

Logic0 (0V) MSDigitAnalogDecimal (7V)

NumberMost

Significant

Digit (MSD)Intermediate Digit

Least

Significant

Digit (LSD)Expressed

NumberDecimal Weight 23 = 8 22 = 4 21 = 2 20 = 1 8+4+2+1=15Binary Number 0 1 1 1 0111Decimal Number 0 4 2 1 0+4+2+1=7

0 1 1 1


11/22

EE2603-10 11

R-2R Ladder D/A Converter (DAC)R R R

2R 2R 2R 2R

D0LSD

D1 D2 D3MSD

Analog voltage(decimal) output

Digital voltage

(binary) input

2R

refN

1N1N

33

22

11

00

o V2

2D2D2D2D2DV

++++

=

D0 to D3 = 1 or 0N= N-bit binary word

Vref = analog voltage of digit 1

) ) ) )V1875.2V5

16

20212121V

3210

o =+++

=

D0=1 , D1=1 , D2 = 1 , D3=024 = 16 (4-bit binary word)

Vref = 5V

R R R

2R 2R 2R 2R

D0=5V

LSD MSD

Analog voltage(decimal) output

Digital voltage(binary) input

2R

D1=5V D2=5V D3=0V

Vo=2.1875V

0 1 1 1V3125.0

2

5

2

VresolutionvoltageahasDACbitN

4Nref

===


12/22

EE2603-10 12

R R R

2R 2R 2R 2RVref

D3

MSD

D2 D1 D0LSD

Digital switch(binary) input

I0I1I2I3

Vo

Vo=-(SIn)xRf

Rf

SIn

0 1 1 110 0 0

2R

DAC using R-2R Ladder Switched Network

R 2R Ladder

Reference CurrentVref

Current Switches

D3

, D2

, D1

, D0

Digital InputsIo

nN

efrn

2

1

R

VI

=

I0 to In = valuesN = N-bit binary word

Vref = reference voltage of DACn = binary digit

( )V9375.3k1mA9375.3RIV

mA9375.3025.2125.15625.0II

mA0IandmA25.24

mA9

2

1

k1

9I

mA125.18

mA9

2

1

k1

9Iand

mA5625.016

mA9

2

1

k1

9

I

foutout

out

3242

141

040

=

=

=

=+++==

===

=

==

=

==

=

1kW

9V

0

MSD

1 1 1

LSDDigital switch(binary) input

I0I1I2I3

Vo

Vo=-(SIn)xRf

Rf=1kWSIn0 1 1 1

1kW 1kW

2kW 2kW 2kW 2kW2kW

0 1 1 1


13/22

EE2603-10 13

Analog to Digital Converters

Integrator

Vref

Comparator

ControlLogic

Clock

DigitalCounter

Count

Reset

Digital Outputs

Count Over

AnalogInput

A / D Converter

LSDigitLogic1 (5V)Logic1 (5V)

Logic1 (5V)

Logic0 (0V)MSDigitAnalogDecimal (7V)


14/22

EE2603-10 14

Fixed time

Analog amplitude recordedduring fixed time

Recorded amplitudedecreases at fixed rate

Digital count increase withlarger decrease time

Dual-slope A/D Converter (ADC)

Integrator Vref

Comparator

ControlLogic

Clock

DigitalCounter

Count

Reset

Digital Outputs

Count Over

Analog

Input

00110111

1110

1110


15/22

EE2603-10 15

Ladder-network A/D Converter (ADC)

Comparator ControlLogic

Clock

DigitalCounter

Count

Reset

Digital Outputs

AnalogInput

Ladder

Network

StopCount

stopcount

startcount

Ladder (stair-case)

analog outputvoltageAnalogvoltage

1. When analog voltage > Ladder DAC output voltage, comparator opens theControl Logic to let the clock count the Digital Counter. Digital bits will increaseat the output of Digital Counter.2. When analog voltage = Ladder DAC output voltage, comparator closes theControl Logic to stop the clock of the Digital Counter. Digital bits will stopincreasing at the output of Digital Counter.3. If the clock is 1MHz, every step 1 will last 1s/Ladder step. For 12-bit LadderDAC, there will be 212=4096 steps. Then one full count will last 4096s. Or during1sec, there will be (1sec/4096x10-6sec) full counts = 244 full counts/sec


16/22

EE2603-10 16

555 timer IC

76

23

1

8

output

vcc

5k

5k

5k

R

S

2/3VCC

1/3VCC

Q

4Reset

DischargeThreshold

Trigger

Q5Modulate

RS-Flip-flopReset(R) or Set(S) with

logic high inputComparators

More positive applied to the positiveterminal (or more negative applied tothe negative terminal will make output

high

If pin 4 (Reset pin) is less than VCC,PNP BJT conducts and (R) becomeshigh to reset the Flip-flop

Output is zero if Reset

and high (VCC) if Set

Discharge pin 7 is zero ifReset and floats if Set

555 Timer


17/22

EE2603-10 17

76

23

1

8

output

vcc

5k

5k

5k

R

S

2/3VCC

1/3VCC

Q

4Reset

DischargeThreshold

Trigger

Q5

Modulate

1. If Threshold pin 6 is morethan 2/3 of VCC, R will be

high and output Q is Set tozero2. If Threshold pin 6 is lessthan 2/3 of VCC, there is nochange at output Q

3. If Trigger pin 2 is less than1/3 of VCC, S will be high and

output Q is Set to VCC4. If Trigger pin 2 is morethan 1/3 of VCC, there is nochange at output Q

5. If Modulate pin 5 is connectedto a dc source or to externalresistor, pin 2 and pin 6 levels willbe no longer 1/3 or 2/3 of VCC but

will be changed to any otherlevels.


18/22

EE2603-10 18

7

6

2

3

1

8

output

vcc

RA

C

RBThreshold

Trigger

Discharge

Astable Multivibrator (pulse generator)VCC

0

VCt

tc tdT

(2/3)VCC

(1/3)VCC

#2. But VC is never charged to VCC because when VC=just above (2/3)VCCpin 6 takes care and the output pin 3 will reset.#3. When pin 3 is reset(=low). Pin 7 will be zero. Then C is discharged to 0through RB=RDISCHA#4. But VC is never discharged to 0 because when VC= just below (1/3)VCC

pin 2 takes care and the output pin 3 will set. It repeats step #1 again.

#1. Let pin 3 is set (=high). Pin 7 will float. Then C is charged to VCCthrough RA+RB=RCHA


19/22

EE2603-10 19

VCC

0

VC

t

tc tdT

(2/3)VCC

(1/3)VCC

2lnCRt2ln2

1lnCR

te3

21

3

2eV

3

2VV

3

2

e)VV3

1(VV

3

2e)VV(VVCharing

CCC

cCR/tCR/tCCCCCC

CR/tCCCCCCCC

CR/tfinalinitialfinalC

CcCc

CcCc

===

+=

+=

+=+=

2lnCRt2ln2

1lnCR

te2

1eV

3

2V

3

1

e)0V3

2(0V3

1e)VV(VVDischaring

ddC

cCR/tCR/t

CCCC

CR/tCCCC


Ccdd

dddd

===

=

=

+=+=

Pulse frequency

C)RR2(

44.1

C)RR(

44.1

2lnC)RR(

1

T

1f

f

1ttT

ABdCdCdc

+

=

+

=

+

===+=


20/22

EE2603-10 20

Example:Find the pulse frequency of the 555 Timer IC Pulse Generator shown below

7

6

2

3

1

8

output

vcc

RA=7.5kW

C=0.1mF

RB=7.5kW

.Hz635101.0)105.7105.72(

44.1

C)RR2(

44.1

C)RR(

44.1

2lnC)RR(

1

T

1f

633

ABdC

dC

=

+

=

+

=

+

=

+

==


21/22

EE2603-10 21

7

6

2

3

1

8

output

vccR

CThreshold

Trigger

Discharge

Output

Monostable Multivibrator (timer)VCC

0

VC

ttc

(2/3)VCC

tc=Pulse width

#3. Now C is charged to VCC through R. Output pin 3 is then high#4. But VC is never charged to VCC because when VC= just above (2/3)VCCpin 6 takes care and the output pin 3 will reset. And it stays stable at

reset all the time until another external trigger.

#1. Let pin 2 is high and pin 3 is low. Pin 7 will zero. Output is also zero.Then C is also discharged to 0 through pin 7 #2. When pin 2 is triggered to zero for a short time, Pin 3 will be high.Then pin 7 is floating.


22/22

EE2603-10 22

7

6

2

3

1

8

output

vcc

R

C

Thigh

Thigh

Example: Find the pulse width of the 555 Timer IC Monostable circuit,if R = 7.5k and C = 0.1F.

( ) 3lnCRt3ln3

1lnCR

te13

2eVVV

3

2

e)V0(VV3

2e)VV(VVCharing

CcCR/tCR/t

CCCCCC

CR/tCCCCCC


cc

cc

===

=+=

+=+=

VCC

0

VC

t

tc

(2/3)VCC

Thigh = tc=Pulse width

ms825.01.1105.7101.03lnCRtwidthPulse36

C ====

linear digital ics

Documents