low leakage asic design style

8/13/2019 LOW LEAKAGE ASIC DESIGN STYLE

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Department of Electronics and Communication Engineering

CERTIFICATE

This is to certify that the technical seminar report work entitled Low-Leakage ASIC Design

Style carried out by Mr.R. Rajesh, Roll Number 10881A0488, submitted to the department of

Electronics and Communication Engineering, in partialfulfillment of the requirements for the award

of degree of Bachelor of Technology in Electronics and Communication Engineering during the year

2013

2014.

LOW-LEAKAGE ASIC DESIGN STYLE

Name & Signature of the Supervisor

Mr. S. Rajendar

Associate Professor

Name & Signature of the HOD

Dr. J. V. R. Ravindra

Head, ECE


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A

Technical Seminar Report

Submitted in the Partial Fulfillment of the

Requirements

for the Award of the Degree of

BACHELOR OF TECHNOLOGYIN

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted

By

R. RAJESH

10881A0488

Under the Guidance of

MR. S. RAJENDARAssociate Professor

Department of ECE

Department of Electronics and Communication Engineering

VARDHAMAN COLLEGE OF ENGINEERING(AUTONOMOUS)(Approved by AICTE, Affiliated to JNTUH&Accredited by NBA)

2013 - 14


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ACKNOWLEDGEMENTS

The satisfaction that accompanies the successful completion of the task would be put

incomplete without the mention of the people who made it possible, whose constant guidance and

encouragement crown all the efforts with success.

I express my heartfelt thanks to Mr. S. Rajendar, Associate Professor, technical seminar

supervisor, for his suggestions in selecting and carrying out the in-depth study of the topic. His

valuable guidance, encouragement and critical reviews really helped to shape this report to perfection.

I wish to express my deep sense of gratitude to Dr. J. V. R. Ravindra, Head of the

Department for his able guidance and useful suggestions, which helped me in completing the

technical seminar on time.

I also owe my special thanks to our Director Prof. L. V. N. Prasadfor his intense support,

encouragement and for having provided all the facilities and support.

Finally thanks to all my family members and friends for their continuous support and

enthusiastic help.

R. Rajesh

10881A0488


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ABSTRACT

In this topic, we describe a new low-leakage standard cell based application-specific integrated circuit

(ASIC) design methodology. This design is based on the use of modified standard cells, designed to

reduce leakage currents (by almost two orders of magnitude) in standby mode and also allow precise

estimation of leakage current. For each cell in a standard cell library, two low-leakage variants of the

cell are designed. If the inputs of a cell during the standby mode of operation are such that the output

has a high value, we minimize the leakage in the pull-down network, and similarly we minimize

leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants

of each standard cell are obtained. While technology mapping a circuit, we determine the particular

variant to utilize in each instance, so as to minimize leakage of the final mapped design. These are

used to compare placed-and-routed area, leakage and delays of this new methodology against Multi

threshold CMOS (MTCMOS) and a regular standard cell based design style.

To avoid these problems, A new methodology (which we call the HL methodology) has better

speed and area characteristics than MTCMOS implementations. The leakage current for HL designs

can be dramatically lower than the worst-case leakage of MTCMOS based designs, and two orders of

magnitude lower than the leakage of traditional standard cells. An ASIC design implemented in

MTCMOS would require the use of separate power and ground supplies for latches and combinational

logic, while our methodology does away with such a requirement.


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CONTENTS

Acknowledgements (iii)

Abstract (iv)

List of Figures (vi)

List of Tables (vii)

1 INTRODUCTION 7

1.1 What is an ASIC 7

1.2 Importance of ASIC 8

1.3 Organization of the Reports 8

2 TYPES OF ASICS 8

2.1 Full-Custom ASIC 9

2.2 Standard Cell ASIC 11

2.3 Gate Array ASIC

2.3.1 Channeled Gate Array

2.3.2 Channel less Gate Array2.3.3 Structured Gate Array

14

15

1617

3 DIFFERENT TYPES OF POWER CONSUMPTION TECHNIQUES 19

3.1 DTMOS 19

3.2 MTCMOS 19

3.3 VTCMOS 20

3.4 SCCMOS 21

4 H/L CELLS 22

5 ADVANTAGES AND DISADVANTAGES 26

6 CONCLUSIONS 28

REFERENCES 29


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LIST OF FIGURES

2.1 Standard Cell ASIC 13

2.2 Channeled Gate Array 16

2.3 Channelless Gate Array 17

2.4 Structured Gate Array 19

4.1 Examples of H/L Cells 25


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INTRODUCTION

With diminishing process feature sizes and operating voltages, the control of (subthreshold) leakage

currents in modern VLSI designs is becoming a significant challenge. Leakage currents increase

exponentially with decreasing threshold voltages (which are typically maintained at a fixed fraction of

supply voltage). This is expected to be a major concern for VLSI design in the nanometerrealm .

The power consumed by a design in the standby mode of operation is due to leakage currents in its

devices. With the prevalence of portable electronics, it is crucial to keep the leakage currents of a

design small in order to ensure a long battery life in the standby mode of operation. The leakage

current for a pMOS or nMOS device corresponds to the of the device when the device is in the

cutofforsubthresholdregion of operation. The expression for this current is as follows

* Saturation Current Equation:

Ids= K(W/L)(VgsVT)2(1+ Vds).(1)

* Sub-threshold Current Equation:

Ids =(W/L)I0e(Vgs-VT-Voff/vT)(1-e(-Vds/VT).(2)

Here and (typically V) are constants, while is the thermal voltage (26 mV at 300

K) and is the subthreshold swing parameter.

We note that increases exponentially with a decrease in . This is why a reduction in supply

voltage (which is accom-panied by a reduction in threshold voltage) results in exponential increase in

leakage.

Another observation that can be made from (1) is that is significantly larger when . For

typical devices, this is satisfied when . The reason for this is not only that the last term of (1)

is close to unity, but also that with a large value of , would be lowered due to drain induced

barrier lowering (DIBL) ( decreases approximately linearly with in-creasing ) [3], [2].

Therefore, leakage reduction techniques should ensure that the supply voltage is not applied across

a single device, as far as possible.

In recent times, much attention has been devoted to leakage current control [4][13]. Theseapproaches employ devices with increased values to reduce leakage. The modification of is

done either statically (at the time of device fabrication) or dy-namically (by increasing via body


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effect and bulk voltage modulation). We prefer the former for its simplicity of imple-mentation.

1.1 What is an ASIC?

Integrated Circuits are made from silicon wafer, with each wafer holding hundreds of die. An ASIC is

an Application Specific Integrated Circuit. An Integrated Circuit designed is called an ASIC if we

design the ASIC for the specific application. Examples of ASIC include, chip designed for a satellite,

chip designed for a car, chip designed as an interface between memory and CPU etc. Examples of

ICs which are not called ASIC include Memories,Microprocessors etc.

1.2 Types of ASICs :

ICs are made on a thin (a few hundred microns thick), circular silicon wafer , with each wafer

holding hundreds of die (sometimes people use dies or dice for the plural of die). The transistors and

wiring are made from many layers (usually between 10 and 15 distinct layers) built on top of oneanother. Each successive mask layerhas a pattern that is defined using a mask similar to a glass

photographic slide. The first half-dozen or so layers define the transistors. The last half-dozen or so

layers define the metal wires between the transistors (the interconnect).

A full-custom ICincludes some (possibly all) logic cells that are customized and all mask

layers that are customized. A microprocessor is an example of a full-custom ICdesigners spend

many hours squeezing the most out of every last square micron of microprocessor chip space by

hand. Customizing all of the IC features in this way allows designers to include analog circuits,

optimized memory cells, or mechanical structures on an IC, for example. Full-custom ICs are the

most expensive to manufacture and to design. The manufacturing lead time(the time it takes just

to make an ICnot including design time) is typically eight weeks for a full-custom IC. These

specialized full-custom ICs are often intended for a specific application, so we might call some of

them full-custom ASICs.

We shall discuss full-custom ASICs briefly next, but the members of the IC family that we are

more interested in are semicustom ASICs, for which all of the logic cells are predesigned and some

(possibly all) of the mask layers are customized. Using predesigned cells from a cell

librarymakes our lives as designers much, much easier. There are two types of semicustom ASICs

that we shall cover: standard-cellbased ASICs and gate-arraybased ASICs. Following this we shall

describe the programmable ASICs, for which all of the logic cells are predesigned and none of the

mask layers are customized. There are two types of programmable ASICs: the programmable logic

device and, the newest member of the ASIC family, the field-programmable gate array.

1.Full-Custom ASIC:


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For this type of ASIC, the designer designs all or some of the logic cells, layout for that one chip. The

designer does not used predefined gates in the design. Every part of the design is done from

scratch.Bycontrast, full-custom ASIC design defines all the photolithographic layers of the device.

Full custom design is used for both ASIC design and for standard product design.The benefits of full-

custom design usually include reduced area (and therefore recurring component cost), performance

improvements, and also the ability to integrate analog components and other pre-designedand thus

fully verified components, such as microprocessor cores that form a system-on-chip.The

disadvantages of full-custom design can include increased manufacturing and design time, increased

non-recurring engineering costs, more complexity in the computer-aided design(CAD) system, and a

much higher skill requirement on the part of the design team.

For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems,

can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and

easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-

limiting aspect of the design.This is designed by using basic logic gates, circuits or layout specially

for a design.

In a full-custom ASICan engineer designs some or all of the logic cells, circuits, or layout

specifically for one ASIC. This means the designer abandons the approach of using pretested and

precharacterized cells for all or part of that design. It makes sense to take this approach only if there

are no suitable existing cell libraries available that can be used for the entire design. This might be

because existing cell libraries are not fast enough, or the logic cells are not small enough or consume

too much power. You may need to use full-custom design if the ASIC technology is new or so

specialized that there are no existing cell libraries or because the ASIC is so specialized that some

circuits must be custom designed. Fewer and fewer full-custom ICs are being designed because of

the problems with these special parts of the ASIC. There is one growing member of this family,

though, the mixed analog/digital ASIC, which we shall discuss next.

Bipolar technology has historically been used for precision analog functions. There are some

fundamental reasons for this. In all integrated circuits the matching of component characteristics

between chips is very poor, while the matching of characteristics between components on the same

chip is excellent. Suppose we have transistors T1, T2, and T3 on an analog/digital ASIC. The three

transistors are all the same size and are constructed in an identical fashion. Transistors T1 and T2 are

located adjacent to each other and have the same orientation. Transistor T3 is the same size as T1

and T2 but is located on the other side of the chip from T1 and T2 and has a different orientation.

ICs are made in batches called wafer lots. A wafer lot is a group of silicon wafers that are all

processed together. Usually there are between 5 and 30 wafers in a lot. Each wafer can contain tens

or hundreds of chips depending on the size of the IC and the wafer.


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If we were to make measurements of the characteristics of transistors T1, T2, and T3 we would

find the following:

Transistors T1 will have virtually identical characteristics to T2 on the same IC. We say thatthe transistors matchwell or the trackingbetween devices is excellent.

Transistor T3 will match transistors T1 and T2 on the same IC very well, but not as closelyas T1 matches T2 on the same IC.

Transistor T1, T2, and T3 will match fairly well with transistors T1, T2, and T3 on adifferent IC on the same wafer. The matching will depend on how far apart the two ICs are on

the wafer.

Transistors on ICs from different wafers in the same wafer lot will not match very well. Transistors on ICs from different wafer lots will match very poorly.

For many analog designs the close matching of transistors is crucial to circuit operation. For

these circuit designs pairs of transistors are used, located adjacent to each other. Device physics

dictates that a pair of bipolar transistors will always match more precisely than CMOS transistors of

a comparable size. Bipolar technology has historically been more widely used for full-custom analog

design because of its improved precision. Despite its poorer analog properties, the use of CMOS

technology for analog functions is increasing. There are two reasons for this. The first reason is that

CMOS is now by far the most widely available IC technology. Many more CMOS ASICs and

CMOS standard products are now being manufactured than bipolar ICs. The second reason is that

increased levels of integration require mixing analog and digital functions on the same IC: this has

forced designers to find ways to use CMOS technology to implement analog functions. Circuit

designers, using clever new techniques, have been very successful in finding new ways to design

analog CMOS circuits that can approach the accuracy of bipolar analog designs.

2. Standard Cell ASIC:

A cell-based ASIC(cell-based IC, or CBICa common term in Japan, pronounced sea-bick)

uses predesigned logic cells (AND gates, OR gates, multiplexers, and flip-flops, for example) knownas standard cells . We could apply the term CBIC to any IC that uses cells, but it is generally

accepted that a cell-based ASIC or CBIC means a standard-cellbased ASIC.

The standard-cell areas (also called flexible blocks) in a CBIC are built of rows of standard

cellslike a wall built of bricks. The standard-cell areas may be used in combination with larger

predesigned cells, perhaps microcontrollers or even microprocessors, known

as megacells.Megacells are also called megafunctions, full-custom blocks, system-level macros

(SLMs), fixed blocks, cores, or Functional Standard Blocks (FSBs).

The ASIC designer defines only the placement of the standard cells and the interconnect in a

CBIC. However, the standard cells can be placed anywhere on the silicon; this means that all the


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mask layers of a CBIC are customized and are unique to a particular customer. The advantage of

CBICs is that designers save time, money, and reduce risk by using a predesigned, pretested, and

precharacterized standard-cell library. In addition each standard cell can be optimized

individually. During the design of the cell library each and every transistor in every standard cell can

be chosen to maximize speed or minimize area, for example. The disadvantages are the time or

expense of designing or buying the standard-cell library and the time needed to fabricate all layers of

the ASIC for each new design.

Figure shows a CBIC. The important features of this type of ASIC are as follows:

All mask layers are customizedtransistors and interconnect. Custom blocks can be embedded. Manufacturing lead time is about eight weeks.

The designer uses predesigned logic cells such as AND gate, NOR gate, etc. These gates are called

Standard Cells. The advantage of Standard Cell ASICs is that the designers save time, money and

reduce the risk by using a predesigned and pre-tested Standard Cell Library. Also each Standard Cell

can be optimized individually. The Standard Cell Libraries is designed using the Full Custom

Methodology, but you can use these already designed libraries in the design. This design style gives a

designer the same flexibility as the Full Custom design, but reduces the risk.


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Each standard cell in the library is constructed using full-custom design methods, but you can use

these predesigned and pre-characterized circuits without having to do any full-custom design

yourself. This design style gives you the same performance and flexibility advantages of a full-

custom ASIC but reduces design time and reduces risk.

Standard cells are designed to fit together like bricks in a wall. Figure 1.1 shows an example of

a simple standard cell (it is simple in the sense it is not maximized for densitybut ideal for

showing you its internal construction). Power and ground buses (VDD and GND or VSS) run

horizontally on metal lines inside the cells.

Standard-cell design allows the automation of the process of assembling an ASIC. Groups of

standard cells fit horizontally together to form rows. The rows stack vertically to form flexible

rectangular blocks (which you can reshape during design). You may then connect a flexible

blockbuilt from several rows of standard cells to other standard-cell blocks or other full-custom

logic blocks. For example, you might want to include a custom interface to a standard, predesignedmicrocontroller together with some memory. The microcontroller block may be a fixed-size

megacell, you might generate the memory using a memory compiler, and the custom logic and


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memory controller will be built from flexible standard-cell blocks, shaped to fit in the empty spaces

on the chip.

Both cell-based and gate-array ASICs use predefined cells, but there is a differencewe can

change the transistor sizes in a standard cell to optimize speed and performance, but the device sizes

in a gate array are fixed. This results in a trade-off in performance and area in a gate array at the

silicon level. The trade-off between area and performance is made at the library level for a standard-

cell ASIC.

Modern CMOS ASICs use two, three, or more levels (or layers) of metal for interconnect. This

allows wires to cross over different layers in the same way that we use copper traces on different

layers on a printed-circuit board. In a two-level metal CMOS technology, connections to the

standard-cell inputs and outputs are usually made using the second level of metal ( metal2 , the

upper level of metal) at the tops and bottoms of the cells. In a three-level metal technology,

connections may be internal to the logic cell . This allows for more sophisticated routing programs to

take advantage of the extra metal layer to route interconnect over the top of the logic cells.

A connection that needs to cross over a row of standard cells uses a feedthrough. The

term feedthroughcan refer either to the piece of metal that is used to pass a signal through a cell or

to a space in a cell waiting to be used as a feedthroughvery confusing.

In both two-level and three-level metal technology, the power buses (VDD and GND) inside the

standard cells normally use the lowest (closest to the transistors) layer of metal (metal1). The width

of each row of standard cells is adjusted so that they may be aligned using spacer cells. The power

buses, or rails, are then connected to additional vertical power rails using row-end cellsat the

aligned ends of each standard-cell block. If the rows of standard cells are long, then vertical power

rails can also be run in metal2 through the cell rows using special power cellsthat just connect to

VDD and GND. Usually the designer manually controls the number and width of the vertical power

rails connected to the standard-cell blocks during physical design.

3. Gate Array ASIC:

In a gate array(sometimes abbreviated to GA) or gate-arraybased ASIC the transistors are

predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the base

array , and the smallest element that is replicated to make the base array (like an M. C. Escher

drawing, or tiles on a floor) is the base cell(sometimes called aprimitive cell ). Only the top few


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layers of metal, which define the interconnect between transistors, are defined by the designer using

custom masks. To distinguish this type of gate array from other types of gate array, it is often called

a masked gate array(MGA). The designer chooses from a gate-array library of predesigned and

pre-characterized logic cells. The logic cells in a gate-array library are often called macros. The

reason for this is that the base-cell layout is the same for each logic cell, and only the interconnect

(inside cells and between cells) is customized, so that there is a similarity between gate-array macros

and a software macro. Inside IBM, gate-array macros are known as books(so that books are part of a

library), but unfortunately this descriptive term is not very widely used outside IBM.

We can complete the diffusion steps that form the transistors and then stockpile wafers

(sometimes we call a gate array a prediffused array for this reason). Since only the metal

interconnections are unique to an MGA, we can use the stockpiled wafers for different customers as

needed. Using wafers prefabricated up to the metallization steps reduces the time needed to make an

MGA, the turnaround time, to a few days or at most a couple of weeks. The costs for all the initialfabrication steps for an MGA are shared for each customer and this reduces the cost of an MGA

compared to a full-custom or standard-cell ASIC design.

There are the following different types of MGA or gate-arraybased ASICs:

Channeled gate arrays. Channelless gate arrays. Structured gate arrays.

The hyphenation of these terms when they are used as adjectives explains their construction. For

example, in the term channeled gate-array architecture, thegate arrayischanneled , as will be

explained. There are two common ways of arranging (or arraying) the transistors on a MGA: in a

channeled gate array we leave space between the rows of transistors for wiring; the routing on a

channelless gate array uses rows of unused transistors. The channeled gate array was the first to be

developed, but the channelless gate-array architecture is now more widely used. A structured (or

embedded) gate array can be either channeled or channelless but it includes (or embeds) a custom

block.

1.3.1 Channeled Gate Array:

Figure 1.2 shows a channeled gate array. The important features of this type of MGA are:

Only the interconnect is customized. The interconnect uses predefined spaces between rows of base cells. Manufacturing lead time is between two days and two weeks.


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FIGURE 1.2 Achanneled gate-array die. The spaces between rows of the base cells are set

aside for interconnect.

A channeled gate array is similar to a CBICboth use rows of cells separated by channels used

for interconnect. One difference is that the space for interconnect between rows of cells are fixed in

height in a channeled gate array, whereas the space between rows of cells may be adjusted in a

CBIC.

1.3.2 Channelless Gate Array

Figure 1.3 shows a channelless gate array(also known as a channel-free gate array, sea-of-gates

array, or SOGarray). The important features of this type of MGA are as follows:

Only some (the top few) mask layers are customizedthe interconnect. Manufacturing lead time is between two days and two weeks.

FIGURE 1.3 A channelless gate-array or sea-of-gates (SOG) array die. The core area of the


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die is completely filled with an array of base cells (the base array).

The key difference between a channelless gate array and channeled gate array is that there are no

predefined areas set aside for routing between cells on a channelless gate array. Instead we route

over the top of the gate-array devices. We can do this because we customize the contact layer that

defines the connections between metal1, the first layer of metal, and the transistors. When we use anarea of transistors for routing in a channelless array, we do not make any contacts to the devices

lying underneath; we simply leave the transistors unused.

The logic densitythe amount of logic that can be implemented in a given silicon areais higher

forchannelless gate arrays than for channeled gate arrays. This is usually attributed to the difference

in structure between the two types of array. In fact, the difference occurs because the contact mask is

customized in a channelless gate array, but is not usually customized in a channeled gate array. This

leads to denser cells in the channelless architectures. Customizing the contact layer in a channelless

gate array allows us to increase the density of gate-array cells because we can route over the top of

unused contact sites.

1.3.3 Structured Gate Array

An embedded gate arrayor structured gate array (also known as mastersliceor masterimage)

combines some of the features of CBICs and MGAs. One of the disadvantages of the MGA is the


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fixed gate-array base cell. This makes the implementation of memory, for example, difficult and

inefficient. In an embedded gate array we set aside some of the IC area and dedicate it to a specific

function. This embedded area either can contain a different base cell that is more suitable for

building memory cells, or it can contain a complete circuit block, such as a microcontroller.

The important features of this type of MGA are the following:

Only the interconnect is customized. Custom blocks (the same for each design) can be embedded. Manufacturing lead time is between two days and two weeks.

FIGURE 1.4 A structured or embedded gate-array die showing an embedded block in the

upper left corner (a static random-access memory, for example). The rest of the die is filled

with an array of base cells.


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An embedded gate array gives the improved area efficiency and increased performance of a

CBIC but with the lower cost and faster turnaround of an MGA. One disadvantage of an embedded

gate array is that the embedded function is fixed. For example, if an embedded gate array contains an

area set aside for a 32 k-bit memory, but we only need a 16 k-bit memory, then we may have to

waste half of the embedded memory function. However, this may still be more efficient and cheaper

than implementing a 32 k-bit memory using macros on a SOG array.

DIFFERENT TYPES OF POWER CONSUMPTION TECHNIQUES

We have many power consumption techniques in VLSI of which some are very important and need to

study. They are as follows

DTMOS VTCMOS


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SCCMOS MTCMOS

DTMOS:

Dynamic Threshold MOS. Device gate connected to bulk.Vth is high in an off-state and is low in an

on state.The DTMOS however suffers from 10mA order leakage current in 0.5-0.7V Vdd for 1million

logic gate VLSI, because of inherent forward bias current of the p-n junction associated with the

source body junction of the MOSFET.

By combining the SCCMOS and DTMOS the leakage current in a standby mode can be reduced

while the DTMOS remains at high speed in an active mode.

Power Gating/MTCMOS

One of the natural techniques to reduce the leakage of a circuit is to gate the power supply using

power-gating transistors (also called sleep transistors). Typically high- VT power-gating transistors

are placed between the power supplies and the logic gates. This is called the MTCMOS (Multi-

threshold CMOS) approach. In standby, these power-gating transistors are turned off, thus shutting off

power to the gates of the circuit. The MTCMOS approach can reduce circuit leakages by up to 23

orders of magnitude (depending on the threshold voltages and size of the sleep transistors used).

However, the addition of sleep transistors causes an increase in the delay of the circuit. This delaypenalty can be reduced by appropriately sizing up the sleep transistor. The downside to the up-sizing

of the sleep transistor is the accompanied increase in the time and switching energy spent in waking

up the circuit. As a consequence, power-gating (turning off the sleep transistors) is applied only when

the circuit is expected to be in the standby state for a long period of time and when the wake-up time

is tolerable. If a circuit using power-gating/sleep transistors goes in and comes out of the standby state

too often, the power consumptionmay actuallyincrease due to the higher power consumed in waking

up the circuit. Another disadvantage of the MTCMOS approach is the fact that implementation of this

technique requires circuit modification and possibly additional process steps (since high-VT sleep

transistors are used). Also, since cell inputs and outputs as well as bulk nodes float in an MTCMOS

design operating in standby mode, the precise prediction or control of leakage is extremely difficult in

MTCMOS. The voltage of these floating nodes can significantly affect the device threshold voltages.

Hence, it is very difficult to precisely predict or control leakage in MTCMOS designs. Another

drawback of MTCMOS is that memory elements in MTCMOS would require clean power supplies

routed to them if we want to maintain their state in standby mode. There has also been some research

into the sizing of these sleep transistors. A conservative method to sizing the sleep transistors would


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be to first estimate the width of the sleep transistor required for each gate (or standard cell) in a design

such that the delay of the individual gate is within a specified bound and then add up the sleep

transistor widths for all gates to come up with the total sleep transistor width required. The authors

propose a MTCMOS standby device sizing algorithm, which is based on mutually exclusive

discharging of gates. This technique is hard to utilize for random logic circuits as opposed to the

extremely regular circuits.

An MTCMOS-like leakage reduction approach was proposed, in which theMTCMOS sleep devices

are connected in parallel with diodes. This ensures that the supply voltage across the logic is VDD _

2VD, where VD is the forward-biased voltage drop of a diode. The sub-threshold leakage current is

significantly larger when Vds _ nvt. This is because VT drops due to the DIBL (Drain Induced Barrier

Lowering) effect when Vdsis large . The approach of ensures that the Vdsacross the sleep transistors

is limited to VDD_2VD, thus keeping the sub-threshold leakage current low.

2.1.2 Body Biasing/VTCMOS

Increasing VT via body effect and bulk voltage modulation is another way to reduce leakage power.

The leakage current of a transistor decreases with greater applied Reverse Body Bias. Reverse Body

Biasing affects VT through body effect, and subthresholdleakage has an exponential dependence on

VT.

The advantage with VTCMOS is that leakage current can be reduced in the standby mode by applying

a reverse body bias (RBB) that raises the threshold voltage or the delay can be reduced in the active

mode by applying a forward body bias that decreases the threshold voltage. However, with current

technology scaling, the body-effect coefficient _ is reducing. Apart from this, there is also the

overhead of implementing additional body-biasing supplies and the need to use special processes

(such as the triple-well process) in order to provide separate well biasing. This method offers the

advantage of decreasing the leakage in standby mode while not increasing the delay in the active

mode. Here the authors propose a dynamic threshold MOSFET design for low-leakage applications.In this scheme, the device gate is connected to the bulk, resulting in high-speed switching and low-

leakage currents through body effect control. The drawback of this approach is that it is only

applicable in situations where VDD is lower than the diode turn-on voltage. Also, the increased

capacitance of the gate slows the device down, and as a result, the authors propose the use of this

technique for partially depleted SOI (Silicon-On-Insulator) designs.

SCCMOS:Super Cut-Off CMOS .

Gate of PMOS device (which gates the VDD supply) overdriven during standbyoperation - reduces

leakage dramatically.


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Drawback:Complex circuitry required to generate the special voltages.

H/L CELLS: A new low-leakage standard cell-based Application Specific Integrated

Circuit (ASIC) design methodology

One of the most popular ways of reducing leakage is through the use high-VT powergating transistors

(as in the MTCMOS technique). The HL approach is a variant of this technique that uses these power

gating transistors selectively. In the HL approach we first create two low-leakage variants of each cell

in a standard-cell library. If the inputs of a cell during the standby mode of operation are such that the

output has a high value, we minimize the leakage in the pull-down network. Similarly we minimize

leakage in the pull-up network if the output has a low value. In this manner, two low-leakage variants

of each standard cell are obtained. While technology mapping a circuit, we determine the particular

variant to utilize in each instance, so as to minimize leakage of the final mapped

design.

By comparing the results placed-and-routed area, leakage and delay of this new methodology


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against MTCMOS and a regular standard-cell-based design style. The results show that the HL

approach has better speed and area characteristics than MTCMOS implementations. The leakage

current for HL designs can be dramatically lower than the worst-case leakage of MTCMOS-based

designs and two orders of magnitude lower than the leakage of traditional standard cells. An ASIC

design implemented in MTCMOS would require the use of separate power and ground supplies for

latches and combinational logic, while our methodology does away with such a requirement. Another

advantage of our methodology is that the leakage is precisely estimable, in contrast with MTCMOS.

4.1 Philosophy of the HL Approach

The leakage current for a PMOS or NMOS device corresponds to the Ids of the device when the

device is in the cut-off orsub-threshold region of operation. The expression for this current [1] is:

Ids =(W/L)I0e(Vgs-VT-Voff/vT)(1-e(-Vds/VT)

Here ID0 and Voff (typically Voff D _0:08V ) are constants, while vtis the thermal voltage (26mV at

300K) and n is the sub-threshold swing parameter.

We note that Ids increases exponentially with a decrease in VT. This is why a reduction in supply

voltage (which is accompanied by a reduction in threshold voltage)results in exponential increase in

leakage.

Another observation that can be made from is that Ids is significantly larger when Vds _ n vt. For

typical devices, this is satisfied when Vds ' VDD. The reason for this is not only that the last term is

close to unity, but also that with a large value of Vds, VT would be lowered due to drain-induced

barrier loweringDIBL (VT decreases approximately linearly with increasing Vds). Therefore,

leakage reduction techniques should ensure that the supply voltage is not applied across a single

device, as far as possible.

Our approach to leakage reduction attempts to ensure that the supply voltage is applied across more

than one turned-off device and one of those devices is a high- VT device. This is achieved by

selectively introducing a high-VT PMOS or NMOS supply gating device in either the pull-up network

of a gate (if the output is low in standby) or the pull-down network of a gate (if the output is high in

standby). By this design choice, we obtain standard cells with both low and predictable standby

leakage currents, unlike MTCMOS-based approaches.


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4.2 The HL Approach

Our goal is to design standard cells with predictably low leakage currents. To achieve this, we design

two variants of each standard cell. The two variants of each standard cell are designated H and L.

If the inputs of a cell during the standby mode of operation are such that the output has a high value,

we minimize the leakage in the pull-down network. So a footer device (a high-VT NMOS with its

gate connected tostandby) is used. We call such a cell the H variant of the standard cell. Similarly,

if the inputs of a cell during the standby mode of operation are such that the output has a low value,

we minimize the leakage in the pull-up network by adding a header device (a high-VT PMOS with its

gate connectedstandby), and call such a cell the L variant of the standard cell.


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4.3Layout Floor plan

Regular Cell L-VarientH-Varient


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Advantages and Disadvantages of the HL Approach

The advantages of the HL methodology are as follows:

1. By ensuring that each cell has a full-rail output value during standby operation, we makesure that the leakage of each standard cell, and therefore the leakage of a standard-cell

based design, is precisely predictable. Therefore, our methodology avoids the

unpredictability of leakage that results when using the MTCMOS style of design. This

unpredictability occurs due to the fact that in MTCMOS, cell outputs, inputs and bulk

voltages float to unknown values that are dependent on

various processing and design factors.

2. Since our invertingH/L cells utilize exactly one supply gating device (as opposed to twodevices for MTCMOS), our cells exhibit better delay characteristics thanMTCMOS for one

output transition (the falling transition for L gates and risingtransition for H gates). It possible to

useonly footer devices, their implementation uses both header and footer devices.Though using

only a footer device will reduce the delay penalties, the leakagecurrent increases.


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3. ForMTCMOS designs, memory elements would require clean power and groundsuppliesif they were to retain state during standby mode . With the HL approach,the inputs to

acombinational block are fixed in the standby mode. Hence,the states of the memory elements

that drive these inputs are also fixed. Therefore,our technique can be applied to sequential

elements as well (by using headerdevices when the leakage path is through the PMOS stack and

using footer deviceswhen the leakage path is through the NMOS stack). Alternatively, we could

utilize the same flip-flop design as in . In either case, the HL approach would not require special

clean supplies to be routed to the flip-flop cell, resulting in lower area utilization for sequential

designs.

4. For many of the standard cells, and particularly for larger cells that exhibit large values ofleakage, our H/L cells exhibit much lower leakage current. However,there are cells for which our

cells exhibit comparable or greater leakage thanMTCMOS as well.

5.

By implementing the header and footer devices in a layout-efficient manner, weensurethat the layout overhead of H/L standard-cells is minimized. Our choice oflayout also allows the

header and footer device regions to be free for over-the-cellrouting.

The disadvantages of H/L Cells are as follows:

1. The determination of the primary input assignments to utilize for the standbymode is acomplex once. Although our current implementation makes this decisionarbitrarily.

2. Using the HL approach requires that the primary inputs to the circuit be driventoknown values in the standby state. However, if we assume that a combinationalblock of

logic implemented using our approach is driven by flip-flops that arescan-enabled, then the

required input vector can be simply scanned in beforethe circuit goes into the standby state.

Alternatively, special circuitry (such as aNAND2 or a NOR2 gate with the standby signal as

one of the inputs) could beadded at the primary inputs.

3. The experiments presented in this chapter can be improved if the technologymappingtools are modified. Assuming that the primary input vector is predeterminedand that we use a

dynamic programming-based technology mapper, themapper would need to store the best

match at any node as well as the logic stateof that best match. For any new node that is being

mapped, its logic state cantherefore be determined, and so we would know whether to use a H

or L cell forthat mapping. In either case, we would know what delay or area value to use foran

optimum match at that node. In reality, the problems of technology mappingand the

determination of an optimal primary input vector are coupled.

4. Our method requires that the standby signals be routed to each cell. However, we haveovercome this problem by designing the layout of H/L cells such that therouting of standbysignal is performed by abutment, while also leaving free spacefor over-the-cell routing above

the region where the standby signals are run.


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CONCLUSIONS:

Process feature sizes / operating voltages are diminishing relentlessly. Threshold voltages of the MOS devices reduced along with operating voltages to satisfy

speed requirements.

Leakage (sub-threshold) currents increase as a consequence. Low leakage crucial for portable electronics to ensure long battery life.


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References:

[1] Nikhil Jayakumar and Sunil P.Khatri, A Predictably Low Leakage ASIC Design Style, IEEE

Transactions on VLSI Systems, vol. 15,No.3, pp. 276-285, March-2007.

[2] J. Rabaey, Digital Integrated Circuits: A Design Perspective, ser. Prentice-Hall Electronics and

VLSI Series. Englewood Cliffs, NJ: Prentice-Hall, 1996.

[3] E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha,H. Savoj, P. R.

Stephan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, SIS: A system for sequential circuit

synthesis, Electron.Res. Lab, Univ. Calif., Berkeley, Tech. Rep. UCB/ERL M92/41, 1992.

low leakage asic design style

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