ltc1608 - high speed, 16-bit, 500ksps sampling a/d ...€¦ · 1 ltc1608 high speed, 16-bit,...
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1
LTC1608
High Speed, 16-Bit, 500kspsSampling A/D Converter
with Shutdown
The LTC®1608 is a 500ksps, 16-bit sampling A/D con-verter that draws only 270mW from ±5V supplies. Thishigh performance device includes a high dynamic rangesample-and-hold, a precision reference and a high speedparallel output. Two digitally selectable power shutdownmodes provide power savings for low power systems.
The LTC1608’s full-scale input range is ±2.5V. Outstand-ing AC performance includes 90dB S/(N+D) and –100dBTHD at a sample rate of 500ksps.
The unique differential input sample-and-hold can acquiresingle-ended or differential input signals up to its 15MHzbandwidth. The 68dB common mode rejection allowsusers to eliminate ground loops and common mode noiseby measuring signals differentially from the source.
The ADC has µP compatible,16-bit parallel output port.There is no pipeline delay in conversion results. A separateconvert start input and a data ready signal (BUSY) easeconnections to FlFOs, DSPs and microprocessors.
A Complete, 500ksps 16-Bit ADC 90dB S/(N+D) and –100dB THD (Typ) Power Dissipation: 270mW (Typ) No Pipeline Delay No Missing Codes Over Temperature Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference
or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth ±2.5V Bipolar Input Range 36-Pin SSOP Package Pin Compatible with the LTC1604
, LTC and LT are registered trademarks of Linear Technology Corporation.
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
FREQUENCY (kHz)0
–40
–20
0
150 200
1608 TA02
–60
–80
50 100 250
–100
–120
–140
AMPL
ITUD
E (d
B)
fSAMPLE = 500kHzfIN = 98.754kHzSINAD = 86.7dBTHD = –92.6dB
LTC1608 4096 Point FFT
Circuitry in the LTC1608 is covered under US Patent #5,764,175
FEATURES DESCRIPTIO
U
APPLICATIO SU
TYPICAL APPLICATIO
U
2.2µF 10µF 10µF10Ω
22µF
4
6
DIFFERENTIALANALOG INPUT
±2.5V
REFCOMP
CONTROLLOGICAND
TIMING
B15 TO B016-BIT
SAMPLINGADC–
+10µF
5V OR3V
µPCONTROLLINES
D15 TO D0
OUTPUTBUFFERS
16-BITPARALLELBUS
11 TO 261608 TA01
OGND
OVDD
28
29
1
2
AIN+
AIN–
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
LTC1608
3 36 35 109
5V 5V
AVDD AVDD DVDD DGNDVREF
8
AGNDAGND
7
AGND
5
AGND
34
–5V
VSS
10µF
2.5VREF
10µF
1.75X+
+ + +
+
+
2
LTC1608
ORDERPART NUMBER
AVDD = DVDD = OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................ 6VNegative Supply Voltage (VSS) ............................... –6VTotal Supply Voltage (VDD to VSS) .......................... 12VAnalog Input Voltage
(Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V)VREF Voltage (Note 4) ................. –0.3V to (VDD + 0.3V)REFCOMP Voltage (Note 4) ......... –0.3V to (VDD + 0.3V)Digital Input Voltage (Note 4) ....................–0.3V to 10VDigital Output Voltage .................. –0.3V to (VDD + 0.3V)Power Dissipation ............................................. 500mWOperating Temperature Range
LTC1608C .............................................. 0°C to 70°CLTC1608I ............................................ –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°CLead Temperature (Soldering, 10 sec)................. 300°C
LTC1608CGLTC1608ACGLTC1608IGLTC1608AIG
PUT
U
IAA
U
LOG
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ –4.75V, ±2.5 VVSS ≤ (AIN
–, AIN+) ≤ AVDD
IIN Analog Input Leakage Current CS = High ±1 µA
CIN Analog Input Capacitance Between Conversions 43 pFDuring Conversions 5 pF
tACQ Sample-and-Hold Acquisition Time 380 ns
tAP Sample-and-Hold Acquisition Delay Time –1.5 ns
tjitter Sample-and-Hold Acquisition Delay Time Jitter 5 psRMS
CMRR Analog Input Common Mode Rejection Ratio – 2.5V < (AIN– = AIN
+) < 2.5V 68 dB
The denotes specifications that apply over the full operating temperature range, otherwisespecifications are at TA = 25°C.
TJMAX = 125°C, θJA = 95°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
AVDD
AVDD
VSS
SHDN
CS
CONV
RD
OVDD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
AIN+
AIN–
VREF
REFCOMP
AGND
AGND
AGND
AGND
DVDD
DGND
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
C CHARA TERISTICSCOU
VERTER
LTC1608 LTC1608APARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution (No Missing Codes) 15 16 16 16 Bits
Integral Linearity Error (Note 7) ±1 ±4 ±0.5 ±2 LSB
Transition Noise (Note 8) 0.7 0.7 LSBRMS
Offset Error (Note 9) ±0.05 ±0.125 ±0.05 ±0.125 % FSR
Offset Tempco (Note 9) 0.5 0.5 ppm/°C
Full-Scale Error Internal Reference ±0.125 ±0.25 ±0.125 ±0.25 %External Reference ±0.25 ±0.25 %
Full-Scale Tempco IOUT(Reference) = 0, Internal Reference ±15 ±15 ppm/°C
The denotes specifications that apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted.
ABSOLUTE AXI U RATI GS
W WW U
PACKAGE/ORDER I FOR ATIOU UW
Consult factory for parts specified with wider operating temperature ranges.
3
LTC1608
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
S/N Signal-to-Noise Ratio 5kHz Input Signal 90 dB100kHz Input Signal 88 dB
S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 90 dB100kHz Input Signal (Note 10) 84 dB
THD Total Harmonic Distortion 5kHz Input Signal –100 dBUp to 5th Harmonic 100kHz Input Signal –91 dB
SFDR Spurious Free Dynamic Range 100kHz Input Signal 94 dB
IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz –88 dB
Full Power Bandwidth 5 MHz
Full Linear Bandwidth (S/(N + D) ≥ 84dB) 350 kHz
PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 2.475 2.500 2.515 V
VREF Output Tempco IOUT = 0 ±15 ppm/°C
VREF Line Regulation 4.75 ≤ VDD ≤ 5.25V 0.01 LSB/V–5.25V ≤ VSS ≤ –4.75V 0.01 LSB/V
VREF Output Resistance 0 ≤ IOUT ≤ 1mA 7.5 kΩREFCOMP Output Voltage IOUT = 0 4.375 V
DY A IC ACCURACY
U W
TA = 25°C (Note 5)
I TER AL REFERE CE CHARACTERISTICSU U U
TA = 25°C (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U U
The denotes specifications that apply over the fulloperating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 5.25V 2.4 V
VIL Low Level Input Voltage VDD = 4.75V 0.8 V
IIN Digital Input Current VIN = 0V to VDD ±10 µA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage VDD = 4.75V, IOUT = –10µA 4.5 VVDD = 4.75V, IOUT = – 400µA 4.0 V
VOL Low Level Output Voltage VDD = 4.75V, IOUT = 160µA 0.05 VVDD = 4.75V, IOUT = 1.6mA 0.10 0.4 V
IOZ Hi-Z Output Leakage D15 to D0 VOUT = 0V to VDD, CS High ±10 µA
COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 11) 15 pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = VDD 10 mA
4
LTC1608
POWER REQUIRE E TS
W U
The denotes specifications that apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V
VSS Negative Supply Voltage (Note 12) – 4.75 – 5.25 V
IDD Positive Supply Current CS = RD = 0V 22 35 mANap Mode CS = 0V, SHDN = 0V 1.5 2.4 mASleep Mode CS = 5V, SHDN = 0V 1 100 µA
ISS Negative Supply Current CS = RD = 0V 32 49 mANap Mode CS = 0V, SHDN = 0V 1 100 µASleep Mode CS = 5V, SHDN = 0V 1 100 µA
PD Power Dissipation CS = RD = 0V 270 420 mWNap Mode CS = 0V, SHDN = 0V 7.5 12 mWSleep Mode CS = 5V, SHDN = 0V 0.01 1 mW
TI I G CHARACTERISTICSUW
The denotes specifications that apply over the full operating temperature range,otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency 500 600 kHz
tCONV Conversion Time 1.0 1.45 1.8 µs
tACQ Acquisition Time (Notes 11, 14) 400 ns
tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) 1.67 2 µs
t1 CS to RD Setup Time (Notes 11, 12, 15) 0 ns
t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) 10 ns
t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) 10 ns
t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns
t5 CONVST Low Time (Note 12) 40 ns
t6 CONVST to BUSY Delay CL = 25pF 36 ns 80 ns
t7 Data Ready Before BUSY↑ 60 ns 32 ns
t8 Delay Between Conversions (Note 12) 200 ns
t9 Wait Time RD↓ After BUSY↑ (Note 12) –5 ns
t10 Data Access Time After RD↓ CL = 25pF 25 40 ns 50 ns
CL = 100pF (Note 11) 45 60 ns 75 ns
t11 Bus Relinquish Time 30 50 ns 60 ns
t12 RD Low Time (Note 12) t10 ns
t13 CONVST High Time (Note 12) 40 ns
t14 Aperture Delay of Sample-and-Hold 2 ns
Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2: All voltage values are with respect to ground with DGND, OGNDand AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, theywill be clamped by internal diodes. This product can handle input currentsgreater than 100mA below VSS or above VDD without latchup.
5
LTC1608
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortionis measured at 100kHz. These results are used to calculate Signal-to-NosiePlus Distortion (SINAD).Note 11: Guaranteed by design, not subject to test.Note 12: Recommended operating conditions.Note 13: The falling CONVST edge starts a conversion. If CONVST returnshigh at a critical point during the conversion it can create small errors. Forbest performance ensure that CONVST returns high either within 250nsafter conversion start or after BUSY rises.Note 14: The acquisition time would go up to 400ns and the conversiontime would go up to 1.8µs. However, the throughput time (acquisition +conversion) is guaranteed by test to be 2µs max.Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓.
Note 4: When these pin voltages are taken below VSS, they will be clampedby internal diodes. This product can handle input currents greater than100mA below VSS without latchup. These pins are not clamped to VDD.Note 5: VDD = 5V, VSS = –5V, fSMPL = 500kHz, and tr = tf = 5ns unlessotherwise specified.Note 6: Linearity, offset and full-scale specification apply for a single-ended AIN
+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from astraight line passing through the actual endpoints of the transfer curve.The deviation is measured from the center of the quantization band.Note 8: Typical RMS noise at the code transitions.Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB whenthe output code flickers between 0000 0000 0000 0000 and 1111 11111111 1111.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Integral Nonlinearityvs Output Code
CODE–32768 32767
INL
(LSB
)
0
0.5
–16384 163840
1608 G01
1.0
1.5
2.0
–0.5
–1.0
–1.5
–2.0
Differential Nonlinearityvs Output Code
CODE–32768 32767
–1.0
DNL
(LSB
)
–0.8
–0.4
–0.2
0
1.0
0.4
–16384 163840
1608 G02
–0.6
0.6
0.8
0.2
S/(N + D) vs Input Frequencyand Amplitude
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SINA
D (d
B)
1608 G03
1k 10k 100k 1M
VIN = 0dB
VIN = –20dB
VIN = –40dB
Signal-to-Noise Ratiovs Input Frequency Distortion vs Input Frequency
Spurious-Free Dynamic Rangevs Input Frequency
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SIGN
AL-T
O-NO
ISE
RATI
O (d
B)
1608 G04
1k 10k 100k 1MINPUT FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
AMPL
ITUD
E (d
B BE
LOW
THE
FUN
DAM
ENTA
L)
1608 G05
1k 10k 100k 1M
THD3RD2ND
INPUT FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SPUR
IOUS
-FRE
E DY
NAM
IC R
ANGE
(dB)
1608 G06
1k 10k 100k 1M
6
LTC1608
AIN+ (Pin 1): Positive Analog Input. The ADC converts the
difference voltage between AIN+ and AIN
– with a differen-tial range of ±2.5V. AIN
+ has a ±2.5V input range whenAIN
– is grounded.
AIN– (Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with AIN+.
VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with2.2µF tantalum in parallel with 0.1µF ceramic.
REFCOMP (Pin 4): 4.375V (Nominal) Reference Compen-sation Pin. Bypass to AGND with 22µF tantalum in parallelwith 0.1µF ceramic. This is not recommended for use asan external reference due to part-to-part output voltagevariations and glitches that occur during the conversion.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog groundplane.
DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGNDwith 10µF tantalum in parallel with 0.1µF ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie toanalog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converterstatus. It is low when a conversion is in progress. Data isvalid on the rising edge of BUSY.
OGND (Pin 28): Digital Ground for Output Drivers.
OVDD (Pin 29): Digital Power Supply for Output Drivers.Bypass to OGND with 10µF tantalum in parallel with 0.1µFceramic.
RD (Pin 30): Read Input. A logic low enables the outputdrivers when CS is low.
CONVST (Pin 31): Conversion Start Signal. This activelow signal starts a conversion on its falling edge when CSis low.
CS (Pin 32): The Chip Select Input. Must be low for the ADCto recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low withCS low for nap mode. Drive this pin low with CS high forsleep mode.
VSS (Pin 34): –5V Negative Supply. Bypass to AGND with10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGNDwith 10µF tantalum in parallel with 0.1µF ceramic.
AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGNDwith 10µF tantalum in parallel with 0.1µF ceramic andconnect this pin to Pin 35 with a 10Ω resistor.
UUU
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Intermodulation DistortionPower Supply Feedthroughvs Ripple Frequency
Input Common Mode Rejectionvs Input Frequency
FREQUENCY (kHz)0
–40
–20
0
200
1608 G07
–60
–80
50 100 150 250
–100
–120
–140
AMPL
ITUD
E (d
B)
fSAMPLE = 500kHzfIN1 = 96.56kHzfIN2 = 99.98kHz
INPUT FREQUENCY (Hz)1k
AMPL
ITUD
E OF
POW
ER S
UPPL
YFE
EDTH
ROUG
H (d
B)
0
–20
–40
–60
–80
–100
–120
–14010k 100k 1M
1608 G08
fSAMPLE = 500kHzVRIPPLE = 10mV
VSSAVDD
INPUT FREQUENCY (Hz)1k
COM
MON
MOD
E RE
JECT
ION
(dB)
80
70
60
50
40
30
20
10
010k 100k
1608 G14a
1M
7
LTC1608
UU WFU CTIO AL BLOCK DIAGRA
Load Circuits for Access Timing Load Circuits for Output Float Delay
1k
(A) Hi-Z TO VOH AND VOL TO VOH
CL
1k
5V
DNDN
(B) Hi-Z TO VOL AND VOH TO VOL
CL
1608 TC01
1k
(A) VOH TO Hi-Z
CL
1k
5V
DNDN
(B) VOL TO Hi-Z
CL
1608 TC02
TEST CIRCUITS
2.2µF 10µF 10µF10Ω
22µF
4
6
DIFFERENTIALANALOG INPUT
±2.5V
REFCOMP
4.375V
CONTROLLOGICAND
TIMING
B15 TO B016-BIT
SAMPLINGADC–
+10µF
5V OR3V
µPCONTROLLINES
D15 TO D0
OUTPUTBUFFERS
16-BITPARALLELBUS
11 TO 26
1608 BD
OGND
OVDD
28
29
1
2
AIN+
AIN–
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
3 36 35 109
5V 5V
AVDD AVDD DVDD DGNDVREF
8
AGNDAGND
7
AGND
5
AGND
34
–5V
VSS
10µF
2.5VREF
10µF
1.75X+
+ + +
+
+
APPLICATIO S I FOR ATIO
WU UU
CONVERSION DETAILS
The LTC1608 uses a successive approximation algorithmand internal sample-and-hold circuit to convert an analogsignal to a 16-bit parallel output. The ADC is complete witha sample-and-hold, a precision reference and an internalclock. The control logic provides easy interface to micro-processors and DSPs. (Please refer to the Digital Interfacesection for the data format.)
Conversion start is controlled by the CS and CONVSTinputs. At the start of the conversion, the successiveapproximation register (SAR) resets. Once a conversioncycle has begun, it cannot be restarted.
During the conversion, the internal differential 16-bitcapacitive DAC output is sequenced by the SAR from theMost Significant Bit (MSB) to the Least Significant Bit(LSB). Referring to Figure 1, the AIN
+ and AIN– inputs are
acquired during the acquire phase and the comparatoroffset is nulled by the zeroing switches. In this acquirephase, a duration of 480ns will provide enough time for thesample-and-hold capacitors to acquire the analog signal.During the convert phase, the comparator zeroing switchesopen, putting the comparator into compare mode. Theinput switches connect the CSMPL capacitors to ground,transferring the differential analog input charge onto thesumming junctions. This input charge is successively
8
LTC1608
–
+COMP
AIN+
CSMPL
HOLD
SAMPLE
AIN–
CSMPL
+CDAC
+VDAC
–CDAC
–VDAC
HOLD
HOLDSAMPLE
HOLD
SAR OUTPUTLATCHES
16 D15
D0
1608 F01
•••
ZEROING SWITCHES
Figure 1. Simplified Block Diagram
compared with the binary-weighted charges supplied bythe differential capacitive DAC. Bit decisions are made bythe high speed comparator. At the end of a conversion, thedifferential DAC output balances the AIN
+ and AIN– input
charges. The SAR contents (a 16-bit data word) whichrepresent the difference of AIN
+ and AIN– are loaded into
the 16-bit output latches.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-cessors as a memory mapped device. The CS and RDcontrol inputs are common to all peripheral memoryinterfacing. A separate CONVST is used to initiate a con-version.
Internal Clock
The A/D converter has an internal clock that runs the A/Dconversion. The internal clock is factory trimmed to achievea typical conversion time of 1.45µs and a maximumconversion time of 1.8µs over the full temperature range.No external adjustments are required. The guaranteedmaximum acquisition time is 400ns. In addition, a through-put time (acquisition + conversion) of 2µs and a minimumsampling rate of 500ksps are guaranteed.
APPLICATIO S I FOR ATIO
WU UU
3V Input/Output Compatible
The LTC1608 operates on ±5V supplies, which makes thedevice easy to interface to 5V digital systems. This devicecan also talk to 3V digital systems: the digital input pins(SHDN, CS, CONVST and RD) of the LTC1608 recognize3V or 5V inputs. The LTC1608 has a dedicated outputsupply pin (OVDD) that controls the output swings of thedigital output pins (D0 to D15, BUSY) and allows the partto talk to either 3V or 5V digital systems. The output istwo’s complement binary.
Power Shutdown
The LTC1608 provides two power shutdown modes, Napand Sleep, to save power during inactive periods. The Napmode reduces the power by 95% and leaves only thedigital logic and reference powered up. The wake-up timefrom Nap to active is 200ns. In Sleep mode, all biascurrents are shut down and only leakage current remains(about 1µA). Wake-up time from Sleep mode is muchlonger since the reference circuit must power up andsettle. Sleep mode wake-up time is dependent on thevalue of the capacitor connected to the REFCOMP (Pin 4).The wake-up time is 80ms with the recommended 22µFcapacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is inshutdown when SHDN is low. The shutdown mode isselected with Pin 32 (CS). When SHDN is low, CS lowselects nap and CS high selects sleep.
Figure 2a. Nap Mode to Sleep Mode Timing
t3
SHDN
CS1608 F02a
t4
SHDN
CONVST1608 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
9
LTC1608
Timing and Control
Conversion start and data read operations are controlledby three digital inputs: CONVST, CS and RD. A falling edgeapplied to the CONVST pin will start a conversion after theADC has been selected (i.e., CS is low). Once initiated, itcannot be restarted until the conversion is complete.Converter status is indicated by the BUSY output. BUSY islow during a conversion.
We recommend using a narrow logic low or narrow logichigh CONVST pulse to start a conversion as shown inFigures 5 and 6. A narrow low or high CONVST pulseprevents the rising edge of the CONVST pulse from upset-ting the critical bit decisions during the conversion time.Figure 4 shows the change of the differential nonlinearityerror versus the low time of the CONVST pulse. As shown,if CONVST returns high early in the conversion (e.g.,CONVST low time <300ns), accuracy is unaffected. Simi-larly, if CONVST returns high after the conversion is over
t2
t1
CS
CONVST
RD
1608 F03
Figure 3. CS top CONVST Setup Timing
Figure 4. Change in DNL vs CONVST Low Time. Be Sure theCONVST Pulse Returns High Early in the Conversion or Afterthe End of Conversion
0
CHAN
GE IN
DNL
(LSB
)
1750 2000
1608 F04
250 500 1000750 1250 1500
4
3
2
1
0
CONVST LOW TIME, t5 (ns)
tCONV tACQ
APPLICATIO S I FOR ATIO
WU UU
(e.g., CONVST low time >tCONV), accuracy is unaffected.For best results, keep t5 less than 500ns or greater thantCONV.
Figures 5 through 9 show several different modes ofoperation. In modes 1a and 1b (Figures 5 and 6), CS andRD are both tied low. The falling edge of CONVST starts theconversion. The data outputs are always enabled and datacan be latched with the BUSY rising edge. Mode 1a showsoperation with a narrow logic low CONVST pulse. Mode 1bshows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge ofCONVST signal starts the conversion. Data outputs are inthree-state until read by the MPU with the RD signal. Mode2 can be used for operation with a shared data bus.
In slow memory and ROM modes (Figures 8 and 9), CS istied low and CONVST and RD are tied together. The MPUstarts the conversion and reads the output with the com-bined CONVST-RD signal. Conversions are started by theMPU or DSP (no external sample clock is needed).
In slow memory mode, the processor applies a logic lowto RD (= CONVST), starting the conversion. BUSY goeslow, forcing the processor into a wait state. The previousconversion result appears on the data outputs. When theconversion is complete, the new conversion resultsappear on the data outputs; BUSY goes high, releasing theprocessor and the processor takes RD (=CONVST) backhigh and reads the new conversion data.
In ROM mode, the processor takes RD (=CONVST) low,starting a conversion and reading the previous conversionresult. After the conversion is complete, the processor canread the new result and initiate another conversion.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog InputsThe differential analog inputs of the LTC1608 are easy todrive. The inputs may be driven differentially or as a single-ended input (i.e., the AIN
– input is grounded). The AIN+ and
AIN– inputs are sampled at the same instant. Any un-
wanted signal that is common mode to both inputs will bereduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current
10
LTC1608
(CONVST = ) Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
DATA ND15 TO D0
DATA (N + 1)D15 TO D0
DATA (N – 1)D15 TO D0
CONVST
CS = RD = 0
BUSY
1608 F05
t5
tCONV
t6 t8
t7
DATA
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
CONVST
CS = 0
BUSY
1608 F07
t5
tCONV t8
t13
t6
t9t12
DATA ND15 TO D0
t11
t10
RD
DATA
DATA (N – 1)D15 TO D0
CONVST
BUSY
1608 F06
tCONV
t6
t13
t7
CS = RD = 0
DATA ND15 TO D0
DATA (N + 1)D15 TO D0DATA
t5
t6
t8
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled(CONVST = )
APPLICATIO S I FOR ATIO
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11
LTC1608
RD = CONVST
CS = 0
BUSY
1608 F08
tCONV
t6
DATA (N – 1)D15 TO D0DATA DATA N
D15 TO D0DATA (N + 1)D15 TO D0
DATA ND15 TO D0
t11
t8
t10 t7
RD = CONVST
BUSY
CS = 0
1608 F09
tCONV
t6
DATA (N – 1)D15 TO D0DATA DATA N
D15 TO D0
t10
t11
t8
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
APPLICATIO S I FOR ATIO
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spike while charging the sample-and-hold capacitors atthe end of conversion. During conversion, the analoginputs draw only a small leakage current. If the sourceimpedance of the driving circuit is low, then the LTC1608inputs can be driven directly. As source impedance in-creases so will acquisition time (see Figure 10). Forminimum acquisition time with high source impedance, abuffer amplifier should be used. The only requirement isthat the amplifier driving the analog input(s) must settleafter the small current spike before the next conversionstarts (settling time must be 200ns for full throughputrate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirementsare taken into consideration. First, to limit the magnitudeof the voltage spike seen by the amplifier from chargingthe sampling capacitor, choose an amplifier that has alow output impedance (<100Ω) at the closed-loop band-width frequency. For example, if an amplifier is used in again of +1 and has a unity-gain bandwidth of 50MHz, then
Figure 10. tACQ vs Source Resistance
SOURCE RESISTANCE (Ω)1 10 100 1k 10k
ACQU
ISIT
ION
TIM
E (µ
s)
10
1
0.1
0.01
1608 F10
the output impedance at 50MHz should be less than100Ω. The second requirement is that the closed-loopbandwidth must be greater than 15MHz to ensureadequate small-signal settling for full throughput rate. Ifslower op amps are used, more settling time can beprovided by increasing the time between conversions.
12
LTC1608
LinearView is a trademark of Linear Technology Corporation.
APPLICATIO S I FOR ATIO
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The best choice for an op amp to drive the LTC1608 willdepend on the application. Generally applications fall intotwo categories: AC applications where dynamic specifi-cations are most critical and time domain applicationswhere DC accuracy and settling time are most critical.The following list is a summary of the op amps that aresuitable for driving the LTC1608. More detailed informa-tion is available in the Linear Technology databooks, theLinearViewTM CD-ROM and on our web site at:www.linear-tech. com.
LT ®1007: Low Noise Precision Amplifier. 2.7mA supplycurrent, ±5V to ±15V supplies, gain bandwidth product8MHz, DC applications.
LT1097: Low Cost, Low Power Precision Amplifier. 300µAsupply current, ±5V to ±15V supplies, gain bandwidthproduct 0.7MHz, DC applications.
LT1227: 140MHz Video Current Feedback Amplifier. 10mAsupply current, ±5V to ±15V supplies, low noise and lowdistortion.
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup-ply current, ±5V to ±15V supplies, good AC/DC specs.
LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-ply current, good AC/DC specs.
LT1364/LT1365: Dual and Quad 50MHz Voltage FeedbackAmplifiers. 6.3mA supply current per amplifier, goodAC/DC specs.
LT1468: 90MHz, 22V/µs 16-Bit Accurate OperationalAmplifier. 3.8mA supply current, excellent DC specs andvery low distortion performance to 100kHz.
LT1469: Dual 90MHz, 22V/µs 16-Bit Accurate OperationalAmplifier. 4.1mA supply current, excellent DC specs andvery low distortion performance to 100kHz.
Input Filtering
The noise and the distortion of the input amplifier andother circuitry must be considered since they will add tothe LTC1608 noise and distortion. The small-signal band-width of the sample-and-hold circuit is 15MHz. Any noiseor distortion products that are present at the analog inputswill be summed over this entire bandwidth. Noisy inputcircuitry should be filtered prior to the analog inputs to
LTC1608
AIN+
AIN–
VREF
REFCOMP
AGND
1608 F11
1
2
3
4
522µF
3000pF
100ΩANALOG INPUT
Figure 11. RC Input Filter
minimize noise. A simple 1-pole RC filter is sufficient formany applications. For example, Figure 11 shows a 3000pFcapacitor from AIN
+ to ground and a 100Ω source resistorto limit the input bandwidth to 530kHz. The 3000pFcapacitor also acts as a charge reservoir for the inputsample-and-hold and isolates the ADC input from sam-pling glitch sensitive circuitry. High quality capacitors andresistors should be used since these components can adddistortion. NPO and silver mica type dielectric capacitorshave excellent linearity. Carbon surface mount resistors canalso generate distortion from self heating and from damagethat may occur during soldering. Metal film surface mountresistors are much less susceptible to both problems.
Input Range
The ±2.5V input range of the LTC1608 is optimized for lownoise and low distortion. Most op amps also perform wellover this same range, allowing direct coupling to theanalog inputs and eliminating the need for special transla-tion circuitry.
Some applications may require other input ranges. TheLTC1608 differential inputs and reference circuitry can ac-commodate other input ranges often with little or no addi-tional circuitry. The following sections describe the refer-ence and input circuitry and how they affect the input range.
Internal Reference
The LTC1608 has an on-chip, temperature compensated,curvature corrected, bandgap reference that is factorytrimmed to 2.500V. It is connected internally to a referenceamplifier and is available at VREF (Pin 3) (see Figure 12a).
13
LTC1608
APPLICATIO S I FOR ATIO
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R212k
R316k
REFERENCEAMP
22µF
REFCOMP
AGND
VREF
R17.5k3
4
5
2.500V
4.375V
LTC1608
1608 F12a
BANDGAPREFERENCE
Figure 12a. LTC1608 Reference Circuit
1
2
3
0.1µF22µF
ANALOGINPUT
1608 F12b
LT1019A-2.5VOUT
VIN
5VAIN
+
AIN–
VREF
LTC1608
AGND
REFCOMP
5
4
+
Figure 12b. Using the LT1019-2.5 as an External Reference
A 7.5k resistor is in series with the output so that it can beeasily overdriven by an external reference or othercircuitry (see Figure 12b). The reference amplifier gainsthe voltage at the VREF pin by 1.75 to create the requiredinternal reference voltage. This provides bufferingbetween the VREF pin and the high speed capacitive DAC.The reference amplifier compensation pin (REFCOMP, Pin4) must be bypassed with a capacitor to ground. Thereference amplifier is stable with capacitors of 22µF orgreater. Using a 0.1µF ceramic in parallel is recommended.
The VREF pin can be driven with a DAC or other meansshown in Figure 13. This is useful in applications where thepeak input signal amplitude may vary. The input span ofthe ADC can then be adjusted to match the peak inputsignal, maximizing the signal-to-noise ratio. The filteringof the internal LTC1608 reference amplifier will limitthe bandwidth and settling time of this circuit. A settlingtime of 20ms should be allowed for after a referenceadjustment.
LTC1608
AIN+
ANALOG INPUT2V TO 2.7V
DIFFERENTIALAIN
–
VREF
REFCOMP
AGND
1608 F13
1
2
3
4
522µF
LTC14502V TO 2.7V
Figure 13. Driving VREF with a DAC
Figure 14a. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)1k
COM
MON
MOD
E RE
JECT
ION
(dB)
80
70
60
50
40
30
20
10
010k 100k
1608 G14a
1M
Differential Inputs
The LTC1608 has a unique differential sample-and-holdcircuit that allows rail-to-rail inputs. The ADC will alwaysconvert the difference of AIN
+ – AIN– independent of the
common mode voltage (see Figure 15a). The commonmode rejection holds up to extremely high frequencies(see Figure 14a). The only requirement is that both inputscan not exceed the AVDD or VSS power supply voltages.Integral nonlinearity errors (INL) and differential nonlin-earity errors (DNL) are independent of the common modevoltage, however, the bipolar zero error (BZE) will vary.The change in BZE is typically less than 0.1% of thecommon mode voltage. Dynamic performance is alsoaffected by the common mode voltage. THD will degradeas the inputs approach either power supply rail, from 96dBwith a common mode of 0V to 86dB with a common modeof 2.5V or –2.5V.
14
LTC1608
APPLICATIO S I FOR ATIO
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LTC1608
AIN+
AIN–
VREF0V TO5V±2.5V
REFCOMP
AGND
1608 F14b
1
2
3
4
522µF
ANALOG INPUT
–
+
Figure 14b. Selectable 0V to 5V or ±2.5V Input Range
Differential inputs allow greater flexibility for acceptingdifferent input ranges. Figure 14b shows a circuit thatconverts a 0V to 5V analog input signal with only anadditional buffer that is not in the signal path.
Full-Scale and Offset Adjustment
Figure 15a shows the ideal input/output characteristicsfor the LTC1608. The code transitions occur midwaybetween successive integer LSB values (i.e., –FS +0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,FS – 0.5LSB). The output is two’s complement binary with1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3µV.
In applications where absolute accuracy is important,offset and full-scale errors can be adjusted to zero. Offseterror must be adjusted before full-scale error. Figure 15bshows the extra components required for full-scale erroradjustment. Zero offset is achieved by adjusting the offsetapplied to the AIN
– input. For zero offset error, apply–38µV (i.e., –0.5LSB) at AIN
+ and adjust the offset at theAIN
– input by varying the output voltage of pin VOUTA fromthe LTC1662 until the output code flickers between 00000000 0000 0000 and 1111 1111 1111 1111. For full-scaleadjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs)is applied to AIN
+ and the output voltage of pin VOUTB isadjusted until the output code flickers between 0111 11111111 1110 and 0111 1111 1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-tion or high speed A/D converters. To obtain the best per-formance from the LTC1608, a printed circuit board with
ANALOGINPUT
1608 F15b
1
2
3
80.6k1%
OFFSET ADJ RANGE: ±0.125%FULL-SCALE ADJ RANGE: ±0.25%
R140.2k
4
5
0.1µF
5V
22µF
–5V
R31.5M
R2100Ω
+2.2µF
+
AIN+
AIN–
VREF
REFCOMP
AGND
LTC1608
LTC1662
CS/LDSCKSDIREF
VOUTAGNDVCC
VOUTB
Figure 15b. Offset and Full-Scale Adjust Circuit
1608 F15a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS – 1LSB–(FS – 1LSB) INPUT VOLTAGE (AIN
+ – AIN–)
OUTP
UT C
ODE
Figure 15a. LTC1608 Transfer Characteristics
ground plane is required. Layout should ensure that digitaland analog signal lines are separated as much as possible.Particular care should be taken not to run any digital trackalongside an analog signal track or underneath the ADC.Theanalog input should be screened by AGND.
An analog ground plane separate from the logic systemground should be established under and around the ADC.Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all otheranalog grounds should be connected to this single analogground point. The REFCOMP bypass capacitor and theDVDD bypass capacitor should also be connected to thisanalog ground plane. No other digital grounds should beconnected to this analog ground plane. Low impedanceanalog and digital power supply common returns areessential to low noise operation of the ADC and the foilwidth for these tracks should be as wide as possible. In
15
LTC1608
APPLICATIO S I FOR ATIO
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applications where the ADC data outputs and controlsignals are connected to a continuously active micropro-cessor bus, it is possible to get errors in the conversionresults. These errors are due to feedthrough from themicroprocessor to the successive approximation com-parator. The problem can be eliminated by forcing themicroprocessor into a WAIT state during conversion or byusing three-state buffers to isolate the ADC data bus. Thetraces connecting the pins and bypass capacitors must bekept short and should be made as wide as possible.
The LTC1608 has differential inputs to minimize noisecoupling. Common mode noise on the AIN
+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1608
will hold and convert the difference voltage between AIN+
and AIN–. The leads to AIN
+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this isnot possible, the AIN
+ and AIN– traces should be run side
by side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10µF or 22µFbypass capacitors should be used at the VDD and REFCOMPpins as shown in Figure 16 and in the Typical Applicationon the first page of this data sheet. Surface mount ceramiccapacitors such as Taiyo Yuden’s LMK325BJ106MN andLMK432BJ226MM provide excellent bypassing in a smallboard space. Alternatively, 10µF tantalum capacitors inparallel with 0.1µF ceramic capacitors can be used. By-pass capacitors must be located as close to the pins aspossible. The traces connecting the pins and the bypasscapacitors must be kept short and should be made as wideas possible.
EXAMPLE LAYOUT
Figures 17a, 17b, 17c, 17d and 17e show the schematicand layout of an evaluation board. The layout demon-strates the proper use of decoupling capacitors and groundplane with a 4-layer printed circuit board.
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: signal-to-noise raio (SNR) in frequency domain and histogram intime domain. The LTC1608 excels in both. Figure 19ademonstrates that the LTC1608 has an SNR of over 90dBin frequency domain. The noise in the time domain histo-gram is the transition noise associated with a high resolu-tion ADC which can be measured with a fixed DC signalapplied to the input of the ADC. The resulting output codesare collected over a large number of conversions. Theshape of the distribution of codes will give an indication ofthe magnitude of the transition noise. In Figure 18, thedistribution of output codes is shown for a DC input thathas been digitized 4096 times. The distribution is Gaussianand the RMS code transition noise is about 0.66LSB. Thiscorresponds to a noise level of 90.9dB relative to full scale.Adding to that the theoretical 98dB of quantization errorfor 16-bit ADC, the resultant corresponds to an SNR levelof 90.1dB which correlates very well to the frequencydomain measurements in Dynamic Performance section.
DYNAMIC PERFORMANCE
The LTC1608 has excellent high speed sampling capabil-ity. Fast fourier transform (FFT) test techniques are usedto test the ADC’s frequency response, distortions and
Figure 16. Power Supply Grounding Practice
1608 F16
AIN+
VSS OVDDDGNDAVDD
LTC1608 DIGITALSYSTEM
ANALOGINPUT
CIRCUITRY
AGND
5, 6, 7, 82 34 29
DVDD OGND
2810
1
REFCOMP
4
22µF
VREF
3
2.2µF
AIN–
10µF
36
10µF
AVDD
35
10µF 10µF+–
9
10µF
16
LTC1608
APPLICATIO S I FOR ATIO
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C4 1µFOVDD
AVDD1
AVDD2
VSS
SHDN
CS
CONV
RD
OVDD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
AIN+
AIN–
VREF
REFCOMP
AGND
AGND
AGND
AGND
DVDD
DGND
D15
D14
D13
D12
D11
D10
D9
D8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
U1 LTC1608
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
1
2
3
4
5
6
7
8
9
10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
U2 MC74HC574ADT
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
U3 74HC574
OVDD
AIN+
AIN–
C112.2µF
C1322µF
R610Ω
C10 22µF
5V
C1222µF
OVDD
C91µF
E4GND
E15V
E53V E2
–5V
E6GND 5V
JP1
C71µF
C61µF
C5 1µF
5V
C80.1µF
R210k
C10.1µF
E7GND
CLKMSB
J1CONN20
C2822µF
R310Ω
R151k
OVDD
J2CONVERTSTARTR5
10kJP3
OVDD
U5TC7SH08FUTE85L
R4 10kE3
VREF
C3 0.1µF
JP2
OVDD
U6TC7SH04F
LSB
–
+U4A
LT1469
4–5V
8
5VC21
0.1µFC27
100pF
C200.1µF
C25100pF
C24100pF
C261000pF
AIN+
(U1-1)
AIN–
(U1-2)
R15100Ω
R1610k
C1710pF
C1810pF
C15 10pF
C16 10pF
R8 402Ω
R9402Ω R12
50ΩR1450Ω
R1150Ω
R1350Ω
1
3
2
–
+
U4BLT1469
7
6
5 C23100pF
C22100pF
C191000pF
R1050Ω
R1710k
J3AIN
+
J4AIN
–
C141000pF
R750Ω
+
+ +
Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic
17
LTC1608
APPLICATIO S I FOR ATIO
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–5 –4 –3 –2 –1 0 1 2 3 4 5
COUN
T
2500
2000
1500
1000
500
0
1608 F18
Figure 18. Histogram for 4096 Conversions
ANALOG GROUND PLANE DIGITAL GROUND PLANE ANALOG GROUND PLANE DIGITAL GROUND PLANE
Figure 17b. Suggested Evaluation Circuit Board.Component Side Silkscreen and Signal Traces
Figure 17c. Suggested Evaluation Circuit Board.Bottom Side Showing Signal Traces
Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1Showing Separate Analog and Digital Ground Planes
Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2Showing Separate Analog and Digital Ground Planes
noise at the rated throughput. By applying a low distortionsine wave and analyzing the digital output using an FFTalgorithm, the ADC’s spectral content can be examined forfrequencies outside the fundamental. Figures 19a and 19bshow typical LTC1608 FFT plots.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is theratio between the RMS amplitude of the fundamentalinput frequency to the RMS amplitude of all other fre-quency components at the A/D output. The output is bandlimited to frequencies from above DC and below half thesampling frequency. Figure 19a shows a typical spectralcontent with a 500kHz sampling rate and a 3kHz input.
18
LTC1608
APPLICATIO S I FOR ATIO
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The dynamic performance is excellent for input frequen-cies up to and beyond the Nyquist limit of 250kHz.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement ofthe resolution of an ADC and is directly related to theS/(N + D) by the equation:
ENOB = [S/(N + D) – 1.76]/6.02
where ENOB is the effective number of bits of resolutionand S/(N + D) is expressed in dB. At the maximumsampling rate of 500kHz, the LTC1608 maintains above 14bits up to the Nyquist input frequency of 250kHz (refer toFigure 20).
FREQUENCY (kHz)0
–40
–20
0
200
1608 F19b
–60
–80
50 100 150 250
–100
–120
–140
AMPL
ITUD
E (d
B)
fSAMPLE = 500kHzfIN = 98.754kHzSINAD = 86.7dBTHD = –92.6dB
Figure 19b. Even with Inputs at 100kHz, theLTC1608’s Dynamic Linearity Remains Robust
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMSsum of all harmonics of the input signal to the fundamentalitself. The out-of-band harmonics alias into the frequencyband between DC and half the sampling frequency. THD isexpressed as:
THD LogV V V Vn
V= + + +
202 3 4
1
2 2 2 2...
where V1 is the RMS amplitude of the fundamental fre-quency and V2 through Vn are the amplitudes of thesecond through nth harmonics. THD vs Input Frequency isshown in Figure 21. The LTC1608 has good distortionperformance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectralcomponent, the ADC transfer function nonlinearity canproduce intermodulation distortion (IMD) in addition toTHD. IMD is the change in one sinusoidal input caused bythe presence of another sinusoidal input at a differentfrequency.
If two pure sine waves of frequencies fa and fb are appliedto the ADC input, nonlinearities in the ADC transferfunction can create distortion products at the sum anddifference frequencies of mfa ±nfb, where m and n = 0,1, 2, 3, etc. For example, the 2nd order IMD terms include
FREQUENCY (kHz)0
–40
–20
0
200
1608 F19a
–60
–80
50 100 150 250
–100
–120
–140
AMPL
ITUD
E (d
B)
fSAMPLE = 500kHzfIN = 2.807kHzSINAD = 88.9dBTHD = –98dB
Figure 19a. This FFT of the LTC1608’s Conversion of aFull-Scale 3kHz Sine Wave Shows Outstanding Responsewith a Very Low Noise Floor When Sampling at 500ksps
FREQUENCY (Hz)1k
EFFE
CTIV
E BI
TS SINAD (dB)
16
15
14
13
12
11
10
9
8
98
92
86
80
74
68
62
56
5010k 100k 1M
1608 F20
Figure 20. Effective Bits and Signal/(Noise + Distortion)vs Input Frequency
19
LTC1608
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 22. Intermodulation Distortion Plot
FREQUENCY (kHz)0
–40
–20
0
200
1608 F22
–60
–80
50 100 150 250
–100
–120
–140
AMPL
ITUD
E (d
B)
fSAMPLE = 500kHzfIN1 = 96.56kHzfIN2 = 99.98kHz
(fa ± fb). If the two input sine waves are equal inmagnitude, the value (in decibels) of the 2nd order IMDproducts can be expressed by the following formula:
IMD fa fb LogAmplitude±( ) = ±
20 at (fa fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-tral component excluding the input signal and DC. Thisvalue is expressed in decibels relative to the RMS value ofa full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at whichthe amplitude of the reconstructed fundamental isreduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at whichthe S/(N + D) has dropped to 84dB (13.66 effective bits).The LTC1608 has been designed to optimize input band-width, allowing the ADC to undersample input signals withfrequencies above the converter’s Nyquist Frequency. Thenoise floor stays very low at high frequencies; S/(N + D)becomes dominated by distortion at frequencies farbeyond Nyquist.
APPLICATIO S I FOR ATIO
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INPUT FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
AMPL
ITUD
E (d
B BE
LOW
THE
FUN
DAM
ENTA
L)
1608 F21
1k 10k 100k 1M
THD3RD2ND
Figure 21. Distortion vs Input Frequency
U
PACKAGE DESCRIPTIOG Package
36-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)
G36 SSOP 0501
.13 – .22(.005 – .009)
0° – 8°
.55 – .95(.022 – .037)
5.20 – 5.38**(.205 – .212)
7.65 – 7.90(.301 – .311)
1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 1813
12.67 – 12.93*(.499 – .509)
2526 22 21 20 192324272829303132333435361.73 – 1.99(.068 – .078)
.05 – .21(.002 – .008)
.65(.0256)
BSC.25 – .38
(.010 – .015)
MILLIMETERS(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
20
LTC1608
1608fs, sn1608 LT/TP 0601 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1410 12-Bit, 1.25Msps, ±5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation
LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD
LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V
LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604 16-Bit, 333ksps, ±5V ADC 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606 16-Bit, 250ksps, Single 5V ADC ±10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
SAMPLING ADCs
D15 TO D0
VSSAGNDAGNDAGNDAGND
REFCOMP
4.375V
11 TO 26
1608 TA03
CH7+
+
+
+
CH0+ 16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
LTC1391
LTC1391
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V+
D
V–
DOUT
DIN
CS
CLK
GND
CH7–
CH0–1µF
5V
DIN
CS
CLK
–5V
–5V
10Ω2.2µF 10µF 5V 10µF 5V
10
34
935363
4
10µF
–5V
1µF
10µF
3000pF
3000pF
5
1
22µF
AIN+
VREF AVDD AVDD DVDD DGND
OVDD
OGND 28
µPCONTROLLINES
5V OR3V
10µF
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
AIN–
2
6 7 8
1µF
5V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V+
D
V–
DOUT
DIN
CS
CLK
GND
16-BITSAMPLING
ADC
+
+
+ + +
1.75X2.5VREF
CONTROLLOGICAND
TIMING
OUTPUTBUFFERS 16-BIT
PARALLELBUS
7.5k
LTC1608
B15 TO B0
+29
µPCONTROLLINES
+
–
DACsPART NUMBER DESCRIPTION COMMENTS
LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597/LTC1591 16-Bit/14-Bit Parallel, Multiplying DACs ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial VOUT DAC Low Power, Low Gritch, 4-Quadrant Multiplication
Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com
TYPICAL APPLICATIO
U