ltc3731h - 3-phase, 600khz, synchronous buck switching … · 2020-02-01 · n 3-phase current mode...

LTC3731H

3731Hfb

Typical applicaTion

FeaTures DescripTion

3-Phase, 600kHz, Synchronous Buck Switching

Regulator Controller

The LTC®3731H is a PolyPhase® synchronous step-down switching regulator controller that drives all N-channel external power MOSFET stages in a phase-lockable fixed frequency architecture. The LTC3731H is rated for operation up to 140°C junction temperature. The 3-phase controller drives its output stages with 120° phase separation at frequencies up to 680kHz per phase to minimize the RMS current losses in both the input and output filter capacitors. The 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. Light load efficiency is optimized by using a choice of output Stage Shedding or Burst Mode operation.

The precision reference supports output voltages from 0.6V to 6V. Current foldback provides protection for the external MOSFETs under short-circuit or overload condi-tions. Please refer to the LTC3731 data sheet for 0°C to 70°C and –40°C to 85°C rated versions.L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks and Stage Shedding is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6462525, 6304066, 5705919.

Figure 1. High Current Triple Phase Step-Down Converter

applicaTions

n 3-Phase Current Mode Controller with Onboard MOSFET Drivers

n ±5% Output Current Matching Optimizes Thermal Performance and Size of Inductors and MOSFETs

n ±2% VREF Accuracy Over Temperature Up to 140°Cn Reduced Power Supply Induced Noisen ±10% Power Good Output Indicatorn 225kHz to 680kHz Per Phase, PLL, Fixed Frequencyn PWM, Stage Shedding™ or Burst Mode® Operationn OPTI-LOOP® Compensation Minimizes COUTn Adjustable Soft-Start Current Rampingn Short-Circuit Shutdown Timer with Defeat Optionn Overvoltage Soft Latchn Adjustable Undervoltage Lockout Thresholdn Selectable Phase Output for Up to 12-Phase

Operationn Available in 36-Pin Narrow (0.209") SSOP and

5mm × 5mm QFN Packages

n Automotive and Industrial Power Suppliesn High Output Current DC/DC Power Supplies

VIN

0.003Ω0.8µH 22µF35V

0.003Ω0.8µHVIN

0.003Ω

COUT470µF4V

VOUT1.35V55A

VIN5V TO 28V

0.8µHVIN

3731H F01

TG1VCC

0.1µF

SW3 SW2 SW1

SW1

BG1

SENSE1+

SENSE1–

BOOST1BOOST2BOOST3

TG2

SW2

BG2

PGOODPLLIN

PLLFLTR

ITH

0.01µF

680pF

5k

OPTIONAL SYNC INPOWER GOOD INDICATOR

RUN/SS

SGNDEAIN

PGNDUVADJ

SENSE2+

SENSE2–

TG3

SW3

BG3

SENSE3+

SENSE3–

+10µF

VCC4.5V TO 7V

+

LTC3731H

36k

12k

7.5k100pF

6.04k

Efficiency vs IOUT

EFFI

CIEN

CY (%

)

0.1LOAD CURRENT (A)

100

90

80

70

60

50

40

30

20

10

01 10 100

3731H F01b

VIN = 8VVOUT = 1.5V

VFCB = OPEN

VFCB = 5VVFCB = 0V

LTC3731H

3731Hfb

absoluTe MaxiMuM raTings

Topside Driver Voltages (BOOSTN) ............ 38V to –0.3VSwitch Voltage (SWN) ................................... 32V to –5VBoosted Driver Voltage (BOOSTN – SWN) .... 7V to –0.3VPeak Output Current <1ms (TGN, BGN) .......................5ASupply Voltages (VCC, VDR), PGOOD Pin Voltage ................................................... 7V to –0.3VRUN/SS, PLLFLTR, PLLIN, UVADJ, FCB Voltages ..............................................VCC to –0.3V

(Note 1)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TOP VIEW

G PACKAGE36-LEAD PLASTIC SSOP

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

VCC

PLLIN

PLLFLTR

FCB

NC

NC

NC

EAIN

SGND

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

SENSE3+

RUN/SS

ITH

UVADJ

CLKOUT

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

VDR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND

TJMAX = 140°C, θJA = 70°C/W, θJC = 25°C/W PINS 5 AND 6 CAN BE GROUNDED OR NC

PIN 7 MUST BE LEFT AS NC

32

33SGND

31 30 29 28 27 26 25

9 10 11 12

TOP VIEW

UH PACKAGE32-LEAD (5mm 5mm) PLASTIC QFN

13 14 15 16

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1NC

NC

EAIN

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

BOOST2

TG2

SW2

VCC

BG1

PGND

BG2

BG3

NC FCB

PLLF

LTR

PLLI

N

CLKO

UT

BOOS

T1

TG1

SW1

SENS

E3+

RUN/

SS I TH

UVAD

J

PHAS

MD/

PG

BOOS

T3 TG3

SW3

TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W

EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB PINS 1, 2 AND 32 MUST BE LEFT AS NC

pin conFiguraTion

orDer inForMaTionLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3731HG#PBF LTC3731HG#TRPBF LTC3731HG 36-Lead Plastic SSOP –40°C to 140°C

LTC3731HUH#PBF LTC3731HUH#TRPBF 3731 32-Lead (5mm × 5mm) Plastic QFN –40°C to 140°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

SENSE+, SENSE– Voltages ........................ 5.5V to –0.3VITH Voltage ............................................... 2.4V to –0.3VOperating Junction Temperature Range (Note 2) .................. –40°C to 140°CStorage Temperature Range .................. –65°C to 150°CLead Temperature G Package (Soldering, 10sec) .. 300°C

LTC3731H

3731Hfb

elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VRUN/SS = 5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

VREGULATED Regulated Voltage at EAIN VITH = 1.2V (Note 3)

l

0.594 0.590

0.600 0.600

0.606 0.614

V V

VSENSEMAX Maximum Current Sense Threshold VEAIN = 0.5V, VITH Open, VSENSE1

–, VSENSE2–, VSENSE3

– = 0.6V, 1.8V

l

65 60

75 75

85 90

mV mV

IMATCH Maximum Current Threshold Match Worst-Case Error at VSENSEMAX –5 5 %

VLOADREG Output Voltage Load Regulation (Note 3) Measured in Servo Loop, ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop, ∆ITH Voltage = 1.2V to 2V

l

l

0.1

–0.1

0.7

–0.7

% %

VREFLNREG Output Voltage Line Regulation VCC = 4.5V to 7V 0.03 %/V

gm Transconductance Amplifier gm ITH = 1.2V, Sink/Source 25µA (Note 3) l 3 5 7 mmho

gmOL Transconductance Amplifier GBW ITH = 1.2V (gm • ZL, ZL = Series 1k – 100kΩ – 1nF) 3 MHz

VFCB Forced Continuous Threshold l 0.54 0.60 0.66 V

IFCB FCB Bias Current VFCB = 0.65V 0.2 0.7 µA

VBINHIBIT Burst Inhibit Threshold Measured at FCB Pin VCC – 1.5 VCC – 0.7 VCC – 0.3 V

UVR Undervoltage RUN/SS Reset VCC Lowered Until the RUN/SS Pin is Pulled Low 3.3 3.8 4.5 V

UVADJ Undervoltage Lockout Threshold 1.13 1.18 1.23 V

IUVADJ Undervoltage Bias Current At UVADJ Threshold 0.2 50 nA

IQ Input DC Supply Current Normal Mode Shutdown

(Note 4) VCC = 5V VRUN/SS = 0V

2.3 50

3.5 100

mA µA

IRUN/SS Soft-Start Charge Current VRUN/SS = 1.9V –0.8 –1.5 –2.5 µA

VRUN/SS RUN/SS Pin ON Threshold VRUN/SS, Ramping Positive 1 1.5 1.9 V

VRUN/SSARM RUN/SS Pin Arming Threshold VRUN/SS, Ramping Positive Until Short-Circuit Latch-Off is Armed

3.8 4.5 V

VRUN/SSLO RUN/SS Pin Latch-Off Threshold VRUN/SS, Ramping Negative 3.2 V

ISCL RUN/SS Discharge Current Soft-Short Condition VEAIN = 0.375V, VRUN/SS = 4.5V –5 –1.5 µA

ISDLHO Shutdown Latch Disable Current VEAIN = 0.375V, VRUN/SS = 4.5V 1.5 5 µA

ISENSE SENSE Pins Source Current SENSE1+, SENSE1–, SENSE2+, SENSE2–, SENSE3+, SENSE3– All Equal 1.2V; Current at Each Pin

13 20 µA

DFMAX Maximum Duty Factor In Dropout, VSENSEMAX ≤ 30mV 95 98.5 %

TG tR, tF Top Gate Rise Time Top Gate Fall Time

CLOAD = 3300pF CLOAD = 3300pF

30 40

90 90

ns ns

BG tR, tF Bottom Gate Rise Time Bottom Gate Fall Time

CLOAD = 3300pF CLOAD = 3300pF

30 20

90 90

ns ns

TG/BG t1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time

All Controllers, CLOAD = 3300pF Each Driver 50 ns

BG/TG t2D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time

All Controllers, CLOAD = 3300pF Each Driver 60 ns

tON(MIN) Minimum On-Time Tested with a Square Wave (Note 5) 110 ns

LTC3731H

3731Hfb

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The LTC3731H is guaranteed to meet specifications over the –40°C to 140°C operating junction temperature range. Note that the maximum ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.Junction temperature (TJ) is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3731HG: TJ = TA + (PD • 70°C/W) LTC3731HG: TJ = TCASE + (PD • 25°C/W) LTC3731HUH: TJ = TA + (PD • 34°C/W)High junction temperatures degrade operating lifetimes. Operating lifetime at junction temperatures greater than 125°C is derated to 1000 hours. The LTC3731H is tested under pulsed load conditions such that TJ ≈ TA.

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Good Output Indication

VPGL PGOOD Voltage Output Low IPGOOD = 2mA, G Package IPGOOD = 1.6mA, UH Package

0.1 0.5

0.3 1

V V

IPGOOD PGOOD Output Leakage VPGOOD = 5V 1 µA

VPGTHNEG VPGTHPOS

PGOOD Trip Thresholds VEAIN Ramping Negative VEAIN Ramping Positive

VEAIN with Respect to Set Output Voltage, PGOOD Goes Low After VUVDLY Delay

–7 7

–10 10

–13 13

% %

VPGDLY Power Good Fault Report Delay After VEAIN is Forced Outside the PGOOD Thresholds 100 150 µs

Oscillator and Phase-Locked Loop

fNOM Nominal Frequency VPLLFLTR = 1.2V 360 400 440 kHz

fLOW Lowest Frequency VPLLFLTR = 0V 190 225 260 kHz

fHIGH Highest Frequency VPLLFLTR = 2.4V 600 680 750 kHz

VPLLTH PLLIN Input Threshold Minimum Pulse Width > 100ns 1 V

RPLLIN PLLIN Input Resistance 50 kΩ

IPLLFLTR Phase Detector Output Current Sinking Capability Sourcing Capability

fPLLIN < fOSC fPLLIN > fOSC

20 20

µA µA

RRELPHS Controller 2-Controller 1 Phase Controller 3-Controller 1 Phase

120 240

Deg Deg

CLKOUT Controller 1 TG to CLKOUT Phase PHASMD = 0V PHASMD = 5V

30 60

Deg Deg

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VRUN/SS = 5V unless otherwise noted.

Note 3: The IC is tested in a feedback loop that servoes the error amplifier output voltage to its midrange point (VITH = 1.2V).Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information.Note 5: The minimum on-time condition corresponds to an inductor peak-to-peak ripple current of ≥40% of IMAX (see minimum on-time considerations in the Applications Information Section).Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Overtemperature protection becomes active at a junction temperature greater than the maximum operating temperature. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

LTC3731H

3731Hfb

Typical perForMance characTerisTics

Reference Voltage vs Temperature

Error Amplifier gm vs Temperature

Maximum ISENSE Threshold vs Temperature

Oscillator Frequency vs Temperature Operating Frequency vs VPLLFLTR

Undervoltage Reset Voltage vs Temperature

Efficiency vs IOUT (Figure 14) Efficiency vs VIN (Figure 14) Efficiency vs Frequency (Figure 14)

EFFI

CIEN

CY (%

)

0.1LOAD CURRENT (A)

100

90

80

70

60

50

40

30

20

10

01 10 100

3731H G01

VIN = 8VVOUT = 1.5V

VFCB = OPEN

VFCB = 5VVFCB = 0V

VIN (V)0

EFFI

CIEN

CY (%

)

100

95

90

85

80

75

70

65

60

55

5020

3731H G02

5 10 15 25

IL = 45A

IL = 15A

VOUT = 1.5Vf = 225kHz

FREQUENCY (kHz)200

EFFI

CIEN

CY (%

)

100

95

90

85

80

75600

3731H G03

300 400 500

ILOAD = 20AVOUT = 1.5V

VIN = 20V

VIN = 12V VIN = 8V

VIN = 5V

TEMPERATURE (°C)–50

REFE

RENC

E VO

LTAG

E (m

V)

3731H G04

0 25 50 75

610

605

600

595

590–25 150125100

TEMPERATURE (°C)

4.0

ERRO

R AM

PLIF

IER

g m(m

mho

)

4.5

5.5

6.0

3731H G05

5.0

–50 0 25 50 75–25 150125100 –50 0 25 50 75–25 150125100TEMPERATURE (°C)

3731H G06

MAX

IMUM

I SEN

SE T

HRES

HOLD

(mV)

85

80

75

70

65

VO = 1.75V

VO = 0.6V

–50 0 25 50 75–25 150125100TEMPERATURE (°C)

FREQ

UENC

Y (k

Hz)

700

600

500

400

300

200

100

0

3731H G07

VPLLFLTR = 2.4V

VPLLFLTR = 1.2V

VPLLFLTR = 0V

VPLLFLTR = 5V

PLLFLTR PIN VOLTAGE (V)0

OPER

ATIN

G FR

EQUE

NCY

(kHz

)

700

600

500

400

300

2000.5 1 1.5 2 2.5

3731H G08

–50 0 25 50 75–25 150125100TEMPERATURE (°C)

3731H G09

0

UNDE

R VO

LTAG

E RE

SET

(V)

1

3

4

5

2

LTC3731H

3731Hfb


Maximum ISENSE vs VRUN/SS

Maximum Current Sense Threshold vs Duty Factor Peak Current Threshold vs VITH

Percentage of Nominal Output vs Peak ISENSE (Foldback)

Maximum Duty Factor vs Temperature ISENSE Pin Current vs VOUT

Short-Circuit Arming and Latchoff vs Temperature Supply Current vs Temperature

RUN/SS Pull-Up Current vs Temperature

–50 0 25 50 75–25 1501251000

RUN/

SS P

IN V

OLTA

GE (V

)

1

3

4

5

2

TEMPERATURE (°C)3731H G10

ARMING

LATCHOFF

–50 0 25 50 75–25 1501251000

SUPP

LY C

URRE

NT (m

A) SHUTDOW

N CURRENT (µA)

0.4

2.0

1.6

2.4

2.8

1.2

0.8


100

80

60

40

20

0

VCC = 5V

–50 0 25 50 75–25 1501251000

RUN/

SS P

ULLU

P CU

RREN

T (µ

A)

0.5

1.5

2.0

3.0

2.5

1.0


VRUN/SS = 1.9V

VRUN/SS VOLTAGE (V)0

MAX

IMUM

I SEN

SE (m

V)

80

70

60

50

40

30

20

10

04

3731H G13

1 2 3 5 6DUTY FACTOR (%)

00

I SEN

SEVO

LTAG

E (m

V)

25

50

75

20 40 60 80

3731H G14

100VITH (V)

0

I SEN

SE V

OLTA

GE T

HRES

HOLD

(mV)

75

60

45

30

15

0

–150.6 1.2 1.8 2.4

3731H G15

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)0

PEAK

I SEN

SE V

OLTA

GE (m

V)

80

70

60

50

40

30

20

10

080

3731H G16

2010 30 50 70 9040 60 100 –50 0 25 50 75–25 15012510090

MAX

IMUM

DUT

Y FA

CTOR

(%)

92

96

98

100

94


VPLLFLTR = 0V

VOUT (V)0

I SEN

SE P

IN C

URRE

NT (µ

A)

40

30

20

10

0

–10

–20

–30

3731H G18

2 51 3 4

LTC3731H

3731Hfb


Continuous Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

Transient Load Current Response: 0 Amp to 50 Amp (Circuit of Figure 14)

Shed Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

Burst Mode at 1 Amp, Light Load Current (Circuit of Figure 14)

3731H G20

VIN = 12VVOUT = 1.5VVFCB = VCCFREQUENCY = 225kHz

VOUTAC, 20mV/DIV

VSW110V/DIV

VSW210V/DIV

VSW310V/DIV

4µs/DIV

3731H G21

VIN = 12VVOUT = 1.5VVFCB = OPENFREQUENCY = 225kHz

VOUTAC, 20mV/DIV

VSW110V/DIV

VSW210V/DIV

VSW310V/DIV

4µs/DIV

3731H G22

VIN = 12VVOUT = 1.5VVFCB = 0VFREQUENCY = 225kHz

VOUTAC, 20mV/DIV

VSW110V/DIV

VSW210V/DIV

VSW310V/DIV

4µs/DIV

3731H G23

VIN = 12VVOUT = 1.5VVFCB = VCCFREQUENCY = 225kHz

VOUTAC, 20mV/DIV

ILOAD20A/DIV

20µs/DIV

LTC3731H

3731Hfb

pin FuncTionsBG1 to BG3: High Current Gate Drives for Bottom N-Channel MOSFETs. Voltage swing at these pins is from ground to VCC.

BOOST1 to BOOST3: Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source, are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from boost source voltage (typically VCC) to this boost source voltage + VIN (where VIN is the external MOSFET supply rail).

CLKOUT: Output clock signal available to synchronize other controller ICs for additional MOSFET stages/phases.

EAIN: This is the input to the error amplifier that com-pares the feedback voltage to the internal 0.6V reference voltage.

FCB: Forced Continuous Control Input. The voltage ap-plied to this pin sets the operating mode of the controller. The forced continuous current mode is active when the applied voltage is less than 0.6V. Burst Mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the VCC pin. (Do not apply voltage directly to this pin prior to the application of voltage on the VCC pin.)

PGOOD: This open-drain output is pulled low when the output voltage has been outside the PGOOD tolerance window for the VPGDLY delay of approximately 100µs.

ITH: Error Amplifier Output and Switching Regulator Com-pensation Point. All three current comparator’s thresholds increase with this control voltage.

PGND: Driver Power Ground. This pin connects directly to the sources of the bottom N-channel external MOSFETs and the (–) terminals of CIN.

PHASMD: This pin determines the phase shift between the first controller’s rising TG signal and the rising edge of the CLKOUT signal. Logic 0 yields 30 degrees and logic 1 yields 60 degrees.

PLLIN: Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the PLLIN signal.

PLLFLTR: The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. (Do not apply voltage directly to this pin prior to the application of voltage on the VCC pin.)

RUN/SS: Combination of Soft-Start, Run Control Input and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. A minimum value of 0.01µF is recommended on this pin.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, SENSE3–: The Inputs to Each Differential Current Com-parator. The ITH pin voltage and built-in offsets between SENSE– and SENSE+ pins, in conjunction with RSENSE, set the current trip threshold level.

SGND: Signal Ground. This pin must be routed sepa-rately under the IC to the PGND pin and then to the main ground plane. The exposed pad in the UH package must be soldered to PCB ground for electrical contact and rated thermal performance.

SW1 to SW3: Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN (where VIN is the external MOSFET supply rail).

TG1 to TG3: High Current Gate Drives for Top N-channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to the boost voltage source super-imposed on the switch node voltage SW.

UVADJ: Input to the Undervoltage Shutdown Compara-tor. When the applied input voltage is less than 1.2V, this comparator turns off the output MOSFET driver stages and discharges the RUN/SS capacitor.

VCC: Main Supply Pin. Because this pin supplies both the controller circuit power as well as the high power pulses supplied to drive the external MOSFET gates, this pin needs to be very carefully and closely decoupled to the IC’s PGND pin.

VDR: Supplies power to the bottom gate drivers only. This pin needs to be very carefully and closely decoupled to the IC’s PGND pin.

LTC3731H

3731Hfb

FuncTional DiagraM

Figure 2

SWITCHLOGIC

CLK2

CLK1

SW

SHDN

B0.55V

3mV

FCB

TOP

BOOST

TG CB

CIN

DB

PGND

BOTBG

VCC

VCC (VDR)

VIN

+

VOUT

3731H F02

DROPOUTDET

RUNSOFT-START

BOT

FORCE BOTS

R

Q

Q

CLK3OSCILLATOR

PLLFLTR

50k

0.600V

0.660V

1.5µA

6V

RSTSHDN

FCB

RUN/SS

CSS

5(VFB)

5(VFB)

0.86V

SLOPECOMP

+

–

SENSE+VCC

36k

54k54k

2.4V

SSCLAMP

I1

SGND

0.600V

INTERNALSUPPLY

VCC

CCC

VCC

PHASE DETPLLIN

DUPLICATE FOR SECOND AND THIRD CONTROLLER CHANNELS

+– + –

RSENSE

L

COUT

+

FIN

RLP

CLP

+

–

+

–

+

–

EAIN VFB

R1

OV

ITH

CC

RC

PGOOD

FCB

+

–

–

+

+

1.2VVREF

UV RESET

VCC

EAIN

0.66V

RSLATCH

FCB0.6V

0.54VPROTECTION

PHASMD

CLKOUT

+

–I2

SENSE–36k

EA

1.2V

UVADJ

+

–

SHED

R2

100µsDELAY

LTC3731H

03731Hfb

operaTionMain Control Loop

The IC uses a constant frequency, current mode step-down architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets each RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of output voltage feedback signal through the external resistive divider and is compared to the internal reference voltage. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until each inductor’s average current matches one third of the new load current (assuming all three current sensing resistors are equal). In Burst Mode operation and stage shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating bootstrap capacitor CB, which is normally recharged through an external Schottky diode when the top FET is turned off. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow CB to recharge.

The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.5µA current source to charge soft-start capacitor CSS. When CSS reaches 1.5V, the main control loop is enabled and the internally buffered ITH voltage is clamped but allowed to ramp as the voltage on CSS continues to ramp. This “soft-start” clamping prevents abrupt current from being drawn from the input power source. When the RUN/SS pin is low, all functions are kept in a controlled state. The RUN/SS pin is pulled low when the supply input voltage is below 4V, when the undervoltage lockout pin (UVADJ) is below 1.2V, or when the IC die temperature rises above 160°C.

Low Current Operation

The FCB pin is a logic input to select between three modes of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchro-nous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB pin is below VCC – 1.5V but greater than 0.6V, the controller performs as a Burst Mode switching regulator. Burst Mode operation sets a minimum output current level before turning off the top switch and turns off the synchronous MOSFET(s) when the inductor current goes negative. This combination of requirements will, at low current, force the ITH pin below a voltage threshold that will temporarily shut off both output MOSFETs until the output voltage drops slightly. There is a burst compara-tor having 60mV of hysteresis tied to the ITH pin. This hysteresis results in output signals to the MOSFETs that turn them on for several cycles, followed by a variable “sleep” interval depending upon the load current. The resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the VCC pin, Burst Mode opera-tion is disabled and the forced minimum inductor current requirement is removed. This provides constant frequency, discontinuous current operation over the widest possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the phase 1 controller alone is active in discontinuous current mode. This “stage shedding” opti-mizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This stage shedding operation is not as efficient as Burst Mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions.

(Refer to Functional Diagram)

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C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, the controller will cause current to flow back into the input filter capacitor. If large enough, the input capacitor will prevent the input supply from boosting to unacceptably high levels; see CIN/COUT selection in the Applications Information section.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be synchronized to an external source using the PLLIN pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator, which operates over a 225kHz to 680kHz range corresponding to a voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal. When no frequency information is supplied to the PLLIN pin, PLLFLTR goes low, forcing the oscillator to minimum frequency. A DC source can be applied to the PLLFLTR pin to externally set the desired operating frequency. A discharge current of approximately 20µA will be present at the pin with no PLLIN input signal.

Input capacitance ESR requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 3-stage, single output voltage implementation can reduce input path power loss by 90%.

Power Good

The PGOOD pin is connected to the drain of an internal N-channel MOSFET. The MOSFET is turned on once an internal delay of about 100µs has elapsed and the output voltage has been away from its nominal value by greater than 10%. If the output returns to normal prior to the delay timeout, the timer is reset. There is no delay time for the rising of the PGOOD output once the output voltage is within the ±10% “window.”

Phase Mode

The PHASMD pin determines the phase shift between the rising edge of the TG1 output and the rising edge of the CLKOUT signal. Grounding the pin will result in 30 degrees phase shift and tying the pin to VCC will result in 60 degrees. These phase shift values enable extension to 6- and 12-phase systems. The PGOOD function above and the PHASMD function are tied to a common pin in the UH package.

Undervoltage Shutdown Adjust

The voltage applied to the UVADJ pin is compared to the internal 1.2V reference to have an externally programmable undervoltage shutdown. The RUN/SS pin is internally held low until the voltage applied to the UVADJ pin exceeds the 1.2V threshold.

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the RUN/SS pin, to charge up the output capacitors and provide full load current, the RUN/SS capacitor is then used as a short-circuit timeout circuit. If the output voltage falls to less than 70% of its nominal output voltage, the RUN/SS capacitor begins discharg-ing, assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing >5µA at a compliance of 3.8V to the RUN/SS pin. This additional current shortens the soft-start period but prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held above the (70%)(0.6V) or 0.42V level even when the actual output voltage is low. Up to 100µA of input current can safely be accommodated by the RUN/SS pin.

operaTion (Refer to Functional Diagram)

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operaTion (Refer to Functional Diagram)

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage (VCC) is allowed to fall below approximately 4V. The capacitor on the RUN/SS pin will be discharged until the short-circuit arming latch is disarmed. The RUN/SS capacitor will attempt to cycle through a normal soft-start

ramp up after the VCC supply rises above 4V. This circuit prevents power supply latchoff in the event of input power switching break-before-make situations. The PGOOD pin is held low during start-up until the RUN/SS capacitor rises above the short-circuit latchoff arming threshold of approximately 3.8V.

applicaTions inForMaTionThe basic application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. Once the inductors and op-erating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs and Schottky diodes are selected. Finally, CIN and COUT are selected according to the voltage ripple require-ments. The circuit shown in Figure 1 can be configured for operation up to a MOSFET supply voltage of 28V (limited by the external MOSFETs and possibly the mini-mum on-time).

Operating Frequency

The IC uses a constant frequency, phase-lockable ar-chitecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to the Phase-Locked Loop and Frequency Synchronization section for additional information.

A graph for the voltage applied to the PLLFLTR pin versus frequency is given in Figure 3. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 680kHz.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-related in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addi-tion to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency.

The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT:

∆I

VfL

VVL

OUT OUT

IN= −

1

where f is the individual output stage operating frequency.

Figure 3. Operating Frequency vs VPLLFLTR

PLLFLTR PIN VOLTAGE (V)0

OPER

ATIN

G FR

EQUE

NCY

(kHz

)

3731H F03

700

600

500

400

300

2000.5 1 1.5 2 2.5

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applicaTions inForMaTionIn a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77.

Figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 4, the zero output ripple current is obtained when:

VV

kN

where k NOUT

IN= = 1 2 1, , ..., –

So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In appli-cations having a highly varying input voltage, additional phases will produce the best results.

Accepting larger values of ∆IL allows the use of low in-ductances but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the input and output voltages, and the inductance.

Inductor Core Selection

Once the value for L1 to L3 is determined, the type of induc-tor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals cancon-centrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that induc-tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space effi-cient, especially when you can use several layers of wire. Because they lack a bobbin, mounting is more difficult. However, designs for surface mount are available which do not increase the height significantly.

Power MOSFET and D1, D2, D3 Selection

At least two external power MOSFETs must be selected for each of the three output sections: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top

Figure 4. Normalized Peak Output Current vs Duty Factor [IRMS = 0.3(IO(P-P)]

DUTY FACTOR (VOUT/VIN)0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

3731H F04

6-PHASE12-PHASE

4-PHASE3-PHASE2-PHASE1-PHASE

∆I O

(P-P

)V O

/fL

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MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs’ on-resistance is normally less important for overall efficiency than its input capaci-tance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators.

The peak-to-peak MOSFET gate drive levels are set by the voltage, VCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-resistance RDS(ON), input capacitance, input voltage and maximum output current.

MOSFET input capacitance is a combination of sev-eral components but can be taken from the typical “gate charge” curve included on most data sheets (Figure 5). The curve is generated by forcing a constant input cur-rent into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain

applicaTions inForMaTionvoltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important se-lection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included.

When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by:

Main SwitchDuty CycleVV

Synchronous SwitchDuty CycleV V

V

OUT

IN

IN OUT

IN

=

=

–

The power dissipation for the main and synchronous MOSFETs at maximum output current are given by:

PVV

IN

R

VI

NR C

V V Vf

PV V

VI

NR

MAINOUT

IN

MAXDS ON

INMAX

DR MILLER

CC TH IL TH IL

SYNCIN OUT

IN

MAXDS ON

=

+( ) +

( )( )

+

( )

=

+( )

2

2

2

1

21 1

1

d

d

( )

( ) ( )

( )

•

–

–

where N is the number of output stages, d is the tem-perature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(IL) is the data sheet speci-fied typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above.

Figure 5. Gate Charge Characteristic

+–

VDS

VIN

3731H F05

VGS

MILLER EFFECT

QIN

a b

CMILLER = (QB – QA)/VDS

VGSV

+

–

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applicaTions inForMaTionBoth MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 12V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 12V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period.

The term (1 + d ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs.

The Schottky diodes (D1 to D3 in Figure 1) conduct during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bot-tom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance.

CIN and COUT Selection

In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 6 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input volt-age varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or:

VV

kN

where k NOUT

IN= = 1 2 1, , ..., –

So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages.

In the graph of Figure 4, the local maximum input RMS capacitor currents are reached when:

VV

kN

where k NOUT

IN= =2 1

1 2–

, , ...,

These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question.

The Figure 6 graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. Bat-tery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further

DUTY FACTOR (VOUT/VIN)0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.6

0.5

0.4

0.3

0.2

0.1

0

3731H F06

RMS

INPU

T RI

PPLE

CUR

RENT

DC L

OAD

CURR

ENT

6-PHASE4-PHASE

12-PHASE

3-PHASE2-PHASE1-PHASE

Figure 6. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Output Stages

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reduced by the factor, N, due to the effective increase in the frequency of the current pulses.

Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. “X7R”, “X5R” and “Y5V” are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions ap-plied. Physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The volt-age can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Never-theless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low ESR.

The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (∆VOUT) is determined by:

∆ ∆V I ESR

NfCOUT RIPPLEOUT

≈ +

18

where f = operating frequency of each stage, N is the number of output stages, COUT = output capacitance and ∆IL = ripple current in each inductor. The output ripple is highest at maximum input voltage since ∆IL increases with

applicaTions inForMaTioninput voltage. The output ripple will be less than 50mV at max VIN with ∆IL = 0.4IOUT(MAX) assuming:

COUT required ESR < N • RSENSE

and

COUT > 1/(8Nf)(RSENSE)

The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementa-tions possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristics of each capacitor type is significantly differ-ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design.

Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and Tokin offer high capacitance value and very low ESR, especially applicable for low output voltage applications.

In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface-mount tantalums or the Panasonic SP series of surface mount special polymer capacitors

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applicaTions inForMaTionavailable in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POS-CAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations.

RSENSE Selection for Output Current

Once the frequency and inductor have been chosen, RSENSE1, RSENSE2, RSENSE3 are determined based on the required peak inductor current. The current comparator has a typical maximum threshold of 75mV/RSENSE and an input common mode range of SGND to (1.1) • VCC. The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the IC and external component values yields:

R N

mVISENSEMAX

= 50

The IC works well with values of RSENSE from 0.002Ω to 0.02Ω.

VCC Decoupling

The VCC and VDR pins supply power to the internal cir-cuits of the controller and to the top and bottom gate drivers. Therefore, they must be bypassed very carefully to ground with ceramic capacitors, type X7R or X5R (de-pending upon the operating temperature environment) of at least 1µF immediately next to the IC and preferably an additional 10µF placed very close to the IC due to the extremely high instantaneous currents involved. The total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary to supply the high transient currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors, CB, connected to the BOOST pins, supply the gate drive voltages for the top-side MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from VCC when the SW pin is low. When one of the topside MOSFETs turns on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply (VBOOST = VCC + VIN). The value of the boost capacitor CB needs to be 30 to 100 times that of the total gate charge capacitance of the topside MOSFET(s) as specified on the manufacturer’s data sheet. The reverse breakdown of DB must be greater than VIN(MAX).

The output voltage is set by an external resistive divider according to the following formula:

V V

RROUT = +

0 6 112

.

The resistive divider is connected to the output as shown in Figure 2.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) ON/OFF, 2) soft-start and 3) a defeatable short-circuit latch off timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit (pro-portional to an internal buffered and clamped VITH). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up cur-rent (>5µA) supplied to the RUN/SS pin will prevent the overcurrent latch from operating. A maximum pull-up cur-rent of 200µA is allowed into the RUN/SS pin even though the voltage at the pin may exceed the absolute maximum rating for the pin. This is a result of the limited current and the internal protection circuit on the pin. The following explanation describes how this function operates.

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applicaTions inForMaTionAn internal 1.5µA current source charges up the CSS capacitor. When the voltage on RUN/SS reaches 1.5V, the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.5V, the internal current limit is increased from 20mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1s/µF to reach full current. The output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. If RUN/SS has been pulled all the way to ground, there is a delay before starting of approximately:

tVA

C s F C

tV V

AC s F C

DELAY SS SS

IRAMP SS SS

=µ

= µ( )

= −µ

= µ( )

1 51 5

1

3 1 51 5

1

..

/

..

/

By pulling the RUN/SS controller pin below 0.4V the IC is put into low current shutdown (IQ < 100µA). The RUN/SS pin can be driven directly from logic as shown in Figure 7. Diode, D1, in Figure 7 reduces the start delay but allows CSS to ramp up slowly, providing the soft-start function. The RUN/SS pin has an internal 6V Zener clamp (see the Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the controllers when an overcurrent condition is detected. The RUN/SS capacitor is used initially to turn on and limit the inrush current of all three output stages. After the con-trollers have been started and been given adequate time to charge up the output capacitor and provide full load current, the RUN/SS capacitor is used for a short-circuit

timer. If the output voltage falls to less than 70% of its nominal value, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the discharge current, and the circuit trip point, the controller will be shut down until the RUN/SS pin voltage is recycled. If the overload occurs during start-up, the time can be approximated by:

tLO1 >> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)

If the overload occurs after start-up, the voltage on the RUN/SS capacitor will continue charging and will provide additional time before latching off:

tLO2 >> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)

This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the RUN/SS pin from VCC as shown in Figure 7. When VCC is 5V, a 200k resistance will prevent the discharge of the RUN/SS capacitor dur-ing an overcurrent condition but also shortens the soft-start period, so a larger RUN/SS capacitor value may be required.

Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal foldback current limiting still remains active, thereby pro-tecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor.

The value of the soft-start capacitor CSS may need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capaci-tance is given by:

CSS > (COUT)(VOUT) (10–4) (RSENSE)

The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications.

RUN/SS PIN3.3V OR 5VRUN/SS PIN

5VVCC

RSS

CSSCSS

3731H F07

D1

SHDNSHDN

Figure 7. RUN/SS Pin Interfacing

LTC3731H

3731Hfb

applicaTions inForMaTion

Figure 8. Foldback Current Elimination

Current Foldback

In certain applications, it may be desirable to defeat the internal current foldback function. A negative impedance is experienced when powering a switching regulator. That is, the input current is higher at a lower VIN and decreases as VIN is increased. Current foldback is designed to ac-commodate a normal, resistive load having increasing current draw with increasing voltage. The EAIN pin should be artificially held 70% above its nominal operating level of 0.6V, or 0.42V in order to prevent the IC from “folding back” the peak current level. A suggested circuit is shown in Figure 8.

The emitter of Q1 will hold up the EAIN pin to a voltage in the absence of VOUT that will prevent the internal sensing circuitry from reducing the peak output current. Remov-ing the function in this manner eliminates the external MOSFET’s protective feature under short-circuit conditions. This technique will also prevent the short-circuit latchoff function from turning off the part during a short-circuit event and the peak output current will only be limited to N • 75mV/RSENSE.

Undervoltage Reset

In the event that the input power source to the IC (VCC) drops below 4V, the RUN/SS capacitor will be discharged to ground. When VCC rises above 4V, the RUN/SS capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. This may be useful in applications that switch between two supplies that are not diode connected,

but note that this cannot make up for the resultant inter-ruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET of output stage 1’s turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 400kHz. The nominal operating frequency range of the IC is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock the internal oscillator to harmonics of the input frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC:

∆fH = ∆fC = ±0.5 fOThe output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the PLLFLTR pin. A simplified block diagram is shown in Figure 9.

If the external frequency (fPLLIN) is greater than the os-cillator frequency, fOSC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fOSC, current is sunk continuously, pulling down

VCC

3731H F08

CALCULATE FOR0.42V TO 0.55V

VCC

EAIN

Q1LTC3731H

LTC3731H

03731Hfb


the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operat-ing point, the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC PLLIN pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A voltage of 1.7V or below applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 550kHz for 1.7V.

The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP ranges from 0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration that the IC is capable of turning on the top MOSFET. It is

determined by internal timing delays and the gate charge of the top MOSFET. Low duty cycle applications may ap-proach this minimum on-time limit and care should be taken to ensure that:

t

VV fON MIN

OUT

IN( ) < ( )

If the duty cycle falls below what can be accommodated by the minimum on-time, the IC will begin to skip every other cycle, resulting in half-frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase.

The minimum on-time for the IC is generally about 110ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.

If an application can operate close to the minimum on-time limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current for each channel equal to or greater than 30% of IOUT(MAX) at VIN(MAX).

Figure 9. Phase-Locked Loop Block Diagram

EXTERNALOSC

2.4V

RLP10k

CLP

OSC

DIGITALPHASE/

FREQUENCYDETECTOR

PHASEDETECTOR/OSCILLATOR

PLLIN

3731H F09

PLLFLTR

50k

LTC3731H

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applicaTions inForMaTionEfficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-age of input power.

Checking Transient Response

The regulator loop response can be checked by look-ing at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior, but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping fac-tor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications.

The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full load current having a rise time of <2µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be in-creased by decreasing CC. If RC is increased by the same factor that CC. is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.

A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If CLOAD is greater than 2% of COUT, the switch rise time should be controlled so that the load rise time is limited to approximately 1000 • RSENSE • CLOAD. Thus a 250µF capacitor and a 2mΩ RSENSE resistor would require a 500µs rise time, limiting the charging current to about 1A.

LTC3731H

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applicaTions inForMaTionAutomotive Considerations: Plugging into the Cigarette Lighter

As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, in-cluding load dump, reverse battery and double battery.

Load dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alterna-tor can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V.

The network shown in Figure 10 is the most straightforward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the IC has a maximum input voltage of 32V on the SW pins, most applications will be limited to 30V by the MOSFET BVDSS.

Design Example

As a design example, assume VCC = 5V, VIN = 12V(nominal), VIN = 20V(max), VOUT = 1.3V, IMAX = 45A and f = 400kHz. The inductance value is chosen first based upon a 30% ripple current assumption. The highest value of ripple current in each output stage occurs at the maximum input voltage.

LVf I

VV

VkHz

OUT OUT

IN=

∆( ) −

= ( )(

1

1 3400 30

.%))( ) −

≥ µ15

11 320

0 68A

VV

H

.

.

Using L = 0.6µH, a commonly available value results in 34% ripple current. The worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current.

RSENSE1, RSENSE2 and RSENSE3 can be calculated by using a conservative maximum sense current threshold of 65mV and taking into account half of the ripple current:

RmV

ASENSE =

+

= Ω65

15 1 342

0 0037%

.

Use a commonly available 0.003Ω sense resistor.

Next verify the minimum on-time is not violated. The minimum on-time occurs at maximum VCC:

t

VV f

VV kHz

nsON MINOUT

IN MAX( ) = ( ) = ( ) =

( )

.1 320 400

162

The output voltage will be set by the resistive divider from the DIFFOUT pin to SGND, R1 and R2 in the Functional Diagram. Set R1 = 13.3k and R2 = 11.3k.

Figure 10. Automotive Application Protection

+

LTC3731H

VCC5V

VBAT12V

3731H F10

LTC3731H

3731Hfb

applicaTions inForMaTionThe power dissipation on the topside MOSFET can be estimated. Using a Fairchild FDS6688 for example, RDS(ON) = 7mΩ, CMILLER = 15nC/15V = 1000pF. At maximum input voltage with T(estimated) = 50°C:

PVV

C C

ApF

V V VkHz W

MAIN ≈ ( ) + ( ) ° − °( )[ ]

+ ( ) ( )( )

Ω( )( )

+

( ) =

1 820

15 1 0 005 50 25

0 007 20452 3

2 1000

15 1 8

11 8

400 2 2

2

2

..

.

– . ..

Ω

The worst-case power dissipation by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50°C junction tem-perature rise is:

P

V VV

A WSYNC = − ( ) ( ) Ω( ) =20 1 320

15 1 25 0 007 1 842.. . .

A short circuit to ground will result in a folded back current of:

I

mVm

ns VH

ASC ≈+( ) Ω

+ ( )µ

=252 3

12

150 200 6

7 5.

.

with a typical value of RDS(ON) and d = (0.005/°C)(50°C) = 0.25. The resulting power dissipated in the bottom MOSFET is:

PSYNC = (7.5A)2(1.25)(0.007Ω) ≈ 0.5W

which is less than one third of the normal, full load con-ditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. Therefore, the system actually cools significantly during a shorted condition!

PC Board Layout Checklist

When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 11. Check the following in the PC layout:

1) Are the signal and power ground paths isolated? Keep the SGND at one end of a printed circuit path thus prevent-ing MOSFET currents from traveling under the IC. The IC signal ground pin should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the “shadow” of the package, connecting to the PGND pin and then continuing on to the (–) plates of CIN and COUT. The VCC decoupling capacitor should be placed immediately adjacent to the IC between the VCC pin and PGND. A 1µF ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 5µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes and (–) plates of CIN, which should have as short lead lengths as possible.

2) Does the VFB pin connect directly to the feedback re-sistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and signal ground.

3) Are the SENSE– and SENSE+ printed circuit traces for each channel routed together with minimum PC trace spac-ing? The filter capacitors between SENSE+ and SENSE– for each channel should be as close as possible to the pins of the IC. Connect the SENSE– and SENSE+ pins to the pads of the sense resistor as illustrated in Figure 12.

4) Do the (+) plates of CPWR connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the pulsed current to the MOSFETs.

5) Keep the switching nodes, SWITCH, BOOST and TG away from sensitive small-signal nodes (SENSE+, SENSE–, EAIN). Ideally the SWITCH, BOOST and TG printed circuit traces should be routed away and separated from the IC and especially the “quiet” side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes.

6) Use a low impedance source such as a logic gate to drive the PLLIN pin and keep the lead as short as possible.

LTC3731H

3731Hfb

7) The 47pF to 330pF ceramic capacitor between the ITH pin and signal ground should be placed as close as pos-sible to the IC.

Figure 11 illustrates all branch currents in a three-phase switching regulator. It becomes very clear after study-ing the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal


+RIN

VIN VOUT

CIN

BOLD LINES INDICATE HIGH,SWITCHING CURRENTS.KEEP LINES TO A MINIMUM LENGTH.

+COUT

D3

D2

SW2

D1

L1

SW1 RSENSE1

L2

RSENSE2

L3

SW3 RSENSE3

3731H F11

RL

SENSE+LTC3731H

1000pF

INDUCTOR

OUTPUT CAPACITOR

SENSERESISTOR

3731H F12

SENSE–

Figure 11. Branch Current Waveforms

Figure 12. Kelvin Sensing RSENSE

LTC3731H

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applicaTions inForMaTionof the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” generated by a switching regulator. The ground terminations of the synchronous MOSFETs and Schottky diodes should return to the bot-tom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the IC power ground pin (PGND). This technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure.

Simplified Visual Explanation of How a 3-Phase Controller Reduces Both Input and Output RMS Ripple Current

The effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input volt-age is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 13 graphically illustrates the principle.

VSW

SINGLE PHASE

TRIPLE PHASE

ICIN

ICOUT

VSW1

VSW2

VSW3

IL1

IL2

IL3

ICIN

ICOUT

3731H F13

Figure 13. Single and Polyphase Current Waveforms

LTC3731H

3731Hfb

applicaTions inForMaTionThe worst-case input RMS ripple current for a single stage design peaks at twice the value of the output voltage. The worst-case input RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input RMS ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. The peaks, however, are at ever decreasing levels with the addition of more phases. A higher effective duty factor results because the duty factors “add” as long as the currents in each stage are balanced. Refer to AN19 for a detailed description of how to calculate RMS current for the single stage switching regulator.

Figure 6 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ratio of input and output voltage. The peak input RMS current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages.

The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge currents term from the stages that has their bottom MOSFETs on subtract current from the (VCC – VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current for a 3-phase design is:

IP-P = ( )( ) ( ) >V

f LDC V VOUT

IN OUT1 3 3–

The ripple frequency is also increased by three, further re-ducing the required output capacitance when VCC < 3VOUT as illustrated in Figure 6.

The addition of more phases, by phase locking addi-tional controllers, always results in no net input or output ripple at VOUT/VIN ratios equal to the number of stages implemented. Designing a system with multiple stages close to the VOUT/VIN ratio will significantly reduce the ripple voltage at the input and outputs and thereby improve efficiency, physical size and heat generation of the overall switching power supply. Refer to Application Note 77 for more information on Polyphase circuits.

Efficiency Calculation

To estimate efficiency, the DC loss terms include the input and output capacitor ESR, each MOSFET RDS(ON), inductor resistance RL, the sense resistance RSENSE and the forward drop of the Schottky rectifier at the operating output current and temperature. Typical values for the design example given previously in this data sheet are:

Main MOSFET RDS(ON) = 7mΩ (9mΩ at 90°C) Sync MOSFET RDS(ON) = 7mΩ (9mΩ at 90°C) CINESR = 20mΩ COUTESR = 3mΩ RL = 2.5mΩ RSENSE = 3mΩ VSCHOTTKY = 0.8V at 15A (0.7V at 90°C) VOUT = 1.3V VIN = 12V IMAX = 45A d = 0.5%°C (MOSFET temperature coefficient) N = 3 f = 400kHzThe main MOSFET is on for the duty factor VOUT/VIN and the synchronous MOSFET is on for the rest of the period or simply (1 – VOUT/VIN). Assuming the ripple current is small, the AC loss in the inductor can be made small if a good quality inductor is chosen. The average current, IOUT, is used to simplify the calculations. The equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application. Determining the MOSFETs’ die temperature may require iterative calculations if one is not familiar with typical performance. A maximum operating junction temperature of 90° to 100°C for the MOSFETs is recommended for high reliability applications.

Common output path DC loss:

P NI

NR R C LoCOMPATH

MAXL SENSE OUTESR≈

+( ) +2

sss

This totals 3.7W + COUTESR loss.

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applicaTions inForMaTionTotal of all three main MOSFETs’ DC loss:

P NVV

IN

RMAINOUT

IN

MAXDS ON=

+( )2

1 d ( )) + C LossINESR

This totals 0.87W + CINESR loss (at 90°C).

Total of all three synchronous MOSFETs’ DC loss:

P N

VV

IN

RSYNCOUT

IN

MAXDS=

+( )1 12

– (d OON)

This totals 7.2W at 90°C.

Total of all three main MOSFETs’ AC loss:

P VA

pF

V V VkHz W

MAIN IN≈ Ω

+

=

3452 3

2 1000

15 1 8

11 8

400 6 3

2( )( )( )

( )( )

– . .( ) .

This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W at VIN = 20V.

Total of all three synchronous MOSFETs’ AC gate loss:

( ) ( ) ( )( ) ( )3 6 15 4 5Q

VV

f nCV

VEG

IN

DSSPEC

IN

DSSPEC=

This totals 0.08W at VIN = 8V, 0.12W at VIN = 12V and 0.19W at VIN = 20V. The bottom MOSFET does not experience the Miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground.

The Schottky rectifier loss assuming 50ns nonoverlap time:

2 • 3(0.7V)(15A)(50ns)(4E5)

This totals 1.26W.

The total output power is (1.3V)(45A) = 58.5W and the total input power is approximately 60W so the % loss of each component is as follows:

Main switch’s AC loss (VIN = 12V) 2.25W 3.75%

Main switch’s DC loss 0.87W 1.5%

Synchronous switch AC loss 0.19W 0.3%

Synchronous switch DC loss 7.2W 12%

Power path loss 3.7W 6.1%

The numbers above represent the values at VIN = 12V. It can be seen from this simple example that two things can be done to improve efficiency: 1) Use two MOSFETs on the synchronous side and 2) use a smaller MOSFET for the main switch with smaller CMILLER to better balance the AC loss with the DC loss. A smaller, less expensive MOSFET can actually perform better in the task of the main switch.

LTC3731H

3731Hfb

Typical applicaTions

Figure 14. 3-Phase 65A Power Supply

0.01µF

1µF

10k

VCCSYNC IN300kHz

300pF

1000pFS1+

S1–

S2+

S2–

S3–

S3+

VCC

PLLIN

PLLFLTR

FCB

NC

NC

NC

LTC3731HG

EAIN

SGND

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

SENSE3+

RUN/SS

ITHITH

UVADJ

CLK1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

VDR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND

1000pF

OPTIONAL FILTER FORSYNCHRONIZATION

100pF

6.04k 9.09k

10Ω

V55V TO 7VVIN

M1

M2 D1S1+

S1–

L1 0.002Ω

0.01µF

2.2k3.3nF

330pF

1000pF

1µF

NC

3731H F14

VIN: 3.3V TO 20VVOUT: 1.5V AT 65ASWITCHING FREQUENCY: 300kHz

PGOOD

47k

1Ω

1000pF

10µF

0.1µF

V5

0.1µF

0.1µF

V5

V5

VIN

M3

M4 D2

S2+ S2–

L2 0.002Ω

VIN

M5

M6 D3

S3+ S3–

L3 0.002Ω

10µF6.3V

3COUT

VIN3.3V TO 20V

VOUT1.5V AT 65A

+

10µF25V

5

CIN68µF25V

+

CIN: SANYO OS-CON 25SP68MCOUT: 270µF/2V 8 PANASONIC SP EEUE0D271R OR 470µF/2.5V 6 SANYO POSCAP 2R5 TPD470MD1 TO D3: DIODES INC. B340A

L1 TO L3: 0.8µH SUMIDA CEP125-0R8M1, M3, M5: IRF7821W 2, Si7860DP

OR HAT2168 2M2, M4, M6: IRF7832 2, Si7892DP 2

OR HAT2165 2

VIN18k

12k

LTC3731H

3731Hfb

Typical applicaTions2.5V/100A Power Supply

3.3k

VCC

220pF

EAIN

1000pFS1+

S1–

S2+

S2–

S3–

S3+

VCC

PLLIN

PLLFLTR

FCB

NC

NC

NC

LTC3731HG

EAIN

SGND

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

SENSE3+

RUN/SS

ITH

UVADJ

CLKOUT1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

VDR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND2

4.64k 14.7k

330pF

8.2k

1k

VIN

M1

X2M2,3 D1

S1+ S1–

L1 0.002Ω

EAIN

RUN/SS

RUN/SS

0.1µF

1000pF

CLK1PGOOD BOOST1

10k

10Ω

1Ω

1000pF

0.1µF

0.1µF

0.1µF

BOOST2BOOST3

10µFCer.

VIN

M4

X2M5,6 D2

S2+ S2–

L2 0.002Ω

VIN

M7

X2M8,9 D3

S3+ S3–

L3 0.002Ω

COUT

VIN

VOUT

VCC

VCC

SYNC IN

VCC

V5

+

CIN

+

3731H F15

NOTES:V5: 5V TO 7VVIN: 10V TO 14V; VOUT: 2.5V/100ASWITCHING FREQUENCY: 500kHz (V5 = 5V)

M1, M4, M7, M10, M13, M16:SILICONIX Si7390DP OR HAT2168M2, M3, M5, M6, M8, M9, M11, M12, M14, M15,M17, M18: SILICONIX Si7356DP OR HAT2165D1 TO D6: B320A

L1 TO L6: TOKO FDH1040: 0.56µHCIN: 10µF/16V CERAMIC 10 + 270µF/16V SANYO Os-ConCOUT: 100µF/6.3V/X5R 10 + 330µF/4V 8

VIN

357k

121k

10Ω 6

10Ω 6

1000pF

68pF

UVADJ

100pF

1µF

10µF10V

1µFCer. 4.7µF

+

+

0.01µF10k

VCC

1000pFS4+

S4–

S5+

S5–

S6–

S6+

VCC

PLLIN

PLLFLTR

FCB

NC

NC

NC

LTC3731HG

EAIN

SGND

SENSE4+

SENSE4–

SENSE5+

SENSE5–

SENSE6–

SENSE6+

RUN/SS

ITH

ITH

UVADJ

CLKOUT1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD

BOOST4

TG4

SW4

BOOST5

TG5

SW5

VDR

BG4

PGND

BG5

BG6

SW6

TG6

BOOST6

PHASMD

SGND2

1000pF

1000pF

VIN

M10

X2M11,12 D4

S4+ S4–

L4 0.002Ω

100pF

1.2k2700pF

270pF

10pF

1000pF

CLKOUT

CLK1

UVADJ

PGOOD

BOOST4

10Ω

1000pF

0.1µF

0.1µF

0.1µF

BOOST5BOOST6

VIN

M13

X2M14,15 D5

S5+ S5–

L5 0.002Ω

VIN

M16

X2M17,18 D6

S6+ S6–

L6 0.002Ω

V5

1µFCer. 4.7µF

+

LTC3731H

03731Hfb

3-Phase Boost Converter. VIN = 10V to 18V with 36V Load Dump, VOUT = 50V at 3A

Typical applicaTions

VCC

C11µF

6.5V

R40Ω

R3OPT

PLLIN

PLLFLTR

FCB

NC

NC

NCLTC3731HG

EAIN

SGND

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

SENSE3+

RUN/SS

ITH

UVADJ

CLK1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

VDR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND

+

C3OPT

R7665k

C41000pF

VOUT+

R10 500Ω

R11 500Ω

R68.06k

R110Ω

R21M

1

2

8

5

4

S1+

S1–

C51000pF

R12 500Ω

R13 500Ω

S2+

S2–

C61000pF

C70.1µF

C531000pF

R14 500Ω

R15 500Ω

RUN/SS

VIN+

VIN+

S3+

S3–

RUN/SS

R1610k

C81000pF

C9220pF

R17121k

R18845k

R30OPT

IS SIGNAL GROUND IS POWER GROUND

KEEP SEPARATE AND REFER TO PCB LAYOUT CHECKLIST FOR ROUTING INFORMATION

C14.7µF

Q3Si7852DP

L312µH

CIN4-CIN6: 10µF, 50V X5R TDK C5750X5R1H106MC16-C26: 1µF, 100V X7R TAIYO YUDEN HMK432BJ105KMC17: 150µF, 63V SANYO ALUMINUM ELECTROLYTIC 63MV150GXC20: 33µF, 100V SANYO ALUMINUM ELECTROLYTIC 100CV33FSL1-L3: 12µH SUMIDA CDRH127/LD-120

R230.007Ω

6.5V S3+

3731H TA01

S3–

Q2Si7852DP

L212µH

R230.007Ω

S2+

S2–

Q1Si7852DP

L112µH D4

30BQ060

D430BQ060

D430BQ060

VIN+

VIN–

VOUT+

50V/3A

VOUT–

VIN+

CIN4-CIN610µF50V

C16-C18,C20-C261µF100V

C17150µF63V

+ C2033µF100V

10V TO 18VWITH 36VLOAD DUMP

R230.007Ω

S1+

S1–

C191µF10V

C181µF50V

R5249k

IN

LT3010

SHDN

OUTVIN+

ADJGND

VOUT+

LTC3731H

3731Hfb

package DescripTion

G36 SSOP 0204

0.09 – 0.25(.0035 – .010)

0° – 8°

0.55 – 0.95(.022 – .037)

5.00 – 5.60**(.197 – .221)

7.40 – 8.20(.291 – .323)

1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 1813

12.50 – 13.10*(.492 – .516)

2526 22 21 20 19232427282930313233343536

2.0(.079)MAX

0.05(.002)MIN

0.65(.0256)

BSC0.22 – 0.38

(.009 – .015)TYPMILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.77.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

G Package36-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

LTC3731H

3731Hfb

package DescripTion

5.00 0.10(4 SIDES)

NOTE:1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1TOP MARK(NOTE 6)

0.40 0.10

31

1

2

32

BOTTOM VIEW—EXPOSED PAD

3.50 REF(4-SIDES)

3.45 0.10

3.45 0.10

0.75 0.05 R = 0.115TYP

0.25 0.05(UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05

0.70 0.05

3.50 REF(4 SIDES)

4.10 0.05

5.50 0.05

0.25 0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUTAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH R = 0.30 TYPOR 0.35 45° CHAMFERR = 0.05

TYP

3.45 0.05

3.45 0.05

UH Package32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

LTC3731H

3731Hfb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisToryREV DATE DESCRIPTION PAGE NUMBER

B 5/10 UH package added. Changes reflected throughout the data sheet 1 - 34

(Revision history begins at Rev B)

LTC3731H

3731Hfb

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2010

LT 0510 REV B • PRINTED IN USA

relaTeD parTs

Typical applicaTion1µF

VCC

1000pFS1+

S1–

S2+

S2–

S3–

S3+

VCC

PLLIN

PLLFLTR

FCB

NC

NC

NC

LTC3731HG

EAIN

SGND

SENSE1+

SENSE1–

SENSE2+

SENSE2–

SENSE3–

SENSE3+

RUN/SS

ITHITH

UVADJ

CLK1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PGOOD

BOOST1

TG1

SW1

BOOST2

TG2

SW2

VDR

BG1

PGND

BG2

BG3

SW3

TG3

BOOST3

PHASMD

SGND

100pF

SHORTPLLFLTR TO

SGND

20k 147k

10Ω

V55V TO 7VVIN

M1

M2 D1S1+

S1–

L1 0.003Ω

0.01µF

3.01k10nF

100pF

1000pF

1µF

NC

3731H TA02

VIN: 9V TO 28VVOUT: 5V AT 40ASWITCHING FREQUENCY: 225kHz

PGOOD

47k

1Ω

1000pF

10µF

0.1µF

V5

0.1µF

0.1µF

V5

V5

VIN

M3

M4 D2

S2+ S2–

L2 0.003Ω

VIN

M5

M6 D3

S3+ S3–

L3 0.003Ω

47µF10V

3COUT

VIN9V TO 28V

VOUT5V AT 40A

+

4.7µF50V

6

CIN47µF35V

4

+

CIN: KEMET T521X476M035ATE070 4COUT: SANYO 6TPE220MI 3D1 TO D3: DIODES INC. B340A

L1 TO L3: 2.2µH WURTH 7443320220M1, M3, M5: RJK0305DPBM2, M4, M6: RJK0330DPB

VIN18k

12k

PART NUMBER DESCRIPTION COMMENTS

LTC3829 3-Phase, Single Output, Synchronous Step-Down Controller with Differential Amp and DCR Temperature Compensation

4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V, Active Voltage Positioning, Stage Shedding

LTC3856 2-Phase, Single Output, Synchronous Step-Down Controller with Differential Amp and DCR Temperature Compensation

4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5V, Active Voltage Positioning, Stage Shedding

LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Differential Amp and DCR Temperature Compensation

Phase-Lockable Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V

LTC3860 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Differential Amp and Tri-State Output Drive

Operates with Power Blocks, DRMOS Devices or External MOSFETs 3V ≤ VIN ≤ 24V, tON(MIN) = 20ns

LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking

Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 24V, VOUT3 up to 13.5V

LTC3850/LTC3850-1/LTC3850-2

Dual 2-Phase, High Efficiency Synchronous Step-Down DC/DC Controller, RSENSE or DCR Current Sensing and Tracking

Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V

ltc3731h - 3-phase, 600khz, synchronous buck switching … · 2020-02-01 · n 3-phase current mode...

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