lte dfe app note

XAPP1123 (v1.0) October 29, 2008 www.xilinx.com 1

2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Summary This application note provides designers with an optimized solution for Digital Up Conversion (DUC), Digital Down Conversion (DDC), and Crest Factor Reduction (CFR) required in a typical 3rd Generation Partnership Protocol (3GPP) Long Term Evolution (LTE) radio.The design is configurable to support seven single and multi-carrier scenarios, while offering an optimized solution for each chosen configuration that allows designers to select their requirement without paying a penalty on design area, and therefore cost and power. Developed in Xilinx System Generator for DSP, the design allows customization to meet the needs of radio designs for the 3GPP LTE specification.Accompanying this application note are design files, test vectors, and scripts that allow designers to quickly evaluate the performance of the reference design within MATLAB. Additionally, instructions on how to integrate the reference design into a larger system design are included. Design files are available for Virtex-5 device architectures.

Introduction The wireless industry is aggressively reducing Capital Expenditure (CapEx) and Operating Expenditure (OpEx). It is estimated that up to 60 percent of the overall CapEx cost is incurred within the radio elements of a typical base station. Additionally, since the radio also contains the power amplifiers, the radio portion of the design is responsible for much of the OpEx incurred during the lifetime of the site. Reducing CapEx can be achieved through the use of less costly non-linear power amplifiers, and highly integrated digital radio transceivers. Integration, low cost, high reliability, and low power are key elements to the Xilinx radio solution. To meet industry cost needs, designs must be realized in Xilinx devices in the most efficient manner possible. This application note demonstrates that high clock rates and efficient design techniques for DUC, DDC, and CFR processing in Xilinx devices enables designers to meet the needs of their radio designs with very low cost and low power, while benefiting from smaller PCB area and greater reliability.Additionally, OpEx can be reduced through the use of advanced algorithms. OpEx is directly related to the power amplifier efficiency in the base station. Currently, a very small proportion of the DC power consumed by the base station is converted to radiated energy. The efficiency at which a power amplifier can be operated is a function of the transmitted signal. LTE signals have a high Peak-to-Average Power Ratio (PAPR) or Crest Factor. This imposes significant operating restrictions on the power amplifier. To handle the peaks, the amplifier is heavily backed off from its most efficient operating point. To increase efficiency, CFR algorithms can be used to decrease the PAPR of the transmitted signal prior to it entering the power amplifier. By doing so, the power amplifier can operate with less back off and thus increased efficiency. Another method of improving the efficiency of power amplifiers is to use Digital Pre-Distortion (DPD). Rather than use digital signal processing to reduce the dynamic range of the transmitted signal as with CFR, DPD is used to linearize the power amplifier itself. DPD is outside the scope of this document, but its reference is included as a widely used method of amplifier efficiency improvement.

Application Note: Virtex-5 FPGA

XAPP1123 (v1.0) October 29, 2008

3GPP LTE Digital Front End Reference DesignAuthors: Helen Tarn, Ed Hemphill, and David Hawke

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Introduction


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Acronyms and Abbreviations3GPP 3rd Generation Partnership ProjectAGC Automatic Gain ControlBlock RAM Block Random Access Memory (Xilinx device resource)BS Base StationBTS Base Transceiver StationCapEx Capital ExpenditureCFR Crest Factor ReductiondB DecibelsDDC Digital Down ConverterDDS Direct Digital SynthesizerDFE Digital Front EndDPD Digital Pre-DistortionDSP Digital Signal Processing/ProcessorDUC Digital Up ConverterEDGE Enhanced Data rates for GSM EvolutionEDGE2 or e-EDGE Evolved EDGEFPGA Field Programmable Gate ArrayFIR Finite Impulse ResponseGSM Global System for Mobile (Communications), originating from Groupe

Spcial MobileGUI Graphical User InterfaceHDL Hardware Description LanguageIF Intermediate FrequencyLSB Least Significant Bit(s)LUT Look-Up TableMAC Multiply-AccumulateMSB Most Significant Bit(s)Msps Mega-samples per second (1,000,000 samples per second)OpEx Operation ExpendituresPAPR Peak-to-Average Power RatioPAR Place and RoutePSD Power Spectral DensityRMS Root Mean SquareSFDR Spurious-Free Dynamic RangeSNR Signal-to-Noise RatioTDM Time Division MultiplexXST Xilinx Synthesis Technology

Contents


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Contents Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4System-Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Transmit Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Receive Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Transmit Downlink Design & Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Digital Up Converter Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Crest Factor Reduction Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Receive Uplink Design & Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44System Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Resource Utilization Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Resource Utilization for Downlink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Resource Utilization for Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Power Consumption for Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Power Consumption for Uplink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Interface Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Downlink Interface Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Downlink Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Uplink Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Uplink Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Notice of Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figures Figure 1. Digital Front-End Architecture for Transmit Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 2. Digital Front-End Architecture for Receive Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 3. Reference Point for EVM Measurement on an LTE System. . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 4. Digital Up Converter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5. PSD of the Baseband LTE Signal for 20-MHz Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 6. Magnitude Response of Single-Rate Channel Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 7. Interpolation Filter Structure for 1x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 8. Interpolation Filter Structure for 1x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 9. Interpolation Filter Structure for 1x15 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 10. Interpolation Filter Structure for 1x20 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 11. Interpolation Filter Structure for 2x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 12. PSD after Multi-Carrier Mixing @ 15.36 MHz for 2x5 MHz Configuration. . . . . . . . . . . . . . . 17Figure 13. Interpolation Filter Structure for 2x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 14. PSD after Multi-Carrier Mixing @ 30.72 MHz for 2x10 MHz Configuration. . . . . . . . . . . . . . 18Figure 15. Interpolation Filter Structure for 4x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 16. PSD after Multi-Carrier Mixing @ 30.72 MHz for 4x5 MHz Configuration. . . . . . . . . . . . . . . 19Figure 17. 4-Channel Mixing and Combining Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 18. Time Domain View of Peak Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 19. Block Diagram of PC-CFR Method (One Iteration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 20. CCDF of CFR Input and Output with Two Iterations of PC-CFR (1x10 MHz) . . . . . . . . . . . . 25Figure 21. PSD of CFR Input and Output with Two Iterations of PC-CFR (1x10 MHz) . . . . . . . . . . . . . 25Figure 22. Constellation Plot for 64 QAM (1x10 MHz) 4% EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 23. CCDF of CFR Input and Output with Two Iterations of PC-CFR (2x10 MHz) . . . . . . . . . . . . 27Figure 24. PSD of CFR Input and Output with Two Iterations of PC-CFR (2x10 MHz) . . . . . . . . . . . . . 27Figure 25. CCDF of CFR Input and Output with [1 1 1 1] Carrier Configuration, 4% EVM . . . . . . . . . . 29Figure 26. Non-ideal CCDF Curve with [1 1 1 1] Carrier Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 27. PSD of CFR Input and Output with [1 0 0 1] Carrier Config, 4% EVM . . . . . . . . . . . . . . . . . 30Figure 28. System Generator Block Diagram of Transmit Downlink for 4x5 MHz Configuration . . . . . . 31

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Figure 29. System Generator DUC Configuration Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 30. GUI for Single Carrier DUC Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 31. System Generator Block Diagram of DUC for 1x15 MHz Configuration . . . . . . . . . . . . . . . . 33Figure 32. System Generator Block Diagram of DUC for 1x15 MHz Configuration . . . . . . . . . . . . . . . . 33Figure 33. System Generator Block Diagram of Mixer & Combiner for 4x5 MHz Configuration . . . . . . 38Figure 34. System Generator Block Diagram of Rasterized DDS (Half Wave Storage . . . . . . . . . . . . . 39Figure 35. System Generator Diagram of Step Terminal Count Block (4x5 MHz Configuration). . . . . . 39Figure 36. System Generator Block Diagram of Rasterized DDS (Full Wave Storage) . . . . . . . . . . . . . 41Figure 37. System Generator Diagram of Step Terminal Count Block (2x5 MHz Configuration). . . . . . 41Figure 38. System Generator Block Diagram of Rate and Data Format Conversion Block . . . . . . . . . . 42Figure 39. System Generator Block Diagram of PC-CFR Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 40. System Generator Diagram of Cancellation Pulses (c_pulses) Module, 6 CPGs version . . 45Figure 41. Decimation Filter Structure for 1x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Figure 42. Decimation Filter Structure for 1x15 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 43. Decimation Filter Structure for 1x20 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 44. Decimation Filter Structure for 2x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 45. Decimation Filter Structure for 2x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 46. Decimation Filter Structure for 4x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 47. Magnitude Response of Channel Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 48. Example DDS Output Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 49. Block Diagram of Receive Uplink Simulation Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 50. PSD of DDC Input with No Noise and No Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Figure 51. Transmitted and Received Constellation with No Noise and No Interference. . . . . . . . . . . . 61Figure 52. PSD of DDC Input for Noise Only Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 53. Transmitted and Received Constellation for Noise Only Case . . . . . . . . . . . . . . . . . . . . . . . 62Figure 54. PSD of DDC Input for Wideband ACS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 55. PSD of DDC Input for Narrowband ACS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 56. PSD of DDC Input for Wideband Intermod Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Figure 57. PSD of DDC Input for Narrowband Intermod Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Figure 58. System Generator Block Diagram of DDC Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 59. System Generator Block Diagram of DDC for 1x5 MHz Configuration . . . . . . . . . . . . . . . . . 68Figure 60. System Generator Block Diagram of DDC for 4x5 MHz Configuration . . . . . . . . . . . . . . . . . 69Figure 61. System Generator Block Diagram of Fs_4_Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Figure 62. System Generator Block Diagram of HB4 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 63. Screen Shots of FIR Compiler 4.0 GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 64. System Generator Block Diagram of Four-Carrier Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 65. System Generator Block Diagram of Four-Carrier Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 66. System Generator Block Diagram of TDM Circuit for Carrier Frequencies. . . . . . . . . . . . . . 76Figure 67. System Generator Block Diagram of Frequency-to-Phase Accumulator . . . . . . . . . . . . . . . 76Figure 68. System Generator Block Diagram of Sine/Cosine Lookup Table . . . . . . . . . . . . . . . . . . . . . 77Figure 69. Dynamic Power versus Frequency of LTE DUC/CFR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 70. Dynamic Power versus Frequency of LTE DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 71. Downlink Top-Level Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Figure 72. Timing Diagram of Input Data Interface for Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 73. Timing Diagram of Input Control Interface for Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 74. Timing Diagram of CFR Configuration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Figure 75. Timing Diagram of Output Data Interface for Downlink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 76. DDC Top-Level Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 77. Timing Diagram of Data Interface for DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Tables Table 1. Performance Summary for Transmit Downlink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Table 2. Performance Summary for Receive Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 3. General LTE Emission Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 4. Additional LTE Emission Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 5. Spectral Mask Requirements for LTE (5/10/15/20 MHz BW). . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 6. Properties for Different Carrier Bandwidth Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 7. Filter Parameters for the Channel Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Table 8. Filter Parameters for Reference Design Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 9. Prototype Filter for Designing Cancellation Pulse Coefficients . . . . . . . . . . . . . . . . . . . . . . . . 21Table 10. PC-CFR Performance for Single-Carrier Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 11. PC-CFR Performance for Dual-Carrier Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 12. PC-CFR Performance for 4x5MHz Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 13. FIR Compiler Settings for 1x5 MHz Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 14. FIR Compiler Settings for 1x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 15. FIR Compiler Settings for 1x15 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 16. FIR Compiler Settings for 1x20 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Table 17. FIR Compiler Settings for 2x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Table 18. FIR Compiler Settings for 2x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Table 19. FIR Compiler Settings for 4x5 MHz Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 20. Resource Utilization Summary for PC-CFR Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 21. E-UTRA BS Reference Sensitivity Level (From 3GPP TR 36.104, Table 7.2-1) . . . . . . . . . . 44Table 22. ACS Requirement with Wideband Interferer (from Table 7.5-3 of [Ref 2]) . . . . . . . . . . . . . . . 45Table 23. ACS Requirement with Narrowband Interferer (from Tables 7.5-1,2 of [Ref 2]). . . . . . . . . . . 45Table 24. In-Band Blocking Requirements (from Tables 7.6-1,2 of [Ref 2]) . . . . . . . . . . . . . . . . . . . . . 46Table 25. Wideband Intermodulation Requirements (from Tables 7.8-1,2 of [Ref 2] . . . . . . . . . . . . . . 47Table 26. Narrowband Intermodulation Requirements (from Table 7.8-3 of [Ref 2]) . . . . . . . . . . . . . . . 47Table 27. Summary of ACS, Blocking, and Intermodulation Requirements . . . . . . . . . . . . . . . . . . . . . . 47Table 28. Filter Parameters for Halfband Decimator that Follows Fs/4 Mixer . . . . . . . . . . . . . . . . . . . . 49Table 29. Filter Parameters for 1x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 30. Filter Parameters for 1x15 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 31. Filter Parameters for 1x20 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 32. Filter Parameters for 1x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 33. Filter Parameters for 2x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Table 34. Filter Parameters for 2x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 35. Filter Parameters for 4x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Table 36. Filter Parameters for the Channel Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 37. Decimation Filter Characteristics after 18-Bit Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . 55Table 38. SC-FDMA Parameters for Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 39. SC-FDMA Parameters for Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 40. Performance Data for Noise Only Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 41. Performance Data for Wideband ACS Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 42. Performance Data for Narrowband ACS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 43. Performance Data for In-Band Blocking Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 44. Performance Data for Wideband Intermod Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 45. Performance Data for Narrowband Intermod Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 46. FIR Compiler Settings for 1x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 47. FIR Compiler Settings for 1x10 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 48. FIR Compiler Settings for 1x15 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 49. FIR Compiler Settings for 1x20 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 50. FIR Compiler Settings for 2x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 51. FIR Compiler Settings for 2x10 MHz Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 52. FIR Compiler Settings for 4x5 MHz Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 53. Resource Utilization Summary for Downlink Design (DUC+CFR) . . . . . . . . . . . . . . . . . . . . . 76Table 54. Resource Utilization Summary for DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 55. Dynamic Power of LTE DUC/CFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 56. Dynamic Power of LTE DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 57. Port Definitions for Downlink Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 58. Period for Input Valid Signal (vin) in Downlink Configurations . . . . . . . . . . . . . . . . . . . . . . . . 82Table 59. Port Definitions for DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 60. Latency and Total Delay of DUC+CFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

System-Level Overview


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Transmit DownlinkFigure 1 shows the top-level block diagram for the transmit downlink portion of the digital front-end reference design. The downlink portion includes a DUC, which up samples the baseband signals to 122.88 Mega-samples per second (Msps), and a peak cancellation crest factor reduction (PC-CFR) module to control the peak of the signal to average power ratio (PAPR). The reference design supports seven different configurations: Single-carrier 5-MHz, 10-MHz, 15-MHz, and 20-MHz bandwidths Dual-carrier 5-MHz and 10-MHz bandwidths Four-carrier 5-MHz bandwidthThe common zero intermediate frequency (IF) architecture is assumed. Therefore, for single-carrier configurations, the DUC consists of several stages of interpolation filtering and no mixer stage is required. For multi-carrier configurations, a mixing and combining stage is necessary to allocate an individual carrier to its relative position in a 10-MHz or 20-MHz bandwidth before further processing.

Performance SummaryTable 1 summarizes the performance of the transmit downlink portion of the digital front-end design.

X-Ref Target - Figure 1

Figure 1: Digital Front-End Architecture for Transmit Downlink

Table 1: Performance Summary for Transmit Downlink Parameter Value Comments

Channel Bandwidths (BW)

5, 10, 15, 20 MHz Also support 2x5 MHz, 2x10 MHz, and 4x5 MHz configurations.

Input Sample Rates 7.68, 15.36, 23.04, 30.72 Msps

For channel bandwidths of 5, 10, 15, 20 MHz, respectively.

Output Sample Rate 122.88 MspsFPGA Clock Rate 368.64 MHz 3122.88 MHzSpectral Mask Requirements

For frequency offsets:within 0 ~ 1 MHz: 55 dB within 1 ~ 10 MHz: 65 dB over 10 MHz: 67 db

Derived from Table 6.6.2.2-6, -7, -12 and -13 of Table 1 plus 15 dB margin (assuming maximum base station power = 46 dBm).

ACLR 60 dBPAPR Target 6~8 dB @ 0.01% clipping

probability

X1123_01_100108

ChannelFilter

PC-CFR

7.6815.3623.0430.72Msps

122.88Msps

InterpolationFiltering andMulti-carrier

Mixing

Digital Up Converter

122.88Msps



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Receive UplinkAs illustrated in Figure 2 the receive uplink portion of the digital front-end reference design consists of a first stage mixer, decimation filters, a second stage mixer (for multi-carrier configurations), and a channel filter. The first stage mixer is based on an IF centered at one fourth the sample rate (Fs/4). This allows for a very efficient hardware implementation of the mixing process and initial halfband filtering. If the IF is centered at a frequency other than Fs/4, an alternate structure must be used. For example, a generic DDS can be generated using the Xilinx DDS Compiler and this can be combined with a DSP48-based complex multiplier to perform the mixing. The output of this more generic mixing process would feed a traditional halfband decimator that can be designed using the Xilinx Finite Impulse Response (FIR) Compiler.Multiple decimation filtering architectures are required to support the various bandwidths and carrier configuration options in a hardware efficient manner. For multi-carrier configurations, the decimation filtering module includes a second stage of mixing that is used prior to final decimation and channel filtering.

Performance SummaryTable 2 summarizes the performance of the receive uplink portion of the digital front-end design. The target filter parameters are derived from the adjacent channel selectivity (ACS), blocking, and intermodulation requirements of the LTE BS receiver described in the [Ref 1]. The ACS,

EVM for Digital Portion For single carrier: 2% at 8 dB PAPR 4% at 7 dB PAPR 7% at 6 dB PAPRFor multi-carrier:Crest Factor Reduction Architecture, page 19 for detail.

64 QAM Modulation

Input Signal Quantization 16 bits I/Q Complex inputOutput Signal Quantization

16 bits I/Q Complex output

Mixer Properties Tunability: FixedResolution: 100 kHzSpurious-Free Dynamic Range (SFDR): Ideal

Assume zero IF; used only in multi-carrier configurations.Use rasterized DDS based on 100 kHz raster.

Table 1: Performance Summary for Transmit Downlink (Contd)Parameter Value Comments


Figure 2: Digital Front-End Architecture for Receive UplinkX1123_02_100108

ChannelFilter

To BasebandProcessing

FromAD

Converter

7.6815.3623.0430.72Msps

7.6815.3623.0430.72Msps

61.44Msps

DecimationFiltering

andMulit-carrier

Mixing

All modules running @ 368.64 MHz. Sample rates are per single complex channel.

Halfband2

Fs/4Mixer

122.88Msps



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blocking, and intermodulation requirements are summarized in the following subsections along with some assumptions that were used in deriving the filter requirements.Table 2: Performance Summary for Receive Uplink

Parameter Value CommentsChannel Bandwidths (BW) 5, 10, 15, 20 MHz Also supports 2x5 MHz, 2x10

MHz, and 4x5 MHz configurations.

Input Sample Rate 122.88 Msps 167.68 Msps.Output Sample Rates 7.68, 15.36, 23.04, 30.72 Msps For channel bandwidths of 5,

10, 15, 20 MHz, respectively.FPGA Clock Rate 368.64 MHz 3122.88 MHz.EVM for DDC 1% In absence of noise and

interferers.

Receive Filter Requirement Fpass = 0.9BW/2Fstop = BW/2Apass 0.1 dBAstop 80 dB

Fpass is the passband frequency.Fstop is the stopband frequency.Apass is the peak-to-peak ripple.Astop is the stopband attenuation.

Input Signal Quantization 14 bits Real input.Output Signal Quantization 18 bits I, 18 bits Q No Automatic Gain Correction

(AGC).First Stage Mixer Properties Tunability: None Fs/4 Mixer.Second Stage Mixer Properties(Used only in multi-carrier configurations)

Tunability: FixedResolution: 100 kHzSFDR: Ideal

Use simplified DDS based on 100 kHz raster.

Transmit Downlink Design & Implementation


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Performance RequirementsSpectral Mask RequirementsThe spectral mask requirements used in the digital front-end design are derived from the LTE (also called E-UTRA) emission limits defined in [Ref 1]. The general LTE emission limits are listed in Table 3, and are summarized from the General LTE Emission Limits from Table 6.6.2.2-6 and Table 6.6.2.2-12 of [Ref 1].

Table 4 shows the additional LTE emission limits generated from Table 6.6.2.2-7 and Table 6.6.2.2-13 of the same volume [Ref 1].

The maximum BS power is 43 dBm for 5-MHz carrier and 46 dBm for 10-MHz, 15-MHz, and 20-MHz carrier, given in the Table 4.6 of [Ref 3].The spectral mask requirement for 5-MHz, 10-MHz, 15-MHz, and 20-MHz bandwidths, respectively, can be calculated given the combined general LTE emission limits and the additional LTE emission limits shown in these tables. Select the most stringent requirement of the four plus 15 dB as the spectral emission mask, so enough margins are guaranteed and the design for various bandwidths configurations can share the same channel filter. The spectral mask requirements are listed in Table 5.

Adjacent Channel Leakage RatioAdjacent Channel Leakage Ratio (ACLR) is defined as the ratio of the in-band power to the power in adjacent LTE carriers.

Table 3: General LTE Emission Limits Frequency Offset to

Measurement Maximum Power in

Measurement Measurement

Filter Edge (-3 dB cutoff) Bandwidth Bandwidth0 MHz to 5 MHz -7 dBm -14 dBm 100 kHz

5 MHz to 10 MHz -14 dBm 100 kHz

> 10 MHz -15 dBm 1 MHz

Table 4: Additional LTE Emission Limit

Frequency Offset to Measurement Filter Edge (-3 dB cutoff)

Maximum Power in Measurement

BandwidthMeasurement

Bandwidth

0 MHz to 1 MHz BW = 5 MHz -15 dBm 30 kHz

BW = 10 MHz -13 dBm 100 kHz



> 1 MHz -13 dBm 1 MHz

Table 5: Spectral Mask Requirements for LTE (5/10/15/20 MHz BW)For |f| Within the Range Minimum Attenuation (dB) Attenuation with 15 dB Margin (dB)

0 MHz to 1 MHz 40 55

1 MHz to 10 MHz 50 65

> 10 MHz 52 67



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The power in an adjacent channel is measured with a rectangular filter with a bandwidth equal to 180 kHz transmission bandwidth configuration (NRB), centered on the first or second adjacent channel (corresponding to ACLR1 and ACLR2). For 5-MHz, 10-MHz, 15-MHz, and 20-MHz LTE carriers, NRB is equal to 25, 50, 75, and 100, respectively. Therefore, the corresponding rectangular filter bandwidth is 4.5-MHz, 9-MHz, 13.5-MHz, and 18-MHz, respectively. The minimum requirement is listed in the section 6.6.2.3.1 of 3GPP TS 36.804 [Ref 1]. The limits for ACLR1 and ACLR2 are both 45 dB. In the reference design, 60 dB is specified as the minimum ACLR requirement to provide 15 dB margin.

Error Vector MagnitudeFor an LTE system, the reference point in the receiver for Error Vector Magnitude (EVM) measurement is at the point after the Cyclic Prefix (CP) removal, FFT, and subcarrier amplitude and phase correction, as shown in Figure 3.

The basic unit of EVM measurement is defined over one subframe in the time domain (1 ms) and one resource block which contains 12 data subcarriers (180 kHz) in the frequency domain for frame structure type 1. To test against the EVM requirements, the Root Mean Square (RMS) average of individual EVM is calculated over 10 consecutive downlink subframes (10 ms) and all allocated resource blocks in the frequency domain for both FDD and TDD frame structure type 1. This can be expressed in Equation 1 as:

Equation 1Where:

is the number of resource blocks is the EVM for ith subframe and jth resource block.

For a more detailed definition, refer to section 6.8.1 of the 3GPP TR 36.804 v0.7.1 (2007-10) [Ref 1].Separate EVM requirements are specified for different modulation schemes: For 64 QAM modulation, a range of 7 ~ 8% is the proposed EVM requirement.


Figure 3: Reference Point for EVM Measurement on an LTE SystemX1123_03_100108

Pre/Post FFTTime/Frequency

Sync

Pre Sub-carrierAmplitude/Phase

Correction

Reference Pointfor EVM

Measurement

Base StationUnder Test

Cyclic PrefixRemoval

SymbolDetection/Decoding

FFT

102,10

1 1

1

1 iNi j

i ji

i

EVM EVMN = =

=

=

iN

,i jEVM



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For 16 QAM and QPSK, 12.5% and 17.5% are the proposed minimum performance requirements.

Note: These figures are for the total system EVM, which includes the digital and analog portion. This application note uses the minimum requirements that EVM 2% at 8 dB PAPR, 4% at 7 dB PAPR, and 7% at 6 dB PAPR for digital portion and single carrier configurations.

Digital Up Converter ArchitectureThis section describes the detailed architecture of major modules in the digital up-converter. Figure 4 shows the overview block diagram of the DUC.

Single Rate Channel FilterThe baseband data first has to pass the channel filter so that the out-of-band power is attenuated to meet the spectral mask requirements. Because the LTE baseband signal is OFDM-based, the power spectral density (PSD) of the input signal to the channel filter already has a natural attenuation starting from the edge of the occupied bandwidth (i.e., 90% of the total channel bandwidth). As shown in Figure 5, for 20-MHz bandwidth configuration, the PSD at 10-MHz frequency point is less than -30 dB compared to that at active bins. Similar PSD characteristics are observed for the 5-MHz, 10-MHz, and 15-MHz bandwidth configurations. To ensure the signal at the output of the channel filter can be down by up to 67 dB (as summarized in Table 6) outside the desired bandwidth, the channel filter needs to support additional ~40 dB attenuation.


Figure 4: Digital Up Converter ArchitectureX1123_04_100108

122.88Msps

Single-RateChannel

Filter

InterpolationFiltering 1

InterpolationFiltering 2

Mixing andCombining

(Multi-carrieronly)

FractionalResampling(1x15MHz

only)

7.6815.3623.0430.72Msps


Figure 5: PSD of the Baseband LTE Signal for 20-MHz Bandwidth



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Table 6 shows some useful properties for all four bandwidth settings, such as the number of usable subcarriers, subcarrier spacing, occupied bandwidth, and the ratio between occupied and total bandwidth. The DC subcarrier is unused. The following numbers are important when it comes to deciding the specification for the channel filter: The passband for the channel filter (Fpass) must be at least BWoccupied/2. The stopband (Fstop) should be BWtotal/2. Because the normalized passband and stopband frequencies, i.e., pass= Fpass/(Fs/2)and stop= Fstop/(Fs/2), respectively, are identical for the four bandwidths, the same channel filter can be shared across configurations.

Table 7 summarizes the channel filter design parameters. It is a single-rate filter with a total of 81 taps. A channel filter with a rate change of 2 can be designed; however, the filter order can double (~160 taps) and does not necessarily result in an efficient implementation. The magnitude response of the channel filter is shown in Figure 6, where the filter coefficients have been quantized to 18 bits.The Fpass used in the Wpass calculation is 9.015 MHz, instead of 9 MHz. It makes the filter requirements more stringent (one more tap than if using 9 MHz) but it also ensures that the signal carried at the last active data bin can pass through. Also, this creates an odd numbers of taps and is preferable in an efficient filter implementation when it comes to speed and area consumption.

Table 6: Properties for Different Carrier Bandwidth Settings

Total BW (BWtotal)(MHz)

Fs (Msps) Usable SubcarriersSubcarrier

Spacing (kHz)

Occupied BW

(BWoccupied)(MHz)

BWoccupied/BWtotal *

100%

5 7.68 300 15 4.5 90%

10 15.36 600 15 9 90%

15 23.04 900 15 13.5 90%

20 30.72 1200 15 18 90%

Table 7: Filter Parameters for the Channel FilterBW

(MHz) pass stopApass (dB)

Astop (dB) # Taps

5, 10, 15, 20

0.587(=9.015/(30.72/2))

0.651(=10.0/(30.72/2))

0.035 45 81



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Interpolation FilteringAfter the channel filter, a cascade of interpolation filters follows to remove the aliasing effect produced by up sampling. The majority of the interpolation filtering chain is implemented using a cascade of halfband filters. Halfband filters are a type of FIR filter where its transition region is centered at one quarter of the sampling rate, Fs/4. The end of its passband and the beginning of the stopband are equally spaced on either side of Fs/4. When implementing an interpolation filter with a rate of two, the halfband filter is often the chosen structure of choice, because it requires much less computational power (and thus less hardware) for a filter realization. This results from the fact that every odd indexed coefficient in the time domain is zero except the center tap and even indexed coefficients are symmetric.In 1x5, 1x10, and 1x20 MHz BW configurations, the desired sampling rate (122.88 MHz) can be achieved by using a cascade of halfband filters. For 1x15 MHz, a rate 4/3 fractional resampler follows the halfband filters to convert the sampling rate from 92.16 Msps to 122.88 Msps. The main difference between the single carrier and multi-carrier configurations is that the interpolation filtering process for the multi-carrier configurations includes a mixing and carrier combining stage. For the 2x10 and 4x5 MHz bandwidth, this stage frequency shifts individual carriers to their relative positions, [-5, 5] and [-7.5, -2.5, 2.5, 7.5] MHz, respectively, in a 20-MHz bandwidth centered at 0 MHz. The composite signal is then processed with further halfband filters. For the 2x5 MHz, two carriers are first shifted to [-2.5, 2.5] MHz in a 10-MHz bandwidth centered at 0 MHz before the later halfband filtering. All filters were designed using the MATLAB Filter Design and Analysis Tool (FDATool). The seven reference designs share a similar filtering structure. The halfband interpolation filter parameters are identical. Table 8 summarizes the filter parameters for easy referencing and comparison.


Figure 6: Magnitude Response of Single-Rate Channel Filter

0 1 2 3 4 5 6 7-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0Magnitude Response of Channel Filter

Frequency (MHz)

dB



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1x5 MHz ConfigurationThe interpolation filtering chain for the 1x5 MHz configuration is shown in Figure 7.Each filter is a halfband interpolation filter with parameters as listed in Table 8. The equiripple halfband lowpass input parameters (in FDATool) are Fs, Fpass, and Apass. The passband cutoff frequency for all four halfband filters was set to 2.5 MHz to protect the entire 5 MHz band and remove the aliasing component completely. The number of taps is the length of the smallest filter that satisfies the requirements specified by the input parameters.

1x10 MHz ConfigurationThe interpolation filtering chain for the 1x10 MHz configuration is shown Figure 8 and the filter parameters are listed in Table 8. Because the passband cutoff frequencies (after normalizing to the filter sample rates) and the passband ripple for HB#1, HB#2, and HB#3 are identical to the ones for the 1x5 MHz configuration, the resultant filter coefficients are identical. The throughput requirement for each filter is doubled in implementation because the sample rates at each stage are doubled (see DUC Implementation section for further details).

1x15 MHz ConfigurationThe interpolation filtering chain for the 1x15 MHz configuration is shown in Figure 9, and the filter parameters are listed in Table 8. A fractional resampler with the rate of 4/3 is required to convert from the 92.16 Msps rate to the desired 122.88 Msps rate. To design the resampler, the standard polyphase filter design technique is used. The sampling frequency Fs is set to 92.164 = 368.64 Msps.

Table 8: Filter Parameters for Reference Design Configurations

Filter Fs (Msps)Fpass (MHz)

Fstop (MHz) Apass (dB)

Astop (dB) # Taps

HB #1 15.36 2.5 0.01 23

HB #2 30.72 2.5 0.01 11

HB #3 61.44 2.5 0.01 7

HB #4 122.88 2.5 0.01 7

Fractional Resampler

368.64 7.5 84.66 0.01 80 19


Figure 7: Interpolation Filter Structure for 1x5 MHz ConfigurationX1123_07_100108

15.36Msps

7.68Msps

HB #12

30.72Msps

HB #22

61.44Msps

HB #32

122.88Msps

HB #4

(23 taps) (11 taps) (7 taps) (7 taps)

2



15.36Msps

HB #12

30.72Msps

HB #22

61.44Msps

HB #32

122.88Msps

(23 taps) (11 taps) (7 taps)



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The passband frequency is set to 7.5 MHz to protect the entire 15 MHz band. The stopband frequency is 92.16-7.5=84.66 MHz to remove the aliasing image.

1x20 MHz ConfigurationFigure 10 shows the interpolation filtering chain for the 1x20 MHz configuration, and the filter parameters are listed in Table 8.

After normalizing to the sample rate, the filter coefficients are identical to those in the corresponding filter for the 1x10 MHz and 1x5 MHz configurations.

2x5 MHz ConfigurationFigure 11 shows the interpolation filtering chain for the 2x5 MHz configuration.

One major difference here from all the single carrier configurations is that signals from two complex channels need to be combined together to a total allocated bandwidth of 10 MHz. Because a zero IF architecture was assumed, two individual carriers are shifted to fixed frequencies at -2.5 and 2.5 MHz before combining. This simplifies the mixer design as the whole 10-MHz BW is centered at zero so that the multi-carrier mixer can be placed at the lowest possible sample rate. This helps to achieve a significant hardware resource saving. In the case of non-zero IF architecture, it requires a mixer at the end of the DUC chain (at the highest sample rate) to support the capability to shift to any frequencies.After channel filtering, signals from two complex channels enter the first halfband filter and are up-sampled to 15.36 Msps. This is the earliest point that two carriers are able to be combined together without triggering any aliasing effect because (Fs BWindividual_carrier) is greater than BWindividual_carrier. Here the sampling rate Fs is 15.36 MHz and BWindividual_carrier is 5 MHz.


Figure 9: Interpolation Filter Structure for 1x15 MHz Configuration



X1123_09_100108

23.04Msps

HB #12

46.08Msps

HB #22

92.16Msps

FractionalResamplerP/Q = 4/3

122.88Msps

(23 taps) (11 taps) (19 taps)

X1123_10_100108

30.72Msps

HB #12

61.44Msps

HB #22

122.88Msps

(23 taps) (11 taps)



7.68Msps

HB #1

2 ComplexChannels

215.36Msps

HB #22

61.44Msps

2-CarrierMixing

& Combiningto

10 MHz BW

122.88Msps

(23 taps)2 Carriers Centered at

[-2.5, 2.5] MHz(11 taps)

HB #32

(7 taps)

15.36Msps

HB #12

30.72Msps

(23 taps)



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After the mixing and combining process, the composite signal is treated as data from one carrier so that the rest of the halfband filters only require supporting a single complex channel. The PSD for 2x5 MHz LTE data after multi-carrier mixing is shown in Figure 12.

The resource trade-off is an important consideration when designing multi-carrier filter structures. Pushing the mixer and combiner to the earlier stage in the DUC chain will increase the complexity of the polyphase filters that are to follow.In this example, instead of using the 11-tap halfband interpolator as shown in 1x5 MHz configuration in Figure 7, this architecture requires a 23-tap halfband filter immediately after the mixer to support the (doubled) 10 MHz total BW. This halfband filter has the same specification as the first filter immediately following the channel filter (both are HB #1), as their normalized passband frequencies are equivalent. The passband of the rest of the halfband filters is doubled. The advantage is that the filtering process only needs to apply to one complex channel instead of two, if mixing and combining at the later stage. The filter parameters are listed in Table 8. The mixer and combiner designs are detailed in Multi-Carrier Mixing and Combining, page 14.

2x10 MHz ConfigurationFigure 13 shows the interpolation filtering chain for the 2x10 MHz configuration and the filter parameters are listed in Table 8. Similar to the 2x5 MHz configuration, signals from two complex channels are shifted to fixed frequencies at -5 MHz and 5 MHz before combining, and this is done at the lowest possible sample rate domain 30.72 MHz. Again, instead of using the 11-tap halfband interpolator, this architecture requires a 23-tap halfband filter after the mixer to support 20 MHz total BW. This halfband filter has the same specification as the first filter immediately following the channel filter (both are HB #1).


Figure 12: PSD after Multi-Carrier Mixing @ 15.36 MHz for 2x5 MHz Configuration

-6 -4 -2 0 2 4 6-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency (MHz)

Wat

ts/H

z (dB

)

Power Spectral Density for LTE Data @ 15.36MHz



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Figure 14 shows the PSD for the 2x10 MHz LTE data after multi-carrier mixing.

4x5 MHz ConfigurationFigure 15 shows the interpolation filtering chain for the 4x5 MHz configuration and the filter parameters are listed in Table 8, page 14.

The multi-carrier output signal has a total allocated bandwidth of 20 MHz. After channel filtering, signals from four complex channels first enter two stages of halfband filter and are up-sampled to 30.72 Msps. Signals are shifted to fixed frequencies at -7.5 MHz, -2.5 MHz, 2.5MHz, and 7.5 MHz before combining. Figure 16 shows the PSD. This is the earliest point that four carriers are able to be combined without any aliasing effect because 30.7210 > 10. After the mixing and combining process, the





X1123_13_100108

15.36Msps

HB #1

2 ComplexChannels

230.72Msps

HB #22

122.88Msps

2-CarrierMixing

& Combiningto

10 MHz BW(23 taps)

2 Carriers Centered at[-5, 5] MHz

(11 taps)

30.72Msps

HB #12

61.44Msps

(23 taps)

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)Power Spectral Density for LTE Data @ 30.72MHz


Figure 15: Interpolation Filter Structure for 4x5 MHz ConfigurationX1123 15 100108

7.68Msps

HB #1

4 ComplexChannels

215.36Msps

HB #22

122.88Msps

4-CarrierMixing

& Combiningto

20 MHz BW(23 taps)

4 Carriers Centered at[-7.5, -2.5, 2.5, 7.5] MHz

(11 taps)

HB #22

30.72Msps

(11 taps)

30.72Msps

HB #12

61.44Msps

(23 taps)



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signals are treated as data from one carrier and the rest of the halfband filters operate on one complex channel.

DUC Filtering Overall Gain

The single rate channel filter was designed to have a unity gain (the sum of all the coefficients is 1). The halfband interpolators were designed with a filter gain of 2 (center tap equals to 1), so that with the zero insertion between samples in the up-sampling process, the average output signal power is maintained to be the same as that of the input signal. Therefore, for 1x5, 1x10, and 1x20 MHz configurations, the DUC filtering process has an overall gain of 0 dB. For 1x15 MHz configuration, the fractional resampling process generates a gain of 1.104. This results in an overall gain of 0.86 dB. For multi-carrier configurations, the up-sampling process for each carrier also preserves a 0 dB gain. With N active carriers, the composite output average amplitude is sqrt(N) times the individual input signal average amplitude. For example, in four carrier [1 1 0 1] configuration, the output signal average amplitude is expected to be sqrt(3) 1.7321 higher than the average amplitude of the input signal from each carrier.

Multi-Carrier Mixing and CombiningThis section describes the architecture of the multi-carrier mixing and combining that is embedded in the interpolation filter chains for the 2x5, 2x10, and 4x5 MHz configurations. In this zero-IF DUC architecture, this operation frequency shifts individual carriers to their relative positions in a given bandwidth centered at 0 MHz. The architecture of the mixing and combining module used in the 4x5 MHz configuration is described as an example. Figure 17 illustrates the 4-channel mixing and combining module.



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The input to the mixing and combining module is four complex signals sampled at 30.72 Msps. The mixer multiplies four input signals x0(n), x1(n), x2(n), and x3(n) by exp(j0n), exp(j1n), exp(j2n), and exp(j3n), respectively, and then sums the product up to generate a complex composite output signal, where the k represent the carrier center frequencies. The real (I channel) and imaginary (Q channel) components of the output signals are given by Equation 2 and Equation 3:

Equation 2

Equation 3Similar to the DDC, the rasterized DDS is used to generate the sine and cosine waveforms used in the above equations. The detailed discussion on the rasterized DDS concept can be found in the Multi-Carrier Mixing and Combining.

Crest Factor Reduction ArchitectureThe LTE DFE downlink design uses a peak cancellation crest factor reduction (PC-CFR) method to reduce the high PAPR signal at the output of the DUC. This section gives an overview of the PC-CFR algorithm and architecture. For more detailed information on the PC-CFR, refer to [Ref 4].


Figure 17: 4-Channel Mixing and Combining ModuleX1123_17_100108

Channel 0Complex

Input

c0

c1

Channel 1Complex

Input

c2

Channel 2Complex

Input

4-ChannelComposite

Complex Output

c3

Channel 3Complex

Input

X

X

X

X

+

3

0( ) ( ( ) cos( ) sin( ))

k kI I k Q kk

y n x n n x n =

=

3

0( ) ( ( ) cos( ) sin( ))

k kQ Q k I kk

y n x n n x n =

= +



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Algorithm OverviewThe peak cancellation method of CFR reduces the peak to average power ratio (PAPR) of a signal by subtracting spectrally shaped pulses from signal peaks that exceed a specified threshold. The cancellation pulses are designed to have a spectrum that matches that of the CFR input signal and, consequently, introduces negligible out-of-band interference. Each cancellation pulse is rotated to match the phase of the corresponding signal peak. The magnitude of a given cancellation pulse is set equal to the difference between the corresponding signal peak magnitude and the desired clipping threshold. This reduces the signal peak magnitudes to the threshold value while preserving the signal phase.Figure 18 illustrates the peak cancellation process in the time domain. Note: The blue curve shows a section of the input signal magnitude before the CFR iteration. The cyan horizontal line overlaid on the plot indicates the clipping threshold. Any peak that exceeds this threshold is a candidate for cancellation. The magenta curve shows the magnitude of the output signal after subtracting the cancellation pulse from the input signal.

ArchitectureFigure 19 shows a block diagram of the PC-CFR algorithm. Peaks in the input signal are detected and cancelled to produce a reduced PAPR signal. The peak detect block works on the signal magnitudes to produce a peak location indicator along with magnitude and phase information for each peak. The difference between the peak magnitudes and the clipping threshold is generated by the peak scaling block. The magnitude difference is combined with the phase information to produce the complex weighting that is used to scale the cancellation pulse coefficients. It is this scaling that replaces the more computationally intense convolution that is used in the noise shaping method. Each cancellation pulse generator (CPG) outputs an unscaled version of the cancellation pulse waveform aligned with a peak location. Each CPG can cancel only one peak at a time. The length of the cancellation pulse combined with the number of CPGs determines the rate at which signal peaks can be cancelled. The allocator block controls the distribution of CPGs to incoming peaks. When a new peak is detected the allocator assigns an available CPG to the cancellation of that peak. If all CPGs are busy when a new peak is detected, it will not be cancelled. Multiple iterations of the algorithm are necessary to eliminate the peaks that were not cancelled during an earlier pass of the


Figure 18: Time Domain View of Peak Cancellation

4.45 4.455 4.46 4.465 4.47 4.475 4.48

x 104

0

0.5

1

1.5

2

2.5

3

3.5

4x 104 Signal Magnitude Before and After CFR Iteration

Time (Samples)

Sign

al M

agnitu

de

InputOutput



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algorithm. The final algorithm step is to subtract the summation of the CPG outputs from a delayed version of the input signal.In the 3GPP LTE reference design, two iterations of the PC-CFR algorithm were used: For single carrier configurations, each iteration consists of three CPGs to achieve

acceptable performance, while resulting in slightly lower area than the multi-carrier configuration.

For multi-carrier configurations, six CPGs were used in the first iteration and another 3 CPGs in the second iteration to eliminate most of the peaks and achieve a satisfactory output PAPR.

Designing Cancellation PulseThe cancellation pulse coefficients can be obtained using any preferred filter design methodology and are computed offline before being written to the PC-CFR. Memory that is external to the design can be used to store multiple sets of cancellation pulse coefficients corresponding to predetermined carrier configurations. Transferring a selected set of coefficients into the PC-CFR memory can be handled with some simple multiplexing circuitry. For multi-carrier configurations, it is useful to first design a prototype filter that is matched to the spectrum of a single carrier. Frequency shifted replicas of the prototype filter are then placed at each carrier center frequency before being summed to create a composite multiband filter. In the 3GPP LTE reference design, the prototype filter was obtained using the firls function in MATLAB. The order of the filter is fixed at 254 (255 taps). Table 9 lists the passband and stopband frequency of the prototype filter. The command prototype_filter_coeff = firls(N, [0 Fpass Fstop Fs/2]/(Fs/2), [1 1 0 0], [Wpass Wstop]) generates the prototype filter coefficients.


Figure 19: Block Diagram of PC-CFR Method (One Iteration)

Table 9: Prototype Filter for Designing Cancellation Pulse Coefficients Bandwidth

(MHz)Fs

(Msps)Fpass (MHz)

Fstop (MHz)

Wpass (dB)

Wstop (dB)

Filter Order (N)

5 7.68 2 2.5 1 50 254

10 15.36 4.5 5 1 50 254

X1123_19_100108

HighPAPRSignal

ReducedPAPRSignal

Delay

PeakDetect

PeakScaling

Allocator CPG #1

CPG #2Sum

CPG #N

+

PeakLocations

MagPhase

X

X

X

+



R

To generate the cancellation pulse coefficients, first the prototype filter coefficient is rotated to respective carriers, for example, multiply it by exp(j*2*pi*Fc*k/Fs) where:

Fc = 0 for single-carrier configurations, Fc = [-2.5, 2.5] in 2x5 MHz case, Fc = [-5, 5] in 2x10 MHz case Fc = [-7.5, -2.5, 2.5, 7.5] in 4x5 MHz case, k is integer, from -# of taps/2 to # of taps/2.

Then, sum all the rotated coefficients together to obtain the CP coefficients.

System PerformanceThis section summarizes the performance of the LTE transmit downlink using PC-CFR method. In all cases, the length of the cancellation pulse is 255, and the cancellation pulse was designed using the least squares filter design method, for example, the firls function in MATLAB, with Fpass = 0.9*BW/2 for 10, 15, and 20 MHz BW, Fpass = 0.8*BW/2 for 5 MHz BW, and Fstop = BW/2. The detailed parameters are described in the Designing Cancellation Pulse. Results are presented based on using two iterations of the algorithm, because no improvement was observed using three or more iterations.

Single-Carrier ConfigurationTable 10 shows the output PAPR and PAPR reduction (dPAPR) versus EVM performance of the PC-CFR algorithm for single carrier configurations. The number of cancellation pulse generators is three for both iterations. All PAPR results are referenced at the 0.01% probability of clip point. With 8 dB PAPR target, less than 2% EVM can be achieved. With 7 dB PAPR target, the EVM is below 4%. The EVM is below 7% when the output PAPR is 6 dB. ACLR1 and ACLR2 meet the 60 dB requirement.

Compared to other CFR methods, such as the Peak Windowing CFR (PW-CFR) and Noise Shaping CFR (NS-CFR), it can be concluded that the PC-CFR performance is slightly better than that of the NS-CFR algorithm, and significantly better than the PW-CFR algorithm. Figure 20 shows the performance comparison based on 1x10 MHz configuration.

15 23.04 6.75 7.5 1 50 254

20 30.72 9 10 1 1 254

Table 10: PC-CFR Performance for Single-Carrier Configurations

Configuration Input PAPR(dB)Output PAPR

(dB)dPAPR

(dB) EVM (%)ACLR1/ACLR

2 (dB)2x10 9.55 8 1.55 1.74 74/82

7 2.55 3.82

6 3.55 7.11

2x5 9.5 8 1.5 1.85 68/767 2.5 3.94

6 3.5 7.43

Table 9: Prototype Filter for Designing Cancellation Pulse Coefficients (Contd)Bandwidth

(MHz)Fs

(Msps)Fpass (MHz)

Fstop (MHz)

Wpass (dB)

Wstop (dB)

Filter Order (N)



R

The PW-CFR method is described in [Ref 5]. The NS-CFR method is described in [Ref 6]. A link to this document can be found in References, page 87.Two iterations are used for both the NS-CFR and PC-CFR methods, while PW-CFR used a 401 tap window. Given the same EVM, the PC-CFR method can provide the highest PAPR reduction of the three.The following three figures are based on 1x10 MHz configuration: Figure 21 shows a plot of the CCDF for the CFR input and output at the 4% EVM

operating point for 1x10 MHz configuration. The curve demonstrates that the PAPR reduction is around 2.72 dB at the 0.01% (1E-4) probability of clip point.

Figure 22 shows the power spectral density (PSD) estimates of the CFR input and output for the single carrier at the 4% EVM operating point.

Figure 23 shows the constellation plot for 64-QAM modulation.


Figure 20: Performance Comparison among Several CFR Methods (1x10 MHz)

1 2 3 4 5 6 7 8 9 105.5

6

6.5

7

7.5

8

8.5

EVM (%)

Out

put P

APR

(dB)

CFR Performance Comparison for 10 MHz BW

PW-CFRNS-CFR (2 iterations)PC-CFR (2 iterations)



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Figure 21: CCDF of CFR Input and Output with Two Iterations of PC-CFR (1x10 MHz)X-Ref Target - Figure 22

Figure 22: PSD of CFR Input and Output with Two Iterations of PC-CFR (1x10 MHz)

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10-4

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100CCDF

PAPR (dB)

Clip

ping

Pro

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lity

Before Clipping: PAPR (@1E-4) = 9.67 dB After Clipping: PAPR (@1E-4) = 6.95 dB

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Dual-Carrier ConfigurationTable 11 shows the output PAPR and PAPR versus EVM performance of the PC-CFR algorithm when using two iterations for the dual carrier configurations (2x5 and 2x10).The PAPR of the CFR input signal is 9.5 dB and 9.55 dB at the 0.01% probability of clip point for 2x5 and 2x10 BW options, respectively.The number of cancellation pulse generators is six for the first iteration, and three for the second iteration. Both ACLR1 and ACLR2 meet the 60 dB requirement.For the PAPR reduction, fewer than 2% EVM can be achieved with 8 dB output PAPR. With 7 dB PAPR target, the EVM is within 4%.When the output PAPR is 6 dB, the EVM is over 7%, which is higher than the single carrier case due to the destructive effect generated from the adjacent carrier.


Figure 23: Constellation Plot for 64 QAM (1x10 MHz) 4% EVM

Table 11: PC-CFR Performance for Dual-Carrier Configurations

Configuration Input PAPR(dB)Output PAPR

(dB)dPAPR

(dB) EVM (%)ACLR1/ACLR2

(dB)2x10 9.55 8 1.55 1.74 74/82

7 2.55 3.82

6 3.55 7.11

2x5 9.5 8 1.5 1.85 68/767 2.5 3.94

6 3.5 7.43



R

Figure 24 shows a plot of the CCDF for the CFR input and output when the output PAPR is 7 dB for 2x10 MHz configuration. The EVM at 0.01% clipping probability operating point is 3.82%.

Figure 25 shows the PSD estimates of the CFR input and output for the 2x10 MHz configuration.


Figure 24: CCDF of CFR Input and Output with Two Iterations of PC-CFR (2x10 MHz)


Figure 25: PSD of CFR Input and Output with Two Iterations of PC-CFR (2x10 MHz)

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10-5

10-4

10-3

10-2

10-1

100CCDF

PAPR (dB)

Clip

ping

Prob

abilit

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Four-Carrier ConfigurationTable 12 shows the output PAPR and dPAPR versus EVM performance of the PC-CFR algorithm when using two iterations for the 4x5 MHz configuration. Because the reference design offers the option to turn on and off each carrier, this configuration includes possible scenarios like three active carriers with one non-adjacent carrier, such as [1 1 0 1] or [1 0 1 1], or two non adjacent carriers, such as [1 0 0 1], and the typical four active carriers [1 1 1 1] carrier settings. Similar to the dual carrier configuration, the number of cancellation pulse generators is six for the first iteration, and three for the second iteration.

In the 4x5 MHz configuration the output PAPR vs. EVM performance is worse than all other configurations, though the ACLR1 and ACLR2 still meet the 60 dB requirement. In four active carriers setting, although less than 2% EVM can still be achieved with 8 dB PAPR and 4% EVM for 7 dB output PAPR, the CCDF curve for 6 dB output PAPR will be curved outwards to high PAPR region at 1e-5 and 1e-6 clipping probability as shown in Figure 27 (instead of a straight line down as the red curve in Figure 26). This is non-ideal as this causes a problem for processing in the digital pre-distortion (DPD) block to follow. Consequently, the minimal achievable (stable) output PAPR is approximately 6.5 dB.

Table 12: PC-CFR Performance for 4x5MHz Configuration

Configuration Allocation SpacingInput PAPR(dB)

Output PAPR (dB)

dPAPR(dB)

EVM (%)

ACLR1/ACLR2 (dB)

Four Active Carriers for example [1 1 1 1]

None or [10, 5]

9.7 8 1.7 1.91 66/757 2.7 4.00

6.5 3.2 5.5

Three Active Carriers with One Non-adjacent Carrierfor example [1 1 0 1] or [1 0 1 1]

None 9.64 8 1.64 2.45 63/767 2.64 5.10

6.7 2.94 6.42

[10, 5] 8 1.64 2.367 2.64 4.81

6.7 2.94 6.00

Two Non-adjacent Carriersfor example [1 0 0 1]

None 9.6 8 1.6 4.11 66/667 2.6 9.57

6.7 2.9 11.80

[10, 5] 8 1.6 2.657 2.6 5.67

6.7 2.9 6.88



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In any non-adjacent carrier setting, the allocation spacing technique must be used to reduce the EVM given certain output PAPR. For example, in a [1 1 0 1] or [1 0 1 1] case, 5.1% EVM was seen to achieve 7 dB of output PAPR, but with the help of allocation spacing, the EVM metric can be reduced to 4.81%, almost 0.3% improvement. The worst case scenario happens in two active carrier with two middle carriers inactive setting, such as [1 0 0 1]. In this case, to achieve 7 dB output PAPR causes almost 10% EVM. This is much improved with the allocation spacing technique, and nearly 4% improvement is seen at 7 dB output PAPR operation point. The optimal allocation spacing is [10, 5], meaning space of 10 is used for the first iteration and 5 is used for the second iteration.


Figure 26: CCDF of CFR Input and Output with [1 1 1 1] Carrier Configuration, 4% EVMX-Ref Target - Figure 27

Figure 27: Non-ideal CCDF Curve with [1 1 1 1] Carrier Configuration

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Figure 28 illustrates the input and output PSD for [1 0 0 1] configuration at a fixed 4% of EVM.

Implementation The transmit downlink was implemented using Xilinx System Generator version 10.1.2. The top-level GUI lets you select from one of seven carrier configurations as shown in Figure 29. The DUC and CFR module settings under the mask change accordingly based on different carrier configurations. The Power Meter block is an optional module and can be turned on and off from the top-level GUI.


Figure 28: PSD of CFR Input and Output with [1 0 0 1] Carrier Config, 4% EVM


Figure 29: System Generator Top-Level GUI of Transmit Downlink Design

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Under the mask is the block diagram of transmit downlink design. Figure 30 shows the diagram of the 4x5 MHz configuration as an example. There are three major blocks in the design: a DUC configuration subsystem, a rate and data format conversion block, and a PC-CFR module (pc_cfr_3x), which are described in the following subsections.

DUC ImplementationThe DUC was implemented with a heavy reliance on the FIR Compiler v4.0. The top-level DUC architecture uses a configurable subsystem to select from one of seven unique architectures that are stored in a Simulink library. See the Xilinx reference, System Generator for DSP User Guide, Release 10.1.2 [Ref 12], for a description of using configurable subsystems in System Generator designs. Because the carrier and BW configuration are determined by the choice in the top-level GUI as shown in Figure 29, the Block Choice menu item changes automatically and the user does not need to (and is not able to) make a selection on this level.


Figure 30: System Generator Block Diagram of Transmit Downlink for 4x5 MHz Configuration

vin In

threshold In

rst3

Out

rst1

Out

reset In

rate and data format conversion

din_i

din_q

vin

rst_1

dout_i

dout_q

vout

rst_3

power Out

pc_cfr_3x

data_i_in

data_q_in

data_sync

threshold

alloc_spacing1

alloc_spacing2

filter _numtaps

filter _ram_addr

filter _ram_data

filter _ram_we

reset

data_i_out

data_q_out

data_valid

ce_3_out

gain _we In

gain _ch In

gain In

filter _ram _we In

filter _ram _data In

filter _ram _addr In

filter _numtaps In

duc _valid

Out

duc _q Out

duc _i Out

din In

coefficients

coef

cfr_valid Out

cfr_q Out

cfr_i Out

ce_3_out Out

alloc _spacing 2 In

alloc _spacing 1 In

reset3

cfr_vout

cfr_q

duc _vout

duc_q

duc _i

power

ce_3_out

reset

cfr_i

tx_data

reinterpret

reinterpret

reinterpret

reinterpret

reinterpret

DUC Configurable SubsystemDUC_4x5

din

vin

reset

gain

gain_we

gain_ch

dout_i

dout_q

vout

power

rst_out

-C-

thresh

255

0

0

-C-

0



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Figure 31 shows the DUC configuration subsystem.

Figure 32 shows another GUI that allows you to add or remove the gain block on the DUC configuration subsystem level if you choose any of the single carrier configurations (1x5, 1x10, 1x15 or 1x20 MHz) on the top-level. The default setting is off. For multi-carrier cases, the gain block always exists and cannot be removed. This is because the gain block also can be used to turn on and off certain carriers.The seven architectures are based on the structures described in the Digital Up Converter Architecture, page 11. The following diagrams provide block diagrams of two configurations: Figure 33, page 32 shows the System Generator block diagram for the 1x15 MHz

configuration. Figure 34, page 32 shows the System Generator block diagram for the 4x5 MHz

configuration.In the single-carrier configurations, the data flow from one module to the next is handled in a Time Division Multiplexing (TDM) fashion except for the last module. The valid in (vin) and valid out (vout) signal is paired with TDM data input (din) and TDM data output (dout), respectively, to indicate the signal availability. Because the output of the DUC needs to feed into the CFR module, the I and Q data of the last module are separate and use some time division demultiplexing logic.There is a higher level of design complexity in the multi-carrier configurations due to the existence of the mixer. For all the modules before the mixer, the data input and output stream


Figure 31: System Generator DUC Configuration Subsystem



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is handled in a TDM manner. However, the efficient mixer design and the final few FIR compilers sometimes generate non-uniform output data, and some data scheduling and FIFO are required in these special situations.


Figure 32: GUI for Single Carrier DUC ConfigurationX-Ref Target - Figure 33

Figure 33: System Generator Block Diagram of DUC for 1x15 MHz ConfigurationX-Ref Target - Figure 34

Figure 34: System Generator Block Diagram of DUC for 1x15 MHz Configuration

rst_out5

power4

vout3

dout _q2

dout _i1

power _meter

I

Q

valid

rst

power

input reg

h_frac _2ch

din

vin

ch

reset

dout_i

dout_q

vout

h_channel

din

vin

reset

dout

vout

h2_2ch

din

vin

reset

dout

vout

ch

h1_2ch

din

vin

reset

dout

vout

Gain Stage SCno_gain_stage

din

vin

gain

reset

dout

vout

gain _ch6

gain _we5

gain4

reset3

vin2

din1

rst_out5

power4

vout3

dout _q2

dout _i1

power _meter

I

Q

valid

rst

power

mixer

din

vin

reset

dout

vout

input reg

h_channel

din

vin

reset

dout

vout

chout

h2_8ch

din

vin

reset

dout

vout

h2_2ch

din

vin

chin

reset

dout_i

dout_q

vout

h1_8ch

din

vin

reset

dout

vout

h1_2ch

din

vin

reset

dout

vout

chout

gain _ctrl

din

vin

chin

gain

gain_we

gain_ch

reset

dout

vout

gain _ch6

gain _we5

gain4

reset3

vin2

din1



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Channel Filtering and InterpolationThis section summarizes the Filter Compiler 4.0 settings for each filter used in each of the seven configurations in the transmit downlink. In all cases, the number of coefficient sets is equal to one and the reloadable coefficient

option is disabled. All filter architectures are based on the systolic multiply accumulate structure with 18-bit

signed coefficients. The setting for the coefficient structure is generally set as Inferred except in the 2x10

and 4x5 MHz cases, where it is set to Non-Symmetric for better resource balancing and speed advantage.

The optimization goal is always left at the default setting of Area. The data buffer type and coefficient buffer type are left at the default setting of

Automatic. All filters in the design use the rst and nd control options.Table 13 through Table 19 list the FIR compiler settings for 1x5, 1x10, 1x15, 1x20 2x5 2x10, 2x15, 2x20, and 4x5 MHz configurations.

Table 13: FIR Compiler Settings for 1x5 MHz Configuration

Parameter Channel Filter 1st

Halfband 2nd

Halfband3rd

Halfband4th

Halfband

Coefficients h_chan h1_duc h2_duc h3_duc h3_ducFilter Type Single_Rate Interpolation Interpolatio

nInterpolatio

nInterpolation

Rate Change Type Integer Integer Integer Integer IntegerInterpolation Rate Value

1 2 2 2 2

Number of Channels 2 2 2 2 1Effective Input Sample Period

24 24 12 6 6

Coefficient Structure Inferred Inferred Inferred Inferred InferredNumber of Paths 1 1 1 1 2

Output Width 18 17 17 17 17Optimization Goal Area Area Area Area Area

Table 14: FIR Compiler Settings for 1x10 MHz Configuration Parameter Channel Filter 1st Halfband 2nd Halfband 3rd HalfbandCoefficients h_chan h1_duc h2_duc h3_ducFilter Type Single_Rate Interpolation Interpolation Interpolation

Rate Change Type Integer Integer Integer IntegerInterpolation Rate Value 1 2 2 2

Number of Channels 2 2 2 1Effective Input Sample

Period12 12 6 6

Coefficient Structure Inferred Inferred Inferred InferredNumber of Paths 1 1 1 2



R

Output Width 18 17 17 17Optimization Goal Area Area Area Area


Parameter Channel Filter 1st Halfband 2nd

Halfband Resampler

Coefficients h_chan h1_duc h2_duc h_fracFilter Type Single_Rate Interpolation Interpolation Fixed_FractionalRate Change Type Integer Integer Integer IntegerInterpolation Rate Value 1 2 2 4Decimation Rate Value 1 1 1 3

Number of Channels 2 2 2 1Effective Input Sample Period

8 8 4 4

Coefficient Structure Inferred Inferred Inferred InferredNumber of Paths 1 1 1 2

Output Width 18 17 17 18Optimization Goal Area Area Area Area

Table 16: FIR Compiler Settings for 1x20 MHz Configuration Parameter Channel Filter 1st Halfband 2nd Halfband

Coefficients h_chan h1_duc h2_ducFilter Type Single_Rate Interpolation InterpolationRate Change Type Integer Integer IntegerInterpolation Rate Value 1 2 2Number of Channels 2 2 1Effective Input Sample Period 6 6 6Coefficient Structure Inferred Inferred InferredNumber of Paths 1 1 2

Output Width 18 17 17Optimization Goal Area Area Area

Table 14: FIR Compiler Settings for 1x10 MHz Configuration (Contd)Parameter Channel Filter 1st Halfband 2nd Halfband 3rd Halfband



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Parameter Channel Filter1st

Halfband2nd

Halfband3rd

Halfband4th

Halfband

Coefficients h_chan h1_duc h1_duc h2_duc h3_ducFilter Type Single_Rate Interpolation Interpolation Interpolation InterpolationRate Change Type Integer Integer Integer Integer IntegerInterpolation Rate Value

1 2 2 2 2

Number of Channels 4 4 2 2 2Effective Input Sample Period

12 12 12 6 3

Coefficient Structure Inferred Inferred Inferred Inferred InferredNumber of Paths 1 1 1 1 1

Output Width 18 17 18 18 17Optimization Goal Area Area Area Area Area


Parameter Channel Filter1st

Halfband2nd

Halfband3rd

Halfband 4th

Halfband

Coefficients h_chan h1_duc h1_duc h2_duc h3_ducFilter Type Single_Rate Interpolation Interpolatio

nInterpolation Interpolation

Rate Change Type

Integer Integer Integer Integer Integer

Interpolation Rate Value

1 2 2 2 2

Number of Channels

4 4 2 2 2

Effective Input Sample Period

12 12 12 6 3

Coefficient Structure

Inferred Inferred Inferred Inferred Inferred

Number of Paths 1 1 1 1 1

Output Width 18 17 18 18 17Optimization Goal

Area Area Area Area Area



R

Multi-Carrier Mixing and Combining

Four-Carrier MixerFigure 35 shows the System Generator block diagram of the four-carrier mixer and combiner. The input data sampling rate is 30.72 Msps and there are eight channel data (I and Q from

4 carriers) coming in from the last FIR compiler. With a 368.64 MHz FPGA clock and the input data throughput of 30.728 = 245.76 Msps,

data enters the mixer module in a bursty mode. 8 valid TDM samples come in during 12 clock cycles. The data is stored in a FIFO and is read out and mixed with the cosine and sine waveform

generated from the raster_dds_4ch block. It requires two DSP48Es for this mixer and combining operation, one for the in-phase

output and another for the quadrature output. Because there are still four empty cycles left, one cycle is used for the symmetric round

operation by the same DSP48E and no extra logic is required. The final TDM block assembles the resultant I and Q channel data in a TDM format to feed

into the next FIR compiler.


Parameter Channel Filter 1st

Ha

lte dfe app note

Documents

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design files

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