23Summer 2002 Yield Management Solutions

It’s A Small, Small, Small,Small WorldPart 1: Shrink Acceleration ThroughSuccessful Pattern Transfer

Harold Lehon, Jim Wiley, William Volk, Mike Slessor, Tony DiBiase, Ingrid Peterson, and Chris Mack, KLA-Tencor CorporationScott Ashkenaz

Repeating defects create enormous costs through yield loss, rework, lost time tomarket, and reduced customer satisfaction. The high cost of a repeating patterndefect has been well established, and a number of strategies have been implementedin fabs worldwide to reduce their impact. With low k1 lithography moving intovolume production for many device types, it is important to understand therequirements for managing pattern transfer under the significantly changed con-ditions that it creates. While all of the causes for repeaters in the higher k1 regimealso print at lower k1—and usually print more strongly—a number of significantnew defect mechanisms have also arisen. In some cases, it is also necessary toestablish new metrics to identify and describe these mechanisms and their impact.

IntroductionOne of the new measures that should be understood when determining reticlequality is its impact on the process window. Shrinking process windows withsmaller design rules challenge the lithographer, requiring significant efforts tomaximize the windows. Even a small deviation in energy on a reticle can collapse that window completely; yet, it is often difficult to identify locationson the reticle that may be probable causes, or even understand the “how” or“why” once the cause has been identified.

There is an ongoing debate about which defects require action, and which canbe ignored. For this paper, our discussion will focus on errors that result in (a)device failure; (b) a decrease in bin yield or performance; or, (c) a reduction inthe size of the process window within which the lithography process must bemaintained in order to produce high-performing devices. We will describe amethod by which the impact of a defect on both the process window and yieldentitlement can be quantified.

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24 Summer 2002 Yield Management Solutions

This paper will examine the newchallenges to pattern transfer pre-sented by low k1 lithography, andpresent best practices currentlybeing used in advanced semiconductorfabs worldwide to overcome thesechallenges. In several of these cases,KLA-Tencor has been working withwafer fabs to develop new tools toenhance pattern transfer manage-ment. These tools also help fabs toincrease their reticle defect-learningrate—the rate at which they respondto, and reduce—the frequency ofdefects occurring for a specificprocess or application. The bestpractices described in this paper are:

• Reticle inspection to identify andcharacterize defects on the reticlethat may create repeating defects onthe product including new typesof defects arising from the imple-mentation of low k1 lithography

• Optimization of the total fab lith-ography window, which providesthe maximum margin for reticlequality

• Identification of design rule errorsthat do not meet the requirementsof low k1 lithography and, therefore,result in reduced process windows,even when they are not classifiableas conventional reticle defects

Characterizing the reticleThe first line of defense againstrepeating pattern defects is charac-terization of the reticles that will beused for patterning. Throughout itslifetime—from the first use for devicecreation to reuse for subsequent pro-duction lots—the reticle should befree of defects that can cause devicefailure or reduce the lithographyprocess window. Reticle specificationsare established by the wafer fab thattypically refer to hard defects (chromepattern errors and glass defects), softdefects (contamination, crystalgrowth), and critical dimension

gates, contacts, vias, or interconnectsin a high-performance device that isexpected to generate significant rev-enue, the fab is more likely to char-acterize it upon receipt, and re-qualifyit before repeated production use.

Fabs that have implemented a spe-cific procedure for reticle manage-ment, with clearly defined frequen-cies and an appropriate database,have enjoyed numerous benefitsbeyond prevention of yield lossresulting from repeating defects.One such example is defect yieldlearning, which is a specific processthat is measured as an improvementrate over time and is well establishedin other fab process modules. Defectyield learning is driven by recordsthat are available for evaluation andthe systematic removal of defectsources. By tracking causes and theirfrequencies, it is possible for a fab toprioritize and focus its improvementefforts on the problems that have thegreatest impact until they are elimi-nated. Figure 1 shows an example of

errors. Ideally, the mask fabricatorcertifies the out-going quality of areticle with a reticle inspection toolthat provides both pattern and con-current all-surface contaminationinspection. An example of one ofthese tools is KLA-Tencor’s TeraStarSLF77, which provides both die-to-die and die-to-database inspection.

Incoming QualificationOnce this certification is complete atthe mask shop, and the reticle isshipped to the wafer fab, the fabshould check this reticle into inven-tory, characterize it, and then beginto use it. In practice, most fabs at0.18 µm design rules and smaller areperforming varying degrees of char-acterization for incoming reticles—from a select number of reticles usedfor critical-layer development to amajority of all reticles. The frequencyof this inspection depends on thevalue of the device being producedwith the reticle. For example, if thereticle is used on critical layers such as

C O V E R S T O R Y

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Pellicle improvements

Damaged Pellicle – OprDamaged PellicleContam – PellicleContam – glass sideContam – chrome side

Month

Figure 1. Reticle Defect Learning Rate – Here, this large DRAM manufacturer inspected critical

reticles every 300 wafers using the TeraStar SLF27. The reticle inspection identified sources for

the various defect types, and improvement efforts were prioritized accordingly.

25Summer 2002 Yield Management Solutions

Some defect types may slightlyreduce the energy transmittedthrough the reticle, due either totransmission issues or small patternerrors. This is especially problematicfor contact and via patterns, as wellas for some types of optical proximi-ty correction (OPC) where they canmean the difference between a work-ing device and a device that fails.TeraFlux on the TeraStar platform

(see sidebar on TeraFlux) offers thecapability to find energy errorssmaller than six percent during thenormal reticle inspection process(see Figure 3).

In some cases, the lithographer maywant to understand the likelyimpact of a defect on the IC pattern.There are a number of tools availablefor this exercise, including printabilityanalysis simulation software, wherethe high-resolution image from thereticle inspector is used to simulatethe likely effect of the defect withoutactually requiring the wafer to bepatterned. Printability analysis sim-ulation software, such as TeraSim,—which is powered by the PROLITHengine—provides the flexibility totake any defect detected at high res-olution and simulate the conditionsof the stepper, substrate, and resistto understand the defect’s printabil-ity and its subsequent impact on thelithography process window.2 Ofcourse, in some cases it may bepreferable to use the reticle to printa wafer in order to examine thedefect location directly using defectreview tools or to inspect it.

a memory fab that identified specificsources and took specific actions forimprovement. The fab identifiedcontamination sources as beingamong the primary defect types.Subsequent improvements weremade to reticle handling with SMIF,and with pellicles.

This characterization is carried outmost effectively through directinspection of the pattern and reticlesurfaces at high resolution. The fourcritical surfaces—pellicle outside,pellicle inside, patterned surfaces,substrate backside—are inspected toidentify pattern (hard) and contami-nation (soft) defects.1 This is typical-ly done in the wafer fab on a reticleinspection system such as theTeraStar SLF27 (see sidebar for adescription on TeraStar.) By usinghigh-resolution inspection, thedefect can be captured in full detail,providing sufficient information tofocus on eliminating its source. Ifthe impact of the defect is uncertain,it may be carefully reviewed usingmethods described below. Figure 2is an example of a hard defect on acontact that would have reduced theprocess window and resulted in yieldloss if left undetected.

C O V E R S T O R Y

Figure 2. Contact Hard Defect – A 60 nm reduction at the corner of the reticle is detected by

TeraStar SLF77. Here, the reference image is in the center, the defective image is at right, and the

calculated difference image is at left. The red box indicates the location of the error (from reference 1).

Figure 3. 130 nm Design Rule Contacts – A 6.5% energy dif ference was detected with TeraFlux

on TeraStar. The red boxes indicate the location of the errors. By having such a tight tolerance,

TeraFlux can identify errors that may not print under optimum conditions, but are likely to reduce

an already tight process window. This is very effective in characterizing new reticles, and ensuring

that reticles in inventory have not degraded.

26 Summer 2002 Yield Management Solutions

Arresting Reticle Degradation in the FabOnce a reticle has been characterizedand checked into inventory, the fabwill periodically re-qualify it toensure that the reticle does notdegrade over time. Probable causesof reticle degradation include conta-mination migration, new contami-nation, crystal growth, changes inorganic residues induced by high-energy photons, and static discharge.Fabs are also beginning to conductmore frequent re-qualification incases of lower wavelength exposure,where energy-related damage mayoccur. The rate of re-qualificationdepends on the fab and the criticalityof the reticle.3 A study conducted byGrenon Consulting suggests that asthe wavelength is reduced, re-quali-fication should increase significantly,as measured by the number of wafersexposed between qualifications (seeFigure 4). This may be explained bya combination of factors. Movementto a lower wavelength is driven bysmaller design rules and higherproduct value, and this also results ina decrease in critical defect size.Lower wavelengths—and, therefore,higher photon energies—may increasethe rate of degradation. While muchof the anecdotal data suggest thatreticle-handling events are the majorcause for degradation, there are also

STARlight signal

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CrystalESDParticleBad repairFissureResidue

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• Concurrent STARlight and Pattern Inspection

TeraStarSTARlight TechnologySimultaneous Transmitted And Reflected light

TeraStar Technology

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Figure 4. Reticle Maintenance Frequency—The

frequency of requalification, as measured by

wafer exposures between inspections, increases

with decreasing wavelength (Source: Grenon

Consulting, Inc.).

Chrome-sideDown

Back-sideGlass

FrontPellicle

TeraStar with URSA

27Summer 2002 Yield Management Solutions

lithographers have simplified theprocess of taking basic process win-dow measurements. Measuring thecommon process window, which iscommon across all critical featureson a device layer, remains the most

important—and challenging—taskat hand. To accurately measure thecommon process window, lithogra-phers must account for:

• Pattern variations across the reticle(process and writing variations)

a significantly higher percentage ofdegradation events related to thenumber of exposures being imple-mented using a given reticle. With300 mm wafers, for example, theincreased number of exposures thatare needed per wafer may contributeto an increased degradation rate. Thesmaller lot sizes, or increased han-dling per wafer exposure that areassociated with these larger wafers,may also be a contributing factor.

Maximizing the usableprocess windowImplementing low k1 lithographyand controlling the lithographyprocess within collapsing processwindows is a constant struggle.While a number of techniques such asoff-axis illumination (OAI), opticalproximity correction (OPC), phase-shift masks (PSM), and lower wave-length exposure, help to open thewindow, the reduced process marginspresent a significant challenge. Witha focus on the reticle, there are anumber of issues, including classi-cally defined defects, which canreduce that window. While adjust-ments to the sigma and numericalaperture (NA) of the scanner can helpoptimize the process window, under-standing and optimizing reticlesrules may still be necessary in orderto maximize the usable window.

In an advanced fab, active manage-ment of the lithography processwindow is critical to the overallyield, speed binning, productivity, andprofitability. To quantify the impactthat a defect from a critical-layer reticlecan have on the process window, thelithographer should first calculate theprocess window. Only then is it pos-sible to quantify any reduction in yieldentitlement and make appropriatedecisions based on benchmarked data.

The Common Process WindowBy using CD metrology tools, combined with integrated analysis,

TeraFlux descriptionLow k1 lithography and high MEEF increase process sensitivity to smallerrors on the reticle. This is especially true on small closed features such ascontacts, gates, and vias.11, 12, 13 While the errors may fall within the CDspecification, the error of transmitted energy may still be sufficient tocause a wafer contact to not clear, or severely constrict the process window.TeraFlux was developed on the TeraStar platform to address the specialneeds of increased sensitivity for these features with high MEEF values.TeraFlux compares the transmitted energy to a reference with this equation:

∆flux = Σx,y (It - Ir)/[(It+Ir)/2]where:

It = Intensity at pixel x,y on test dieIr = Intensity at pixel x,y on reference die and the inspection mode is die-to-die.

This algorithm detects errors in total energy flux on critical layers

• Contacts• Vias• Small DRAM figures

These energy flux differences may be due to:

• Classical corner, intrusion, extrusion defects• CD errors• Semi-transparent defects• FIB repairs• CD SEM staining

C O V E R S T O R Y

28

• Small reticle defects that affectprinted line widths (attenuator,substrate, contamination)

• OPC and PSM methods and errors

• Scanner dose uniformity across thescanned field

• Scanner focus uniformity acrossthe field

• Field-to-field repeatability of focusand dose

• Wafer-to-wafer repeatability offocus and dose

Having access to this comprehensiveset of process window data alsoallows the lithographer to useadvanced lithography simulationand analysis software to accuratelytune the simulation to achieve thebest process.4 This approach is alsovalid for process development, defectprintability, test reticle design, anddesign verification.

The Total Common Process WindowAlthough this approach is useful inproviding an accurate representationof a single process cell for a givenpoint in time, there are a number of

additional process window varia-tions to consider, especially inadvanced production fabs. Whiletoday’s scanners have impressiveclosed-loop controls and compensa-tions, process window variations can

Summer 2002 Yield Management Solutions

still occur over time as a result of thevariables listed above and, whencoupled with small fluctuations inthe resist track performance, canhave a significant impact on theprocess window. The total commonprocess window is the overlap of thesevariations over time, and, in allcases, represents a reduction in thenet process window. The lithographycell’s manufacturable process win-dow must take these variations intoaccount, or risk reduced yield orspeed bin value. To maximize thetotal common process window,many fabs are beginning to activelymonitor and manage the processwindow over time. By tightly man-aging the fluctuations, this processwindow can be increased, resultingin improved productivity and yieldin the lithography cell.

Process Window MonitoringSeveral fabs are using both optical andSEM-based CD metrology systemswith integrated process windowmanagement5 (PWM) capability to

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Dense

IsolatedOverlap

Figure 6. Example of Common Process Window – The overlap of isolated lines and dense lines

or spaces depicts the total common process window, which was measured with KLA-Tencor’s 8XXX

CD SEM and automatically calculated with integrated ProDATA, process window analysis soft-

ware. Here, the x-axis represents focus, and the y-axis represents dose. The contour lines (shown

as thin lavender and thin red lines) depict the regions where the described features meet the CD

requirements. The heavy blue line encompasses the area of overlap where both feature types are

within specification, and the inscribed red rectangle is the combined process window.

1982 1986 1990 1994 1998 2002

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Figure 5. Process window reduction over time with technology node.

29Summer 2002 Yield Management Solutions

track and manage the stability of theprocess window over time. By run-ning a periodic PWM procedure, thelithographer can quickly identifydeviations in the process window,and obtain the quantitative informa-tion needed to make an informeddecision to either: (a) correct it if theproblem is simply a shift of bestfocus; or, (b) shut down the lithogra-phy cell if the depth of focus haschanged unacceptably. Figure 7 is anexample of the focus stability for alitho cell, showing the best focusand depth of focus over time. Thefrequency of the PWM procedurecould be daily or once per shift, andis dependent on the process tolerancelevel (see sidebar for PWM procedure).

A high-volume production fab willhave several critical scanners on thefab floor. To achieve maximum pro-ductivity, a fab should implement astrategy that enables any given waferlot to be routed to multiple scanners,depending upon tool availability.However, if scanners have not beenmatched for a given process window,the yield or performance may varydepending upon which scanner thelot is diverted to. To address theproblem, the lithographer must lookat the combined process window of allof the lithography cells in a scannerfamily and maximize their commonwindow. This is the total fab processwindow. By managing the stability ofeach scanner, and carefully matchingthe process windows of a scannerfamily, the lithographer will providethe best environment for yield andproductivity, and provide the widesttolerance for the reticle issues thatare covered in this paper.

If scanners are not matched accurately,then it is necessary to either dedicatea reticle to one litho cell, or charac-terize it on only one cell. While thisis adequate for development or for a single run, it is very costly in a manufacturing environment.

Figure 7. Daily process window stability for DUV scanner performed with KLA-Tencor 8450-PWM

system. The blue line shows fluctuations in best focus, whereas the red line shows fluctuations in

the size of the process window around best focus (from reference 5).

PWM procedure1. Process focus-exposure matrix wafer on the critical layer lithography

cell. This application typically utilizes daily test wafers, to isolate resultfrom product-wafer topography and films variations.

2. Measure wafer on 8x50-PWM or SpectraCD-PWM, using automatedFEM metrology.

3. Following completion of automated measurement job, FEM data isautomatically processed according to predefined specification limits and analysis conditions/parameters to produce a focus-exposure processwindow for that lithography cell, on that day.

4. Process-window data and reports for all PWM-monitored lithographycells are from anywhere on a company intranet, both inside the fab andat office-area desktops.

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30

Figure 8 shows dose matching ofthree DUV litho cells, representedby a web chart. The green line rep-resents the reference. The blue lineshows the location of each of thethree scanners relative to the refer-ence and the zero-window position(identified by the outer red line).Process window monitoring withthe 8x50-PWM shows that all threescanners can be brought within thereference with the indicated doseadjustment to maximize the totalfab process window.

This procedure for lithography cellmatching and management may alsobe extended between “brick andmortar” fabs and virtual fabs. PWMprovides a usable quantitative toolfor ensuring that a device willencounter the same process windowno matter where it is produced.

Determining the reticleprocess window Once PWM has been implemented,the fab’s common process window

will have been identified and stabi-lized, providing the maximum win-dow for a given process. The nextarea of focus is to ensure that eachcritical reticle functions within thatprocess window.

Verifying the DesignSignificant effort has been investedin ensuring device design for manu-facturability. TCAD products havebeen developed, which allow verifi-cation of the compatibility of device

Summer 2002 Yield Management Solutions

patterns with design rules forenhanced lithography.6, 7, 8 Verifyingthe design, however, is very chal-lenging when advanced lithographyprocesses with low k1 values arebeing used to produce the actualdevice. Lithographers in advancedfabs have often observed that pat-terns may not print accurately overthe entire process window, resultingin yield loss or performance loss.Unfortunately, it is not always easyto identify the locations that maycause a reduction in the total fabprocess window due to design issues.These design issues may includesimple rule violations, errors in modelor rule-based RET application, frac-turing errors, grid errors, writingerrors, or mask process biases.9 Some,but not all of these, may be identifiedby direct reticle inspection in eitherthe mask fab, or in the fab character-ization process described above.

The MEEFAdvanced lithography processeswith low k1 values enhance theimpact of errors on reticles. Thedeviation in critical dimensionsbetween the intended reticle imageand the image printed on the waferdue to errors on the reticle is known asthe Mask Error Enhancement Factor.10

The enhanced errors contribute tothe loss in process window, or, as inthe case of the example in Figure 9,

C O V E R S T O R Y

Figure 8. Three-Scanner Process Window Matching (dose). PWM shows that dose adjustment

allows all three lithography cells to be brought within the reference dose window (from reference 5).

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Figure 9. Contact Energy Error – MEEF factor associated with low k1 lithography causes contact

design to be printed much smaller than intended, resulting in complete process window failure. A

365UV HR reticle inspection system is used to detect the source of the error and PROLITH simula-

tion software is used to verify the process window and pattern transfer.

31Summer 2002 Yield Management Solutions

total failure in the overlap of theprocess windows.

These errors may occur at any pointon the reticle, and identifying themis the challenge. Quite often, thesemarginal design errors will not bedetected during reticle inspectionbecause the reticle was built correct-ly and perfectly matches the writerdata. Design rule modifications forresolution enhancement that havenot been based on adequate processmodels are, in fact, the actual causefor these failures. These erroneousmodifications result in patterningfailure within the process window.For example, sub-resolution scatter-ing bars—which are often printed atlower doses—are a common sourceof process window reduction due toresolution enhancement techniques.Regardless of the source of theseerrors, it is the lithographer who isresponsible for yield in the lithogra-phy cell, and who must ensure thatthe reticle is compatible with theestablished process window.

Identifying Patterning FailuresAssuming that the error cannot bedetected by the most advanced reti-cle pattern inspection (either die-to-die or die-to-database), but is stillsignificant to the pattern transferand device process window, it isdesirable to identify the possiblepatterning failure. Once the failureis identified, it is then possible tounderstand the impact, and make adecision for disposition of the waferlot.

A method has recently been devel-oped which uses wafer inspection toidentify marginal design errors thatmight fail only at the corners of theprocess window. These defects,which reduce the usable size of theprocess window, are often transientand show up as soft (or intermittent)repeaters at probe. This is sufficientto flag the weakness and allow the

lithographer to work with the prod-uct engineer or designer to make adisposition.

This method enables the lithograph-er to identify problems that causefailure within the known goodprocess window, or just outside of it.It has been effective in identifyingproblems with scattering bars, serifs,model-based OPC, and PSM errors.In some cases, the window wasseverely restricted, making the reti-cle unviable for manufacturing. Inother instances, it was determinedthat the reticle had a slight impacton the process window. In the lattercase, it might be feasible to use thereticle for prototype or small pro-duction runs, or limit its use to onelithography cell. Another outcome isthat these areas also become primarylocations for production CD moni-toring, since these marginal errorsare likely to be the first to causeprocess window failure. The defectlocation, as reported by the waferinspector, may be used as the loca-tion for easily generating a CD SEMrecipe. Part II of this article will dis-cuss this methodology in greaterdetail.

Bringing it all togetherThis paper has provided an overviewof complementary strategies that thelithographer can use to support thefab’s transition to more advancedlithography processes. By employing acomprehensive reticle managementstrategy that assures incoming qual-ity and continuously monitors thereticle for degradation, the lithogra-pher can minimize the impact ofrepeating defects on yield and avoidcostly crises. When defects are iden-tified, the high-resolution images maybe used to simulate their printabilityand impact on the process window.

This paper has also demonstratedthat it is possible to ensure the man-ufacturability of a new reticlethrough the use of wafer inspection,when built on top of the foundationof a stable process window achievedthrough the implementation ofprocess window management. Incases where there may be an issuewith a reticle, these qualificationmethods provide a well-quantifiedbenchmark for decisions to be made,and can even direct the designer toweaknesses that will limit manufac-turability. By understanding the

Figure 10. Pattern Failure within Process Window – The KLA-Tencor 2351 high-resolution imaging

tool was used to determine that a pattern design error caused a process window failure.

C O V E R S T O R Y

32

amount of process window that islost to a limiting reticle, to the lith-ographer can more easily makequantified decisions about the reti-cle’s overall impact on the processwindow entitlement.

Lithography is becoming more chal-lenging with each generation ofdesign rule and shrink. While itcontinues to grow in complexity andcost, lithography is also contribut-ing to the increased value in theproducts produced within a fab. Thestrategies and best practicesdescribed in this paper provide con-clusive and quantitative tools thatenable the lithographer to maximizethe productivity of expensive scan-ners and litho cells. These tools pro-vide definitive and rapid informa-tion to make decisions about reticlesand their impact on yield and binsort results. By minimizing theimpacts and delays of more criticalrequirements of smaller design rules,the lithographer is empowered toaccelerate new technology shrinks,and reap the financial rewards thataccompany their timely introduc-tion to the marketplace.

AcknowlegementsThe authors gratefully acknowledgethe assistance and support ofInternational SEMATECH, Infineon,Atmel, and TSMC. The authorswould like to thank Moshe Preil forhis contributions and input.

References1. W. Volk et al, Multibeam high-reso-

lution die:database reticle inspec-tion, BACUS Symposium on Pho-tomask Technology, Monterey, CA,USA, October, 2001.

2. L. Pang, K. K. Chan, Q. D. Qian,Comparison of attenuated PSM maskdefect printability analysis using vir-tual stepper system and aerial imagemicroscope system, SPIE Microlitho-graphy, Santa Clara, CA, USA,March, 2002.

3. V. Samek, et al, Cost effective reticlequality management strategies inwafer fabs, IEEE/SEMI AdvancedSemiconductor Manufacturing Con-ference and Workshop (ASMC),Boston, MA, USA, September, 1999.

4. J. Byers, C. Mack, R. Huang, S. Jug,Automatic calibration of lithographysimulation parameters using multipledata sets, micro and nano-engineer-ing, Grenoble, France, September,2001.

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5. R. Routh, et al, Automated lithogra-phy process window monitoring with8250-PWM, KLA-Tencor LithographyUsers Forum, Santa Clara, CA, USA,February 2002.

6. P. LaCour, E. Y. Sahouria, Y. Granik,Chip leve l l inewidth predic t ionmethodology, SPIE Microlithography,Santa Clara, CA, USA, March,2002.

7. M. L. Rieger, J. P. Mayhew, Z. Tang,Verifying RET mask layouts, SPIE Mi-crolithography, Santa Clara, CA,USA, March, 2002.

8. K. Liu, J.Cheng, J. Z. Wu, A. Jain, M.Mehrotra, M. Rodder, Improving de-vice performance and process man-ufacturabi l i ty through the use ofTCAD, SPIE Microlithography, SantaClara, CA, USA, March, 2002.

9. A. Berbert, et al, Adjustment of opti-cal proximity correction (OPC) soft-ware for mask process correction(MPC), BACUS Symposium on Pho-tomask Technology, Monterey, CA,USA, October, 2001.

10. W. Maurer, et al, Process proximi-ty correction using an automated soft-ware tool, SPIE Microlithography,Santa Clara, CA, USA, March,1998.

11. Y. H. Kim, J. H. Park, K. H. Lee, H.K. Cho, H. S. Yoon, Detectabilityand printability of programmed de-fects in the contact layer for 256-Mb-DRAM grade reticle, BACUSSymposium on Photomask Technolo-gy, Monterey, CA, USA, October1996.

12. H. J. Kim, J. S. Hong, J. W. Kye,D.H. Cha, H. Y.Kang, J. T. Moon, De-fect inspection and printability ofdeep-UV halftone phase-shifting mask,BACUS Symposium on PhotomaskTechnology, Monterey, CA, USA,October 1996.

13. K. Takeuchi, Y. Miyahara, Defectdetectability and printability of con-tact hole pattern of KrF halftone reti-cle, Photomask and X-Ray Mask Tech-nology, Kanagawa, Japan 1999.

Software DRC andprocess window check

Logical verification

Physical verification

Reticle inspection

Wafer qualification

Electrical test

Netlist

Layout (wafer)

Reticle

Wafer

Chip

TeraStarfinds all defects

23xx confirms processwindow and repeaters

Final electricalconfirmation

Figure 11. Best known methods for preventing repeating pattern defects.

C O V E R S T O R Y

When a leading foundry needed to increase yields from their low k1 reticles,

they turned to TeraStar. That’s because TeraStar delivers the highest sensitivity

available in a reticle inspection tool. And by eliminating false and nuisance

defects, it gives the freedom to thoroughly inspect reticles – regardless of design

complexity. As a result, in a 6-month period, engineers were able to move from

zero yield on one of every four devices manufactured to finding every critical

reticle defect. And bring their 0.13µm ramp yield issue under control faster and

more efficiently than they ever thought possible. To see what you’ve been miss-

ing, please visit www.kla-tencor.com/tera, or call 1-800-450-5308. Accelerating Yield

For more about how

TeraStar helped

a major fab shorten

its time to yield, please visit

www.kla-tencor.com/tera.

Getting better yields from reticles doesn’t have to be a puzzle.

©2001 KLA-Tencor Corporation