Summer 2002 Yield Management Solutions 45

cell. From a defect management perspective, the lithography cell has some unique characteristics. First,defects in the photo process module routinely have thewidest range of sizes, from full-wafer to sub-optical,and with the largest variety of characteristics. Some ofthese defects fall into the categories of coating problems,focus and exposure defects, developer defects, edge-beadremoval problems, contamination and scratches usuallydefined as lithography macro defects as illustrated inFigure 1. Others, as illustrated in Figure 2, fall intothe category of lithography micro defects. They arecharacterized as having low topography such as stains,developer spots, satellites, and are very small such as thecases of microbridging, microbubbles, CD variation andsingle isolated missing or deformed contacts or vias.

Second, photo is the only area of the fab besides CMPin which defect excursions can typically be corrected byreworking the wafers. The opportunity to fix defect

Pattern Transfer/Shrinks

The Art of Defect War in the Litho CellIngrid Peterson, Meryl Stoller, Dadi Gudmundsson, Raman Nurani, Scott Ashkenaz, and Louis Breaux,

KLA-Tencor Corporation

The latest technology advances and new processes in the lithography area, coupled with the increasing market pressures,have placed greater demands on defect management. Thinner resists, new resist chemistries, and tighter process windowsalong with shorter product life cycles and the need for faster return on investment create the necessity to focus more attentionon defectivity. In order to be competitive, fabs must detect, identify, and resolve defects in the lithography area before committing product wafers to production.

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IntroductionAt present, the application of availableadvanced defect management technology inthe lithography area has lagged comparedto other areas in the semiconductor fab.Optimizing the defect management strategywith the large range of possible defectmechanisms and related yield impact thatcan occur within the lithography area is arelatively complicated task. With the varietyof available defect inspection technologies,the capital and labor support costs associatedwith defect metrology and the ability tocorrect problems by rework, there is a needto approach the problem of defect manage-ment in a systematic manner to measurethe cost effectiveness of the defect manage-ment strategy. In this paper the SamplePlanner™ cost model was applied to thefull range of available defect inspectiontechnologies and sampling strategies basedon the commonly known defect mechanismsthat occur in the lithography area. Fromthis a recommended optimum samplingand monitoring strategy was obtained.

Defect management in the lithography cellToday, the semiconductor process itself con-tributes the largest number and variety ofdefects, and a significant portion of the totaldefects originate within the lithography Figure 1. Examples of lithography macro defects.

Summer 2002 Yield Management Solutions46

Model inputs and assumptionsSample Planner Model OverviewThe Sample Planner 3 Cost Model is basedon several cost components which can beseparated into two main cost factors: thecosts of inspection operations and thecost-based risk of yield loss due to misseddefect occurrences. The first set of costsare those investments that are made inorder to perform defect inspection andthe time involved in isolating and fixingdefect issues. These are costs incurred bythe fab, and increase as higher rates ofsampling and defect inspection are imple-mented. The latter costs are the revenuegained by taking action and resolvingdefect issues so that subsequent lots yieldhigher or, alternately, the revenue lost bynot capturing a defect problem sooner.These “costs” will likely be large at first

compared to no sampling, so that performing a mini-mum level of sampling will result in revenue gained.As inspection sampling is increased at some point, theincremental revenue to be gained will diminish. Forthe sample planning model, the potential revenue lossis expressed by the number of lots at risk of a certainlevel of yield loss while a defect excursion event is inprogress, until that event is captured and eliminated.This is illustrated in Figure 3.

The inspection operations costs consist of several com-ponents including the capital costs of the inspectiontools needed, the cost of labor to operate the tools interms of shift personnel, labor costs for engineering toact on defect issues (real or false), other direct and indirect labor costs, facilities costs and, where applica-ble, the costs of test wafers and test wafer processing.

The revenue loss due to defect excursion events is afunction of the frequency of excursions, the duration of an excursion, the yield impact of the excursion and

the die price for the particular fab. In thismodel, the baseline yield level is assumedto be at entitlement, so that any defectexcursion event results in yield loss and,thus, revenue loss. What this means isthat in the model the full impact ofexcursion will be realized on a lot, and notmasked by other yield loss mechanisms.

problems without scrapping wafers is best served by adefect inspection strategy that captures the full rangeof all relevant defect types.

Third, to some extent, the litho cell remains a defectfrontier. In most areas of the fab, leading-edge defectmanagement tools and methodology have already beenadopted, but in the lithography area defectivity is oftenunder-managed. For example, recent studies have shownthat replacing manual inspection for macro defects byautomated inspection can result in an increase of 1 to2% in real yield1.

This complex problem requires a sophisticated modelof the costs and risks involved in order to evaluate theeffectiveness of a variety of scenarios and strategies fordefect management in the lithography area. The SamplePlanner 3 model developed by KLA-Tencor in partner-ship with UC-Berkeley, Carnegie-Mellon University,and Stanford University has the capability of analyzingthe cost effectiveness of defect management strategiesfor the lithography area.

S P E C I A L F O C U S

Figure 3. Sample Planner model definition of “material-at-risk” during a defect excursion event.

Avg. 136 nmAvg. 94 nm

Figure 2. Examples of lithography micro defects.

Summer 2002 Yield Management Solutions 47

Inputs for Lithography Area ModelingFab-level. To perform the model for the lithographyarea, an appropriate fab model had to be chosen. Forthis study, an “average” 300 mm fab model was chosento represent the costs. To model such a fab, the lot sizewas set at 12 wafers and the wafer starts at 5,000wafers per week. The potential revenue for this fab wasbased on a fictitious device which had 600 dice perwafer and an ASP of $25.00 per die. This, on average,underestimates the potential revenue savings by yieldimprovement, although DRAM devices will likelyhave a lower potential revenue per die.

This fab is assumed to operate 24 hours per day, 7 daysper week with 3 shifts per day. These last inputs arenecessary for the model, but typically do not impactthe model results in any appreciable fashion comparedto a fab that operates on 2 – 12 hour shifts per day. Inthis model, the cycle times used were based upon actu-al 200 mm cycle times that, on average, are commonin the industry. These times would include the processtimes for the various lithography steps including thewait and queue times. In modeling tool monitors, suchas a photocell monitor (PCM), it was assumed that thetracks would continue to process wafers while the mon-itors were being evaluated; thus, there were no “oppor-tunity costs” associated with lost time on the toolsother than the time to process the tool monitors.

Lithography defectivity. To model the lithographyarea defectivity a set of 31 typical defects that com-

S P E C I A L F O C U S

monly occur in lithography areas worldwide was estab-lished. This list was developed by pooling the experi-ence and data from knowledgeable resources withinKLA-Tencor that have worked on lithography defectiv-ity through consulting projects and other past workexperience for many years up to the present. Some ofthese defect types are represented in Figures 1 and 2. Acomplete listing of the defects used for the model arepresented in Tables 1 and 2 along with some of thepertinent parameters used to model the frequency ofoccurrence of excursions for such defects (for simplicityall are set at 5% probability of occurrence) and theirimpact on the yield, and the exposure of lots and waferwithin lots to these defect types during an excursionevent.

The exposure of wafers to an excursion is based on anassumption of an excursion event occurring for onlyone resist or developer cup on a track. Multiple resistcups and developer cups are assumed per track (mini-mum of two), so that for defect mechanisms that arelimited to single cup events, the wafer exposure is apercentage of the total wafers in a lot.

Inspection technologies and strategies. The modelwas used to compare the best combination of defectinspection strategies and tool types for the lithographyarea. A block diagram that shows the various possibledefect inspection points and likely tools used is shown inFigure 4. The inspection possibilities included the useof automated low sensitivity (≥ 50 µm) “macro” inspec-tion on product wafers (such as use of KLA-Tencor’s2430), brightfield high sensitivity “micro” inspection(such as use of a KLA-Tencor 2351), and darkfieldinspection (such as use of a KLA-Tencor AIT XP). Not

Table 1. Macro-level defects used in Sample Planner model with the

associated excursion frequencies and impacts.

Table 2. Micro-level defects used in Sample Planner model with the

associated excursion frequencies and impacts.

Summer 2002 Yield Management Solutions48

considered by this model is the use of unpatternedwafer inspection such as would be performed on resist-coat only wafers or other unpatterned monitors. Theprimary goal of this study is the evaluation of inspec-tion technologies on patterned wafers. Included in thepatterned wafer grouping is the use of PCM,2-4 whichare tool monitors that see the entirety of the litho-graphic process, but on an initially unpatterned substrate. Therefore, the combination of inspectionstrategies modeled were macro after-develop inspection

(macro DI), brightfield and darkfieldmicro DI, and brightfield PCM.

Inspection points modeled were after fullpatterning and typically performed afterthe CD and overlay measurement steps.Also included in the model was a bright-field micro inspection step after the etchstep, which captured issues that werepotentially missed by the post developinspections. In the etch inspection case, thedefectivity caused a yield loss; whereas thedefectivity caught after the post-developstep was resolved by rework of the lot orlots affected. Prior cross-platform studieson product and photo-cell monitor wafers,as well as hands-on experience, were referenced to estimate the ability of aparticular inspection technology to

capture the various defect types in Tables 1 and 2. Ingeneral, the capture rate for this study was either“YES” or “NO,” i.e. captured or not captured. Table 3shows the capturability used for this model by inspec-tion monitoring for the 31 defects considered.

Results from model scenariosSeveral scenarios for performing lithography area moni-toring were considered. The scenarios were based onthe various combinations of inspection technologiesand methods described above, as well as the frequencyat which these monitors were performed and the sam-pling of lots and wafers as applicable. A listing of thesampling scenarios considered is provided in Table 4below. For all of the potential scenarios the possibilityof not performing each monitor was considered.

The outputs of the model for each scenario would bethe operational costs of performing the monitoringwhich is the sum of capital equipment costs, test wafermaterials and processing costs (if applicable), and

S P E C I A L F O C U S

Figure 4. Block diagram of possible lithography defect inspections modeled.

Table 3. Capturability of defect types modeled by inspection tech-

nology and technique.

Table 4. Inspection scenarios considered for modeling. For the PCM

monitoring and wafers at risk, a 2-cup track scenario is used.

Summer 2002 Yield Management Solutions 49

direct and indirect labor costs and the “excursion costs”which is the potential revenue lost due to yield lossfrom excursion events not captured or the number ofdie negatively impacted by excursion events that werenot recoverable (by rework, for instance). The costswere annualized in some cases producing an annualcosts summary. The goal is to minimize both the oper-ational costs and excursion costs and achieve the lowestexcursion costs with the least added operational costs.

Figure 5 shows the combination of costs for selectedscenarios. Not shown is the cost for performing nomonitoring. For reference purposes, that annual cost is entirely excursion-related and amounts to about$64,500,000 for this particular fab. As can be seenfrom Figure 5, just performing macro DI inspectionresults in minimal added operational costs, while reducing excursion costs (costs of yield loss) to under$35,500,000. Without macro DI monitoring, all othermonitoring scenarios considered had an additional$10,000,000 or more in annual total costs. This ismostly due to the greater risk of excursion yield losssince the operational costs of macro DI are minimal.

Also from Figure 5, it is seen that the least total annualcost occurs for the scenario with a combination ofmacro DI (100% of lots), PCM at three times a dayand a brightfield inspection after develop (DI) at a lowsampling of 6.25% of lots. Eliminating the brightfieldDI inspection, as low as it is, reduces the inspectioncosts; but, that is more than offset by the increased riskfrom missing some excursion events. Darkfield inspec-tion after develop (DI) at a high sampling rate can

reduce excursion costs, but not significantly more thana lower sampling rate for brightfield DI, and theinspection costs will be higher. From the model resultsit is seen that PCM, nonetheless at a relatively highmonitoring rate, is worth the investment (test wafercosts, etc.) even for 300 mm, as long as it is capable ofcapturing the defect events.

ConclusionsIn a lithography area, the defectivity and yield lossmechanisms are diverse and complicated. In order tounderstand the optimum methods for defect monitoringit is necessary to consider the overall strategy as a sys-tem. The ability to perform rework in the lithographyarea adds an additional benefit in that potential yieldproblems can be corrected. As a result of the typicalcycle times through a lithography area, it is more bene-ficial to use a high sensitivity brightfield inspection forboth DI inspections and PCM inspections in spite ofthe slower overall inspection throughput. While adarkfield approach may appear cheaper, that advantageis more than lost by the defect types which are missed.As long as an excursion event is captured in a reason-able time before etch, a large enough number of lotscan be saved to justify the inspection costs. However,using a lower sensitivity darkfield inspection can resultin missed excursions and higher yield loss, even with avery high sampling rate. The model indicates that it isbetter to use macro DI inspection in combination withfrequent brightfield PCM and brightfield DI at a lowsampling rate for optimum lithography area monitoring.

References1. A. Yanof, et. al., “Implementation of Automated Macro

After Develop Inspection in a Production LithographyProcess,” SPIE 25th Annual International Symposium on Mi-crolithography, February 2000.

2. E.H. Bokelberg and M.E. Pariseau, “Tracking the per-formance of photolithographic processes with excursionmonitoring,” MICRO, January 1998.

3. S. Ashkenaz, et. al., “Effective Defect Management in theLithography Cell,” Yield Management Solutions, Vol. 3,Issue 4, Fall 2001.

4. I. Peterson, et. al., “Lithography Defects: Reducing andManaging Yield Killers Through Photo Cell Monitoring,”Yield Management Solutions, Vol. 2, Issue 3, Summer2000, pg 17-24.

S P E C I A L F O C U S

Figure 5. Comparison of inspection operation and excursion costs for

selected scenarios for lithography area defect monitoring. For compar-

ison, the cost of no monitoring is $64,500,000 per year.

With the transition to 0.10 µm, optimizing your lithography process window is tougher than ever. And there’s no secondchance to make a good first shot. Fortunately, by providing reticle, CD, defect and overlay control – as well assimulation – our sub-wavelength lithography solution is the most comprehensive one available. So you get unprecedented control over the entire process, from reticle to wafer. Commonality between tools. The ability to pinpoint targets in shrinking process windows. And a nice big score on ROI. For moreinformation, visit www.kla-tencor.com/litho, or call 1-800-450-5308.

Shrinking process windows are a challenge. Hitting them doesn’t have to be.

Accelerating YieldFor a free bound set of lithography articles by Chris Mack, please visit www.kla-tencor.com/litho.

©2001 KLA-Tencor Corporation