HDL LAB IVth Sem EC

H.D.L LABFor IV Semester B.E

Electronics and Communication Engineering

(As per VTU Syllabus)

SL.NONAME OF THE EXPERIMENTPAGE NO

1LOGIC GATES6

2ADDERS AND SUBTRACTORS10

3COMBINATIONAL DESIGNS

a.2 TO 4 DECODER

b.8 TO 3 ENCODER

c.8 TO 1 MULTIPLEXER

d.4 BIT BINARY TO GRAY CONVERTER

e. MULTIPLEXER, DE-MULTIPLEXER, COMPARATOR

14

4FULL ADDER(3 MODELING STYLES)32

532 BIT ALU USING THE SCHEMATIC DIAGRAM37

6FLIP-FLOPS (SR, D, JK AND T)40

74 BIT BINARY,BCD COUNTERS

SYNCHRONOUS & ASYNCHRONOUS COUNTERS45

8

9ADDITIONAL EXPERIMENTSRING COUNTER

JHONSON COUNTER

INTERFACING

1DC AND STEPPER MOTOR48

2EXTERNAL LIGHT CONTROL51

3WAVEFORM GENERATION USING DAC52

4SEVEN SEGMENT DISPLAY56

EXPERIMENTS LIST (ACCORDING TO VTU SYLLABUS)

PROGRAMMING (using VHDL and Verilog)

1.Write HDL code to realize all the gates.

2.Write a HDL program for the following combinational designs

a. 2 to 4 decoder

b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer

d. 4 bit binary to gray converter

e. Multiplexer, de-multiplexer, comparator.

3. Write a HDL code to describe the functions of a full adder using three modeling styles.

4. Write a model for 32 bit ALU using the schematic diagram shown below

A(31:0)

ALU should use the combinational logic to calculate an output based on the four bit op-code input.

ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low.

ALU should decode the 4 bit op-code according to the given in example below.

OPCODEALU OPERATION

1.A+B

2.A-B

3.A Complement

4.A*B

5.A AND B

6.A OR B

7.A NAND B

8.A XNOR B

5. Develop the HDL code for the following flip-flop, SR, D, JK, T.

6. Design 4 bit binary , BCD counters (Synchronous reset and asynchronous reset) and any sequence counters

INTERFACING (at least four of the following must be covered using VHDL/Verilog)1. Write HDL code display messenger on the given seven segment display and LCD and accepting Hex key pad input data.

2. Write HDL code to control speed, direction of DC and stepper motor.

3. Write HDL code to accept 8 channel analog signal, Temperature sensors and display the data on LC panel or seven segment display

4. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,)using DAC change the frequency and amplitude.

5. Write H DL code to simulate Elevator operation

6. Write HDL code to control external light using relays.

*******************

HDL MANUALIt is one of most popular software tool used to synthesize VHDL code. This tool

Includes many steps. To make user feel comfortable with the tool the steps are

given below:-

Double click on Project navigator. (Assumed icon is present on desktop).

Select NEW PROJECT in FILE MENU.Enter following details as per your convenience

Project name : sample

Project location : C:\example

Top level module : HDL

In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is given below:

Device family : Spartan2

Device : xc2s200

Package : PQ208

TOP Level Module : HDL

Synthesis Tool : XST

Simulation : Modelsim / others

Generate sim lang : VHDL

In source window right click on specification, select new source

Enter the following details

Entity: sample

Architecture : Behavioral

Enter the input and output port and modes.

This will create sample.VHDL source file. Click Next and finish the initial Project preparation.

Double click on synthesis. If error occurs edit and correct VHDL code.

Double click on Lunch modelsim (or any equivalent simulator if you are using) for functional simulation of your design.

Right click on sample.VHDL in source window, select new source

Select source : Implementation constraints file.

File name : sample

This will create sample. UCF constraints file.

Double click on Edit constraint (Text) in process window.

Edit and enter pin constraints with syntax:

NET NETNAME LOC = PIN NAME

Double click on Implement, which will carry out translate, mapping, place and route of your design. Also generate program file by double clicking on it, intern which will create .bit file.

Connect JTAG cable between your kit and parallel pot of your computer.

Double click on configure device and select mode in which you want to configure your device. For ex: select slave serial mode in configuration window and finish your configuration.

Right click on device and select program. Verify your design giving appropriate inputs and check for the output.

Also verify the actual working of the circuit using pattern generator & logic analyzer.

EXPERIMENT NO. 1

WRITE HDL CODE TO REALIZE ALL LOGIC GATES

AIM: Simulation and realization of all logic gates.

COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.

Truth table with symbols

Black Box

c a d e f b g h i Truth table Basic gates: abcdefghi

000011101

010111010

100101010

111100001

VHDL CODE VERILOG CODE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOG IC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is

Port ( a,b : in std_logic;

c,d,e,f,g,h,i : out std_logic);

end gates;

architecture dataflw of gates is

begin

c