march 23, 2001vlsi test: bushnell-agrawal/lecture 211 lecture 21 i ddq current testing n definition...
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March 23, 2001 VLSI Test: Bushnell-Agrawal/Lecture 21
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Lecture 21IDDQ Current Testing
Lecture 21IDDQ Current Testing
Definition Faults detected by IDDQ tests
Vector generation for IDDQ tests Full-scan Quietest
Instrumentation difficulties Sematech study Limitations of IDDQ testing Summary
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MotivationMotivation
Early 1990’s – Fabrication Line had 50 to 1000 defects per million (dpm) chips IBM wants to get 3.4 defects per million
(dpm) chips (0 defects, 6 ) Conventional way to reduce defects:
Increasing test fault coverage Increasing burn-in coverage Increase Electro-Static Damage awareness
New way to reduce defects: IDDQ Testing – also useful for Failure Effect
Analysis
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Basic Principle of IDDQ Testing
Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus
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Faults Detected by IDDQ Tests
Faults Detected by IDDQ Tests
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Stuck-at Faults Detected by IDDQ Tests
Stuck-at Faults Detected by IDDQ Tests
Bridging faults with stuck-at fault behavior Levi – Bridging of a logic node to VDD or
VSS – few of these
Transistor gate oxide short of 1 K to 5 K
Floating MOSFET gate defects – do not fully turn off transistor
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NAND Open Circuit Defect – Floating gate
NAND Open Circuit Defect – Floating gate
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Floating Gate DefectsFloating Gate Defects
Small break in logic gate inputs (100 – 200 Angstroms) lets wires couple by electron tunneling Delay fault and IDDQ fault
Large open results in stuck-at fault – not detectable by IDDQ test
If Vtn < Vfn < VDD - | Vtp | then
detectable by IDDQ test
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Multiple IDDQ Fault ExampleMultiple IDDQ Fault Example
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Capacitive Coupling of Floating Gates
Capacitive Coupling of Floating Gates
Cpb – capacitance from
poly to bulk Cmp – overlapped metal
wire to poly Floating gate voltage
depends on capacitances and node voltages
If nFET and pFET get enough gate voltage to turn them on, then IDDQ
test detects this defect K is the transistor gain
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IDDQ Current Transfer Characteristic
IDDQ Current Transfer Characteristic
Segura et al. – 5 defective inverter chains (1-5) with floating gate defects
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Bridging Faults S1 – S5Bridging Faults S1 – S5
Caused by absolute short (< 50 ) or higher R
Segura et al. evaluated testing of bridges with 3 CMOS inverter chains
IDDQRb tests fault when Rb
> 50 K or 0 Rb 100 K
Largest deviation when Vin = 5 V bridged nodes at
opposite logic values
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S1 IDDQ Depends on K, RbS1 IDDQ Depends on K, Rb
K |IDDQ|
(A)
Rb (k)
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CMOS Transistor Stuck-Open Faults
CMOS Transistor Stuck-Open Faults
IDDQ test can sometimes detect fault
Works in practice due to body effect
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Delay FaultsDelay Faults
Most random CMOS defects cause a timing delay fault, not catastrophic failure
Many delay faults detected by IDDQ test –
late switching of logic gates keeps IDDQ
elevated Delay faults not detected by IDDQ test
Resistive via fault in interconnect Increased transistor threshold voltage
fault
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Leakage FaultsLeakage Faults
Gate oxide shorts cause leaks between gate &
source or gate & drain
Mao and Gulati leakage fault model:
Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG
G = gate, S = source, D =
drain, B = bulk
Assume that short does not change logic
values
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Weak FaultsWeak Faults
nFET passes logic 1 as 5 V – Vtn
pFET passes logic 0 as 0 V + |Vtp|
Weak fault – one device in C-switch does not
turn on
Causes logic value degradation in C-switch
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Paths in CircuitPaths in Circuit
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Transistor Stuck-Closed Faults
Transistor Stuck-Closed Faults
Due to gate oxide short (GOS)
k = distance of short from drain
Rs = short resistance
IDDQ2 current results
show 3 or 4 orders of magnitude elevation
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Gate Oxide ShortGate Oxide Short
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Logic / IDDQ Testing ZonesLogic / IDDQ Testing Zones
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Fault Coverage MetricsFault Coverage Metrics Conductance fault model (Malaiya & Su)
Monitor IDDQ to detect all leakage faults Proved that stuck fault test set can be used
to generate minimum leakage fault test set Short fault coverage
Handles intra-gate bridges, but may not handle inter-gate bridges
Pseudo-stuck-at fault coverage Voltage stuck-at fault coverage that
represents internal transistor short fault coverage and hard stuck-at fault coverage
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Fault Coverages for IDDQ Fault Models
Fault Coverages for IDDQ Fault Models
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Vector Selection with Full Scan -- Perry
Vector Selection with Full Scan -- Perry
Use voltage testing & full scan for IDDQ tests
Measure IDDQ current when voltage vector
set hits internal scan boundary Set all nodes, inputs & outputs in known
state Stop clock & apply minimum IDDQ current
vector Wait 30 ms for settling, measure IDDQ
against 75 A Limit, with 1 A accuracy
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Quietest Leakage Fault Detection – Mao and
Gulati
Quietest Leakage Fault Detection – Mao and
Gulati
Sensitize leakage fault
Detection – 2 transistor terminals with
leakage must have opposite logic values,
& be at driving strengths
Non-driving, high-impedance states won’t
work – current cannot go through them
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Weak Fault Detection – P1 (N1) Open
Weak Fault Detection – P1 (N1) Open
Elevates IDDQ from 0 A to 56 A
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Second Weak Fault Detection ExampleSecond Weak Fault Detection Example
Not detected unless I3 = 1
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Hierarchical Vector Selection
Hierarchical Vector Selection
Generate complete stuck-fault tests Characterize each logic component – relate
input/output logic values & internal states: To leakage fault detection To weak fault sensitization/propagation Uses switch-level simulation
Store information in leakage & weak fault tables
Logic simulate stuck-fault tests – use tables to find faults detected by each vector No more switch-level simulation
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Leakage Fault TableLeakage Fault Table
k = # component I/O pins n = # component transistors m = 2k (# of input / output combinations) m x n matrix M represents the table Each logic state – 1 matrix row Entry mi j = octal leakage fault information
Flags fBG fBD fBS fSD fGD fGS
Sub-entry mi j = 1 if leakage fault detected
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Example Leakage Fault Table
Example Leakage Fault Table
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Weak Fault TableWeak Fault Table
Weak faults: Sensitized by input/output states of
faulty component Propagated by either faulty
component input/output states or input/output states of components driven by node with weak fault
Use weak fault detection, sensitization, and propagation tables
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Quietest ResultsQuietest Results
If vector tests 1 new leakage/weak fault, select it for IDDQ measurement
Example circuit:
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Results – Logic & IDDQ Tests
Results – Logic & IDDQ Tests
IDDQ measurement vectors in bold & italics
Time in units
Time99199299399499599699
I10011011
I21001110
X11110100
O10000000
Time799899999
1099112912991399
I10011011
I20110001
X10100000
O11000100
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Quietest ResultsQuietest Results
Ckt.
12
# ofTran-
Sistors758442373
# ofLeakageFaults39295
220571
%SelectedVectors0.5 %
0.99 %
LeakageFault
Coverage94.84 %90.50 %
# ofWeakFaults19231497
%SelectedVectors0.35 %0.21 %
WeakFault
Coverage85.3 %
87.64 %
Ckt.
12
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Instrumentation Problems
Instrumentation Problems
Need to measure < 1 A current at clock > 10 kHz
Off-chip IDDQ measurements degraded Pulse width of CMOS IC transient
current Impedance loading of tester probe Current leakages in tester High noise of tester load board
Much slower rate of current measurement than voltage measurement
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Sematech StudySematech Study IBM Graphics controller chip – CMOS ASIC,
166,000 standard cells 0.8 m static CMOS, 0.45 m Transistors (Leff),
40 to 50 MHz Clock, 3 metal layers, 2 clocks Full boundary scan on chip Tests:
Scan flush – 25 ns latch-to-latch delay test 99.7 % scan-based stuck-at faults (slow 400
ns rate) 52 % SAF coverage functional tests
(manually created) 90 % transition delay fault coverage tests 96 % pseudo-stuck-at fault cov. IDDQ Tests
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Sematech ResultsSematech Results Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure
Analysis Data for devices failing some, but not all, tests.
passpassfailfail
pass
14652
pass
pass60136fail
fail14633413
1251pass
fail718
fail
passfail
passfail
Scan
-based
Stu
ck-a
t
IDDQ (5 A limit)
Functional
Scan
-based
dela
y
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Sematech ConclusionsSematech Conclusions
Hard to find point differentiating good and bad devices for IDDQ & delay tests
High # passed functional test, failed all others High # passed all tests, failed IDDQ > 5 A Large # passed stuck-at and functional tests
Failed delay & IDDQ tests Large # failed stuck-at & delay tests
Passed IDDQ & functional tests Delay test caught delays in chips at higher
Temperature burn-in – chips passed at lower T.
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Limitations of IDDQ TestingLimitations of IDDQ Testing
Sub-micron technologies have increased leakage currents Transistor sub-threshold conduction Harder to find IDDQ threshold separating
good & bad chips IDDQ tests work:
When average defect-induced current greater than average good IC current
Small variation in IDDQ over test
sequence & between chips Now less likely to obtain two conditions
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SummarySummary IDDQ tests improve reliability, find defects
causing: Delay, bridging, weak faults Chips damaged by electro-static discharge
No natural breakpoint for current threshold Get continuous distribution – bimodal
would be better Conclusion: now need stuck-fault, IDDQ, and
delay fault testing combined Still uncertain whether IDDQ tests will remain
useful as chip feature sizes shrink further