May 9, 2001 2

USB 2.0 High Bandwidth Peripheral Design

Challenges

USB 2.0 High Bandwidth Peripheral Design

ChallengesRobert Shaw

Cypress Semiconductorxro@cypress.com

Robert ShawCypress Semiconductor

xro@cypress.com

May 9, 2001 3

USB 2.0 in a NutshellUSB 2.0 in a Nutshell

Runs 40X faster than USB 1.1– Low speed: 1.5Mb/s– Full speed: 12Mb/s– High speed: 480Mb/s

Fully supports existing USB devices– Forward compatible—plug existing 1.1 devices into new

2.0 hosts– Backward compatible—plug new 2.0 devices into existing

1.1 hosts Uses the same cables as USB 1.1

Runs 40X faster than USB 1.1– Low speed: 1.5Mb/s– Full speed: 12Mb/s– High speed: 480Mb/s

Fully supports existing USB devices– Forward compatible—plug existing 1.1 devices into new

2.0 hosts– Backward compatible—plug new 2.0 devices into existing

1.1 hosts Uses the same cables as USB 1.1

May 9, 2001 4

SOF

327

SOF

328

USB 2.0 BandwidthUSB 2.0 Bandwidth

SOF

327

SOF

327

SOF

327

SOF

327

SOF

327

SOF

327

SOF

327

125 usec

125 usec

125 usec

125 usec

125 usec

125 usec

125 usec

125 usec

1 msec1 msec

SOF

327

SOF

327

10241024

SOF

327

SOF

327

512

646410241024 10241024 512 512 ISO

INTISOINT

BU

LK512 512 512 512 512

CT

LC

TL

6464. . . . .

May 9, 2001 5

Packet SizesPacket Sizes

Control

Bulk

Interrupt

Isochronous

Control

Bulk

Interrupt

Isochronous

8, 16, 32, 64

8, 16, 32, 64

1–64

1023

8, 16, 32, 64

8, 16, 32, 64

1–64

1023

64

512

1024

1024

64

512

1024

1024

USB 1.1USB 1.1 USB 2.0USB 2.0

Transfer TypeTransfer Type Packet SizePacket SizePacket SizePacket Size

May 9, 2001 6

USB 2.0–13 Bulk packets per microframe max–13 * 512 * 8 * 1000 = 53 MB/s

USB 2.0–13 Bulk packets per microframe max–13 * 512 * 8 * 1000 = 53 MB/s

Bandwidth ExampleBandwidth Example

ATA Hard Drive 7200 RPM, 2Mbyte Internal Buffer– Transfer rate, Interface: up to 100MB/s– Transfer rate, Media: up to 57 MB/s– Typical system transfer rates 39 MB/s

ATA Hard Drive 7200 RPM, 2Mbyte Internal Buffer– Transfer rate, Interface: up to 100MB/s– Transfer rate, Media: up to 57 MB/s– Typical system transfer rates 39 MB/s

May 9, 2001 7

USBHost

BufferBuffer

HeadHead

57

Disk Drive

USB 2.0Controller

USBUSB 10010010–5310–53 IFIF

39 Sustained *

39 Sustained *

Bandwidth AnalysisBandwidth Analysis

*1.5GHz P4 Host,7200 ATA 100 Drive

USB Hard DriveUSB Hard Drive

May 9, 2001 8

Bandwidth ConclusionsBandwidth Conclusions

Both sides, USB and Interface, must supporthigh bandwidth

USB– Large endpoint buffers– At least double buffering

Interface– Internal processor should not touch 480 Mbit/sec data.

Use the CPU for USB housekeeping & I/O Optimize the data channel using specialized logic

– Fast data transfers require fast control logic Interface logic should be programmable ATA, EPP, etc.

Both sides, USB and Interface, must supporthigh bandwidth

USB– Large endpoint buffers– At least double buffering

Interface– Internal processor should not touch 480 Mbit/sec data.

Use the CPU for USB housekeeping & I/O Optimize the data channel using specialized logic

– Fast data transfers require fast control logic Interface logic should be programmable ATA, EPP, etc.

May 9, 2001 9

16Low level protocolCRC, PID encode-

decode, chirp Deliver WORDS

Low level protocolCRC, PID encode-

decode, chirp Deliver WORDS

TokenProcessorEP0, Ping, ACK/NAK/

STALL/NYET

"Chapter 9"

TokenProcessorEP0, Ping, ACK/NAK/

STALL/NYET

"Chapter 9"

Outside InterfaceOutside Interface

High speed logicclock extraction

serialize/ deserialize

bit stuffNRZI

SYNC,EOP

High speed logicclock extraction

serialize/ deserialize

bit stuffNRZI

SYNC,EOP

16

16 EndpointsEndpoint FIFOS& control logic

EndpointsEndpoint FIFOS& control logic

16

CPU48 MHz 8051

CPU48 MHz 8051

Program & Data RAMProgram & Data RAM

Down

load

Cod

e

Down

load

Cod

e

Dat

a C

hann

el

GPIF

Single-Chip SolutionSingle-Chip Solution

FX2

May 9, 2001 10

USB BW: Endpoint BuffersUSB BW: Endpoint Buffers

512512

512512

512512

512512

EP2

EP4

512512

512512

512512

512512

EP2

512512

512512

512512

512512EP6

EP8

512512

512512

512512

512512

EP6

512512

512512

512512

512512

EP2

512512

512512EP6

10241024

10241024

EP2

10241024

10241024

EP6

10241024

10241024

EP2

10241024

10241024

10241024

EP2

10241024

10241024

512512

512512EP8

EP0 IN&OUTEP0 IN&OUT

EP1 INEP1 IN

EP1 OUTEP1 OUT 646464646464

646464646464

646464646464

646464646464

646464646464

646464646464

512512

512512EP8

May 9, 2001 11

EndpointEndpoint

FIFOSFIFOS

EndpointEndpoint

FIFOSFIFOSMicroprocessorMicroprocessorMicroprocessorMicroprocessorUSBUSB

OutsideWorld

OutsideWorld

(a) Low to Medium Speed(a) Low to Medium Speed

Data TransferSpeed EvolutionData TransferSpeed Evolution

May 9, 2001 12

Data TransferSpeed EvolutionData TransferSpeed Evolution

EndpointEndpoint

FIFOSFIFOS

EndpointEndpoint

FIFOSFIFOSInterfaceInterface

FIFOFIFOInterfaceInterface

FIFOFIFODMADMADMADMAUSBUSBUSBUSB OutsideOutsideWorldWorld

OutsideOutsideWorldWorld

(b) Faster(b) Faster

MicroprocessorMicroprocessorMicroprocessorMicroprocessor

RAM/FIFORAM/FIFORAM/FIFORAM/FIFO

May 9, 2001 13

Data TransferSpeed EvolutionData TransferSpeed Evolution

(c) Fastest(c) Fastest

EndpointEndpoint

FIFOSFIFOS

EndpointEndpoint

FIFOSFIFOSUSBUSB

OutsideWorld

OutsideWorld

MicroprocessorMicroprocessorMicroprocessorMicroprocessor

RAM/FIFORAM/FIFORAM/FIFORAM/FIFO

May 9, 2001 14

Quantum FIFOQuantum FIFO256x16256x16

256x16256x16

256x16256x16

256256x16x16256256x16x16

USBUSB

256x16256x16

I/OI/O

256256x16x16256256x16x16

256256x16x16256256x16x16

256256x16x16256256x16x16

1 clock1 clock

May 9, 2001 15

Quantum FIFOQuantum FIFO

256x16256x16

256x16256x16

256256x16x16256256x16x16

USBUSB

256x16256x16

I/OI/O

256256x16x16256256x16x16

256256x16x16256256x16x16

256256x16x16256256x16x16

256256x16x16256256x16x16

May 9, 2001 16

GPIF Control Structure GPIF Control Structure

StateMachine

6 Outputs

6 Inputs

RD

Y

WaveformDescriptor

28 bytes define up to 7programmable

intervals

00

CTL

01

10

11

RDY(FLG)

RDY(CPU)

8051 Register

addr 9 Outputs

EPnFLGSELEPnFLGSEL

EP2 EFFFPF

EP4

EP6

EP8

Transaction Count= 64KTransaction Count= 64KTransaction Count= 64KTransaction Count= 64K

May 9, 2001 17

GPIF: UDMA Read Example (Data in)GPIF: UDMA Read Example (Data in)

DMARQ DMACK STOPHDMARDYDSTROBEDATA

DMARQ DMACK STOPHDMARDYDSTROBEDATA

N1N1 N2N2 N3N3 N4N4 N5N5 N6N6

FLOW STATEFLOW STATE

CRCCRCDATADATA

17ns17ns

D1D1 D2D2 D3D3 D4D4

May 9, 2001 18

Architectural SummaryArchitectural Summary

Don’t let the CPU be a bottleneck– Use fast logic to do the transfers

Some type of DMA is essential– Even better--”Zero time” DMA transfers with

programmable control signals GPIF = General-Programmable Interface

Don’t let the CPU be a bottleneck– Use fast logic to do the transfers

Some type of DMA is essential– Even better--”Zero time” DMA transfers with

programmable control signals GPIF = General-Programmable Interface

May 9, 2001 19

Putting It All TogetherATAPI Throughput AnalysisPutting It All TogetherATAPI Throughput Analysis

38MB/s38MB/ssustainedsustained38MB/s38MB/s

sustainedsustained

Mass Storage Device

Mass Storage Device

FX2FX2USB 2.0USB 2.0HostHost

100MB/s100MB/s53MB/s53MB/s~17MB/s~17MB/s 96 MB/s96 MB/s

Winbench 99 Disk TestWinbench 99 Disk Test

May 9, 2001 20

Host Data Transfer Host Data Transfer

Data transfers are divided into 64K Byte packets Host sends packet read request

– Command Block Wrapper (CBW) Host sends 128 IN packet requests (Data reads)

– 128 * 512 = 64 KBytes Host requests status using IN request Device provides termination status

– Command Status Wrapper (CSW)

Data transfers are divided into 64K Byte packets Host sends packet read request

– Command Block Wrapper (CBW) Host sends 128 IN packet requests (Data reads)

– 128 * 512 = 64 KBytes Host requests status using IN request Device provides termination status

– Command Status Wrapper (CSW)

May 9, 2001 21

64K Block Read Analysis64K Block Read Analysis

ActivityActivity DelayDelay

CBWCBW DataData CSWCSW

43%43% 56%

4%4% 17%17%79%79%

(a)(a) (b)(b)

May 9, 2001 22

(a) Data Phase of Read(a) Data Phase of Read

8.8us8.8us

11.6us Typ.11.6us Typ.

NoNAKS!

NoNAKS!

May 9, 2001 23

(B) Read Command, CSW(B) Read Command, CSW

662uS662uS

May 9, 2001 24

USB Disk Drive SummaryUSB Disk Drive Summary

USB 2.0 is a significant improvement over 1.1 Room for improvement

– Increase number of packets per uFrame Biggest improvement in data transfer stage

Now 5.5 BULK packets per microframe, Spec allows 13.

– Reduce latencies Improvement in CSW status phase

USB 2.0 and FX2 have the headroom when the host BW bottleneck is improved

USB 2.0 is a significant improvement over 1.1 Room for improvement

– Increase number of packets per uFrame Biggest improvement in data transfer stage

Now 5.5 BULK packets per microframe, Spec allows 13.

– Reduce latencies Improvement in CSW status phase

USB 2.0 and FX2 have the headroom when the host BW bottleneck is improved

May 9, 2001 25

ConclusionConclusion

Bandwidth will improve– USB Controller programmability is important

New ATA modes are possible– Many ‘disk-like’ standards

Compact Flash, etc.– GPIF-performance and flexibility is required to support

Other non-disk interfaces must be supported– EPP, PCMCIA, UTOPIA, etc.– Device programmability and GPIF flexibility

Bandwidth will improve– USB Controller programmability is important

New ATA modes are possible– Many ‘disk-like’ standards

Compact Flash, etc.– GPIF-performance and flexibility is required to support

Other non-disk interfaces must be supported– EPP, PCMCIA, UTOPIA, etc.– Device programmability and GPIF flexibility