mc14017b

MOTOROLA CMOS LOGIC DATAMC14017B74

The MC14017B is a fivestage Johnson decade counter with builtin codeconverter. High speed operation and spikefree outputs are obtained by useof a Johnson decade counter design. The ten decoded outputs are normallylow, and go high only at their appropriate decimal time period. The outputchanges occur on the positivegoing edge of the clock pulse. This part canbe used in frequency division applications as well as decade counter ordecimal decode display applications. Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading DividebyN Counting Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower

Schottky TTL Load Over the Rated Temperature Range PinforPin Replacement for CD4017B Triple Diode Protection on All Inputs

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

0.5 to + 18.0

V

Vin, Vout

Input or Output Voltage (DC or Transient)

0.5 to VDD + 0.5

V

lin, lout

Input or Output Current (DC or Transient),per Pin

10

mA

PD

Power Dissipation, per Package

500

mW

Tstg

Storage Temperature

65 to + 150

C

TL

Lead Temperature (8Second Soldering)

260

C* Maximum Ratings are those values beyond which damage to the device may occur.Temperature Derating:

Plastic P and D/DW Packages: 7.0 mW/C From 65C To 125CCeramic L Packages: 12 mW/C From 100C To 125C

LOGIC DIAGRAM

CLOCKCLOCK

ENABLE CARRY

RESET

Q5 Q1 Q7 Q3 Q9117621

12

Q0 Q6 Q2 Q3 Q43 5 4 9 10

14

13

15

CCDR R

Q

Q

CCDR R

Q

Q

CCDR R

Q

Q

CCDR R

Q

Q

CCDR R

Q

Q

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 31/94

L SUFFIXCERAMICCASE 620

ORDERING INFORMATIONMC14XXXBCP PlasticMC14XXXBCL CeramicMC14XXXBD SOIC

TA = 55 to 125C for all packages.

P SUFFIXPLASTICCASE 648

D SUFFIXSOIC

CASE 751B

BLOCK DIAGRAM

FUNCTIONAL TRUTH TABLE(Positive Logic)Clock Decode

Clock Enable Reset Output=n0 X 0 nX 1 0 nX X 1 Q0

0 0 n+1X 0 n

X 0 n1 0 n+1

X = Dont Care. If n < 5 Carry = 1,Otherwise = 0.

CLOCK

CLOCKENABLE

RESET

14

13

15 CoutQ9Q8Q7Q6Q5Q4Q3Q2Q1Q0 3

2471015691112

VDD = PIN 16VSS = PIN 8

MOTOROLA CMOS LOGIC DATA75

MC14017B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

VDDVdc

55C

25C

125C

Unit

Characteristic

Symbol

VDDVdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage 0 LevelVin = VDD or 0

1 LevelVin = 0 or VDD

VOL

5.01015

0.050.050.05

000

0.050.050.05

0.050.050.05

Vdc

1 LevelVin = 0 or VDD

VOH

5.01015

4.959.9514.95

4.959.9514.95

5.01015

4.959.9514.95

Vdc

Input Voltage 0 Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

1 Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

VIL

5.01015

1.53.04.0

2.254.506.75

1.53.04.0

1.53.04.0

Vdc

1 Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

VIH

5.01015

3.57.011

3.57.011

2.755.508.25

3.57.011

Vdc

Output Drive Current(VOH = 2.5 Vdc) Source(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH

5.05.01015

3.0 0.64 1.6 4.2

2.4 0.51 1.3 3.4

4.2 0.88 2.25 8.8

1.7 0.36 0.9 2.4

mAdc

(VOL = 0.4 Vdc) Sink(VOL = 0.5 Vdc)(VOL = 1.5 Vdc)

IOL

5.01015

0.641.64.2

0.511.33.4

0.882.258.8

0.360.92.4

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance(Vin = 0)

Cin

5.0

7.5

pF

Quiescent Current(Per Package)

IDD

5.01015

5.01020

0.0050.0100.015

5.01020

150300600

Adc

Total Supply Current**(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs, allbuffers switching)

IT

5.01015

IT = (0.27 A/kHz) f + IDDIT = (0.55 A/kHz) f + IDDIT = (0.83 A/kHz) f + IDD

Adc

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.**The formulas given are for the typical characteristics only at 25C.To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfkwhere: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.0011.

This device contains protection circuitry to guard against damagedue to high static voltages or electric fields. However, precautions mustbe taken to avoid applications of any voltage higher than maximum ratedvoltages to this high-impedance circuit. For proper operation, Vin andVout should be constrained to the range VSS (Vin or Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltagelevel (e.g., either VSS or VDD). Unused outputs must be left open.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

CoutCE

CLOCK

RESETVDD

Q8Q4Q9

Q2Q0Q1Q5

VSS

Q3Q7Q6


SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25C)

Characteristic

Symbol

VDDVdc

Min

Typ #

Max

Unit

Output Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,tTHL

5.01015

1005040

20010080

ns

Propagation Delay TimeReset to Decode OutputtPLH, tPHL = (1.7 ns/pF) CL + 415 nstPLH, tPHL = (0.66 ns/PF) CL + 197 nstPLH, tPHL = (0.5 ns/pF) CL + 150 ns

tPLH,tPHL

5.01015

500230175

1000460350

ns

Propagation Delay TimeClock to CouttPLH, tPHL = (1.7 ns/pF) CL + 315 nstPLH, tPHL = (0.66 ns/pF) CL + 142 nstPLH, tPHL = (0.5 ns/pF) CL + 100 ns

tPLH,tPHL

5.01015

400175125

800350250

ns

Propagation Delay TimeClock to Decode OutputtPLH, tPHL = (1.7 ns/pF) CL + 415 nstPLH, tPHL = (0.66 ns/pF) CL + 197 nstPLH, tPHL = (0.5 ns/pF) CL + 150 ns

tPLH,tPHL

5.01015

500230175

1000460350

ns

TurnOff Delay TimeReset to CouttPLH = (1.7 ns/pF) CL + 315 nstPLH = (0.66 ns/pF) CL + 142 nstPLH = (0.5 ns/pF) CL + 100 ns

tPLH

5.01015

400175125

800350250

ns

Clock Pulse Width

tw(H)

5.01015

25010075

1255035

ns

Clock Frequency

fcl

5.01015

5.01216

2.05.06.7

MHz

Reset Pulse Width

tw(H)

5.01015

500250190

25012595

ns

Reset Removal Time

trem

5.01015

750275210

375135105

ns

Clock Input Rise and Fall Time

tTLH,tTHL

5.01015

No Limit

Clock Enable Setup Time

tsu

5.01015

350150115

1757552

ns

Clock Enable Removal Time

trem

5.01015

420200140

26010070

ns

* The formulas given are for the typical characteristics only at 25C.#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.


MC14017B

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

VDD

VoutVSS

VDD

VSS

S1

S1

A

B

VSS

ID

EXTERNALPOWERSUPPLY

CLOCKENABLE

RESET

CLOCK Cout

Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9

OutputSink Drive

OutputSource Drive

DecodeOutputs

Clock todesiredoutputs

(S1 to B)(S1 to A)

CarryClock to 5

thru 9(S1 to B)

S1 to A

VGS = VDDVDDVDS = Vout VDDVout

Figure 2. Typical Power Dissipation Test Circuit

VDD

VSS

ID

CLOCKENABLE

RESET

CLOCK

Cout

Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9

500 F 0.01 FCERAMIC

PULSEGENERATOR

fc

CL CL CL CL CL CL CL CL CL CL CL

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-quential within each stage and from stage to stage, with no dead time (except propagation delay).

Figure 3. Counter Expansion

RESETCLOCKCE MC14017BQ0 Q1 Q8 Q9

9 DECODEDOUTPUTS

CLOCKFIRST STAGE INTERMEDIATE STAGES LAST STAGE

RESETCLOCKCE MC14017BQ0Q1 Q8 Q9

RESETCLOCKCE MC14017B

Q1 Q8 Q9

8 DECODEDOUTPUTS

8 DECODEDOUTPUTS


Figure 4. AC Measurement Definition and Functional Waveforms

Pcp NcpCLOCK

CLOCKENABLE

tremRESET

20 nsQ0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Cout

tPHL

tPHLtPLH

tPLH

tPLH

tPLH

tPLH

tPLH

tTHL

tTHL

tTLH

tPLH

tPLH

tPLH

tTLHtPLH

tPHL

tPHL

tPHL

tPHL50%

tPHL

tPHL90%

10%tTHL

tPHL

tTHL tPHL

tTHL

tTLHtTHL

tPHL

trem tsu 20 ns 20 ns

20 ns20 ns

tPLH

90%10% 50%

tTLH

tTLH

tTLH

tTLH

tTLH

tTHL

tTHL

tTHL

tTHLtPHL

tTHL

90%50%

10%

20 ns

tPLH

tTLH

VDDVSS

VDDVSS

VDDVSS

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL

VOHVOL


MC14017B

OUTLINE DIMENSIONS

P SUFFIXPLASTIC DIP PACKAGE

CASE 64808ISSUE R

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.

A

B

F CS

HG

DJ

L

M

16 PL

SEATING

1 8

916

KPLANET

MAM0.25 (0.010) T

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.740 0.770 18.80 19.55B 0.250 0.270 6.35 6.85C 0.145 0.175 3.69 4.44D 0.015 0.021 0.39 0.53F 0.040 0.70 1.02 1.77G 0.100 BSC 2.54 BSCH 0.050 BSC 1.27 BSCJ 0.008 0.015 0.21 0.38K 0.110 0.130 2.80 3.30L 0.295 0.305 7.50 7.74M 0 10 0 10 S 0.020 0.040 0.51 1.01

L SUFFIXCERAMIC DIP PACKAGE

CASE 62010ISSUE V

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMICBODY.

A

B

T

FE

G

N K

C

SEATINGPLANE

16 PLDSAM0.25 (0.010) T

16 PLJSBM0.25 (0.010) T

M

L

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.750 0.785 19.05 19.93B 0.240 0.295 6.10 7.49C 0.200 5.08D 0.015 0.020 0.39 0.50E 0.050 BSC 1.27 BSCF 0.055 0.065 1.40 1.65G 0.100 BSC 2.54 BSCH 0.008 0.015 0.21 0.38K 0.125 0.170 3.18 4.31L 0.300 BSC 7.62 BSCM 0 15 0 15 N 0.020 0.040 0.51 1.01

16 9

1 8


OUTLINE DIMENSIONS

D SUFFIXPLASTIC SOIC PACKAGE

CASE 751B05ISSUE J

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATINGPLANE

F

JM

R X 45

G

8 PLPB

A

M0.25 (0.010) B S

T

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019

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MFAX: [email protected] TOUCHTONE 6022446609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://DesignNET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be providedin Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patentrights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implantinto the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create asituation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended orunauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registeredtrademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC14017B/D

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mc14017b

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