The Intel MCS-48 family of single-chip microcom-puters contains at least nine different microcomputerchips having a common instruction set but differentamounts of on-chip read-only memory, read/write memory, and input/output (see Table 1). Ac-

Table 1.MCS-48 microcomputers.

ON-CHIP ON-CHIPPACKAGE PROGRAM DATA

PART # SIZE MEMORY MEMORY I/O(pins) (bytes) (bytes) (lines)

8048 40 1K ROM* 64-* 278748 40 1K EPROM* 64** 278035 40 none' 64* 278049 40 2K ROM 128** 278039 40 none* 128** 278021 28 1K ROM 64 218022 40 2K ROM 64 23 plus 2 8-bit A/D conv.8041 40 1K ROM 64 18 plus master sys. intf.8741 40 1K EPROM 64 18 plus master sys. intf.

Expandable to 4K with external chipsPlus 256 bytes or more of external data memory with external chips

Table 2.MCS-48 expander chips.

ON-CHIP ON-CHIPPACKAGE PROGRAM DATA

PART # SIZE MEMORY MEMORY I/O(pins) (bytes) (bytes) (lines)

8355 40 2K ROM none 168755 40 2K EPROM none 168155/56 40 none 256 22 plus timer/counter8243 24 none none 16

A system designer and teacher,who has made liberal use ofmicrocomputers in his own workand whose students have designed8048 processors, reviews thecapabilities and limitations of theMCS-48 family of microcomputers.

cording to Intel, the MCS-48 family was originallyaimed primarily at the "4-bit market"-users of In-tel's 4040 and other low-cost microcontrollers. Re-cent entries into the family (the 8021,8022,8041, and8741) are increasingly specialized for low-end micro-controller applications. The MCS-48 family has metthis market very well.TheMCS-48 family was also aimed at a second mar-

ket-applications that require an expandable, single-chip, general-purpose microcomputer. As shown inTable 2, several expansion chips are available to pro-vide an MCS-48 computer with up to 4K bytes ofpro-gram ROM, 256 or more bytes of external RWM, andas many I/O bits as a designer would ever need. In ad-dition, the external I/O bus of the MCS-48 familyallows easy interfacing of standard 8080/8085-com-patible peripheral chips. Nevertheless, the architec-ture of the MCS-48 family makes it difficult to use inmany general-purpose applications, where a morecapable 8-bit architecture is required.

Basic architecture

Figure 1 shows the basic structure of an MCS-48microcomputer chip. (Table 1 gives the facilitiesavailable for each of the microcomputers in theMCS-48 family that had been announced by late1978.) The first member of the family was introducedin late 1976-the 8048 with 1K bytes ofon-chip ROM,64 bytes of RWM, timer/counter, and 27 I/O bits. Adetailed description of the entire family can be foundin the user's manual published by Intel.'The MCS-48 is a single-accumulator architecture.

Program memory and data memory are logically andphysically separated (thus, the MCS-48 is not a von

0018-9162179/0020-0022$00.75 © 1979 IEEE

0_..o

COMPUTER22

Neumann machine!). The maximum program ad-dress space (including external ROM) supported bythe architecture is 4K bytes. There are amaximum of256 bytes of on-chip (internal) data memory, ofwhich128 bytes are implemented in the current familyleader, the 8049. In addition to internal data memory,the MCS-48 directly supports 256 bytes of externaldata memory.Most MCS-48 family members have 27 1/0 pins, ar-

ranged as three 8-bit ports, two test inputs, and an in-terrupt input. Additional pins are provided for suchfunctions as power-on reset, single-stepping, andmemory and I/O expansion strobes. One 8-bit portand part of a second are used to form a multiplexedaddress and data bus for I/O and memory expansion.The MCS-48 has a single-level interrupt, system

(only one interrupt in service at a time) and accepts in-terrupts from two sources-its internal timer/counter and an external interrupt input pin. Inter-rupt calls and returns automatically push and popthe program counter and certain internal status flagsusing a stack in the internal data memory.

Program store and program control

The MCS-48 architecture supports a maximum of4K bytes of program store, configured as shown inFigure 2. However, a close look at program-storeorganization shows that the MCS-48 was originallydesigned as a 2K-byte machine, with the second2K-byte capability added as a clumsy afterthought.This creates two problems with the addressing mech-anism.

First, theprogram counter is really only 11 bits andthus addresses instructions only within a 2K-bytebank of program store. Jump and subroutine call in-structions likewise specify an 11-bit address. Theproblem, then, is how to provide a 12th address bit.

Intel's solution is as follows. Provide an internalflag, MB, that can be set and cleared by two instruc-tions (SEL MB1 and SEL MBO, respectively). Wheneverajump or subroutine call is executed, take the 11 low-order PC bits from the instruction, and load the high-order bit from MB. On subroutine calls and returns,push and pop the entire 12-bit address.There are some problems with this solution. First,

in a general sequence of jumps and calls in a 4K sys-tem, we don't always know where we came from, andtherefore we don't know the current value of MB. Soin general, a SEL MBi instruction must precede everyjump or call. Naturally the programmer can some-times avoid this instruction on a case-by-case basis,but this is another thing to worry about.Having solved the first problem, we think we un-

derstand the addressing mechanism until we writeour first interrupt routine. Then we wake up in themiddle of the night thinking, "Whoops! MB can't beread as part of the processor state PSW. But MBmust be set to anewvalue in order to dojumps withinthe interrupt routine. How can the old value be re-stored onreturn?"We lie awake a few hours dreamingup possible solutions-don't use calls or jumps in in-

TO -

Tl-

INT -10

RESET-_(

6 MHz0

P10-17

P24-27

-_ PROG

P P20-23

DBO-7

-_ ALE

D_00 PSEN

)--lo WR

EA-

Figure 1. Basic structure of a typical member of Intel's MCS-48 familyof microcomputers.

ADDRESS(hex)FFF

PAGE MEMORY(hex) BANK

F

FOOEFF

E

EOODFF

eV

C-

o

N

Co-

C:

zo

9008FF

88007FF

4003FF

3002FF

3

2

2001FF

0

100OFF

L L 000Figure 2. MCS-48 program memory.

February 1979

l

23

+5

.7

.M#.w# 4 r.m. . .r4.r'{.n..

4 .

.

tfl.. ..4a.

.

ft

4

terrupt routines; determine the value of MB experi;mentally by doing a jump to a fixed location and see-ing whether it winds up in MBO or MB1; keep a soft-ware copy of MB, updating it (with interrupts dis-abled, of course) every time we do a SEL MBi; make allthe code fit in 2K, as we expected to do at the start ofthe project; and so on. The next morning we read thefine print to discover that theMCS-48 forces the mostsignificant bit of the program counter to 0 during allinterrupt routines. We should put all of our interruptcode in the bottom 2K of memory and not touch MB;in fact, we should forget that MB exists!The requirement to put interrupt code in the bot-

tom 2K makes the MCS-48 very difficult to use as a4K machine in a real-time application. Not only mustthe basic interrupt service routine be in the bottom2K but also any utility routine that might be calledbyit-that is, any code executed before an interrupt re-turn instruction is executed. This could be well overhalf the code in an interrupt-driven environment.But the main problem we find with MCS-48 pro-

gram store, after writing half of our applications pro-grams, is that the address space is just too small.With only two chips (and soon withjust one, I'm sure)we can fill the entire 4K-byte address space of theMCS-48 with code for our original application, newfeatures, diagnostics, and-of course-patches.

Conditional jumps specify an 8-bit targetaddress in the current page; it would befar more useful to have a signed offset

from the current address.

The annual halving of the cost of IC memory im-plies that every year we will need another address bitfor the maximum-size application program (sincemost evolving products tend to use the decreasedmemory cost to increase features, not to reduce pro-duct cost). Clearly, then, a 4K limit is too low for anynew architecture, even a single-chip microcomputer.Besides the 2K memory banks, program store is

also divided into 256-byte pages. Conditional jumpsspecify an 8-bit target address in the current page. Itwould be far more useful to have a signed offset fromthe current address; this would increase the like-lihood of being able to use the short jump address,since most branch targets are within 128 bytes of thebranch instruction.2 More importantly, it wouldeliminate the partitioning problem created whenmany procedures must be packed into the memoryspace and split across page boundaries.The only indirect jump instruction also uses an

8-bit target address in the current page. Verystrangely, this instruction uses an 8-bit value in theaccumulator not as the target address, but as a point-er to a program-store byte in the current page thatcontains the target address. So the page containingthe indirect jump instruction must also contain all ofthe routines to be jumped to, as well as a silly littletable that contains their starting addresses in thepage. This not only wastes space and time, but,

February 1979

worse, makes it impossible to dynamically compute atarget address after assembly time, since the jumptable is in ROM. In my recent experience, three ex-perienced programmers have coded MCS-48 indirectjumps improperly, believing "The manual must havea typo-the contents of the accumulator must be thetarget address itself." In any case, instructions sup-porting indirect jumps and calls anywhere in the pro-gram store (12-bit address) would be far more useful.

Arithmetic and logical operations

The MCS-48 contains a single accumulator inwhich arithmetic and logical operations take place.Unary operations on the accumulator are as follows:increment,decrement,-clear,one's complement,decimal adjust,swap nibbles,rotate left,rotate left with carry,rotate right, androtate right with carry.Binary operations combine the accumulator and an

operand specified by one of the addressing modes de-scribed in the next section. The binary operations are:

add,add with carry,AND,OR, andexclusive OR.There are also "data-move" operations that load or

store the accumulator.The main difficulty with MCS-48 operations is not

the operations themselves but the lack of conditioncodes for testing their results. Only the accumulatorcan be tested for zero or negative, and an overflow bitis not provided, making comparisons of signed two's-complement numbers very frustrating.

Operands

Most data moves and binary operations use an on-chip read/write internal data memory (see Figure 3)accessible by two addressing modes: REGISTER andINTERNAL REGISTER INDIRECT. The three other ad-dressing modes are EXTERNAL REGISTER INDIRECT,IMMEDIATE, and ACCUMULATOR INDIRECT.

In REGISTER mode an operand is contained in aregister specified by a 3-bit field in the instruction. Aflag bit BS, set by a SEL RBi instruction, specifies oneof two 8-byte register banks, corresponding to inter-nal data memory locations 0-7 if BS is 0 and 24-31 ifBS is 1. The specified register may be loaded with animmediate value, moved to or from the accumulator,combined with the accumnulator by arithmetic orlogical operations, incremented, decremented, orused as a loop counter.

25

a,Cl)

Z

:z

0-

.0

x

m

86N

N

z

CL

ADDRESS(decimal)

255

128127

6463

3231

2423

87

Figure 3. MCS-48 internal data memory.

INTERNAL REGISTER INDIRECT allowsRl in the current register bank to be us4

pointer to internal data memory. The admay be loaded with an immediate value,from the accumulator, combined withlator, or incremented (but for some obnot decremented, even though the neceexists in the instruction set).Locations 8-23 of the internal data mi

served for a return address stack (8 entper entry). These locations are written I

and subroutine calls and read-by interrroutine return instructions. The stackmaking it hard to write procedural code.portant in larger programs ( 2K-4K bytgrammer must constantly worry abou,quences and.generally enable interrupttop level of the program to avoid ovestack.There are no instructions to directly I

byte. However, the stack can be ri

veniently written or read by extractirpointer field from the PSW, building thiaddress, and using INTERNAL REGIST]mode.

26

The architecture also supports up to 256 bytes ofFUNCTION external data memory (which resides on a separate

chip), accessed by EXTERNAL REGISTER INDIRECTmode. Either RO or Rl in the current register bankmay be used as an 8-bit pointer to external datamemory; the addressed byte may be copied into theaccumulator or written from the accumulator.Since pointers are contained in 8-bit registers, the

maximum amount of directly accessible data mem-ory supported by the MCS-48 architecture is 256bytes internal plus 256 bytes external. However,bank switching via I/O bits can be used to addressany desired amount of additional external datamemory.The modes for reading operands from program

store are rather limited. In IMMEDIATE mode anoperand is contained in the byte following the in-struction; immediate operands can either be loaded

REGISTER into or combined with the accumulator or be loadedBANK 1 into internal data memory with REGISTER or INTER-

NAL REGISTER INDIRECT modes.In ACCUMULATOR INDIRECT mode the accumulator

is used as an 8-bit pointer to an operand in either thecurrent page orpage 3 ofprogram store; only one typeof operation uses this mode, and it loads the accumu-lator with the specified operand.

STACK A number of instructions specify some "special"operands implicitly, such as the program statusword, I/O ports, timer/counter, carry bit, and two1-bit flags, FO and Fl.The MCS-48 addressing modes are simple, but they

provide most of the facilities a program needs. Still,REGISTER there are some deficiencies. The most serious prob-BANK O lem is the way in which operands in program store

are addressed. Since program store only in the cur-rent page and in page 3 can be read through a pointer,either lookup tables must all be located in page 3 orthe code that reads each table must be in the samepage as the table. This is inconvenient if more than

either RO or one 256-byte translation table is needed. It alsoed as an 8-bit makes it difficult to do a ROM checksum self-testdressed byte routine-a checksum subroutine would have to bemoved to or placed in every page ofprogram store (and since therethe accumu- is no indirect subroutine call, the main checksum pro-scure reason gram would have to contain a separate call instruc-ssary "hole" tion to each page's checksum routine).

For most programs, the method of indirectly ad-emory are re- dressing data memory through RO and Rl is accept-tries, 2 bytes able, but, for some data-structure manipulations, oneby interrupts wishes for one or two more registers that could beupt and sub- used as pointers.is too small, The 256-byte limit on directly addressable internal, which is im- data memory is too loqw. The 8049 already contains;es). The pro- 128 bytes of RWM, and Intel should soon be able toit calling se- provide the full 256 bytes ofRWM on one chip. Thes only at the architecture cannot make straightforward use ofrflowing the technology improvements for more RWM once this

limit is reached.push or pop aather incon-kg the stack- Input/output and interruptsappropriateER INDIRECT Most MCS-48 microcomputers have three 8-bit I/O

ports, as shown in Figure 1. Two of the ports (1 and 2)

COMPUTER

n

are "quasi-bidirectional," an interfacing arrange-ment shown in Figure 4. This type of I/O port wasfirst introduced in the Fairchild F8.3 In this arrange-ment, each I/O pin is both an open-drain output andan input pin with a high-inpedancepullup to the logic1 level. When a pin is used for output, the correspond-ing input buffer is unused except, possibly, for check-ing the output value. When a pin is used for input, thecorresponding output bit must be set to logic 1 sothat the I/O device drives only the high-impedancepullup. This can be contrasted with a tristate I/Oport, which provides both active pullup and activepulldown in output mode and high impedance in in-put mode. Electrically, tristate I/O is more desirable,but it requires extra control bits to set the I/O direc-tion for each port or bit. Intel has improved the quasi-bidirectional design by briefly providing activerather than passive pullup whenever a 1 is written tothe port, which speeds up 0-to-1 transitions.What quasi-bidirectional I/O means to the pro-

grammer is that input data on the port is logicallyANDed with the current output. Ports 1 and 2 are setto all l's at system reset, and the programmer mustleave bits intended for inputs set at output value 1 atall times. The third port (bus) has conventionaltristate outputs and can be used for eight strobed in-puts, for eight strobed outputs, or for adding externalprogram or data memory.Four operations on the ports are available:read input value into accumulator (IN),load output latch from accumulator (OUTL),logical AND output latch with immediate mask

(ANL), andlogical OR output latch with immediate mask (ORL).The logical operations allow a program to set or

clear any bit or group of bits in one instruction.However, since the mask is an immediate value inprogram store, the bits to be set or cleared must beknown at assembly time. Otherwise, a copy of theoutput value must be kept in data memory, combinedwith the mask by logical operations on the accumu-lator, and loaded into the port. (In general, the quasi-bidirectional interface prevents simply reading theport to get the old value of the output latch.)A novel "expander-port" arrangement allows four

external 4-bit I/O ports to be added to an MCS-48using a five-wire interface. Again, four operations onthe ports are available:read input value into accumulator,load output latch from accumulator,logical AND output latch with accumulator, andlogical OR output latch with accumulator.Only the low-order four bits of the accumulator are

used in these operations. For these ports, dynamicselection of mask bits is possible because the mask isin the accumulator. On the other hand, dynamic selec-tion takes more overhead because the accumulatormust be loaded with the mask (and then possibly re-stored to its old value).Both the on-chip and expander I/O port instruc-

tions contain the port number as an immediate value

ORL, ANL

INTERNAL 5KD|BUS

D

OUTL

WRITE-PULSE

.INPUTBUFFER

IN J

Figure 4. "Quasi-bidirectional" 1/0 port.

in the instruction; it is not possible to specify the portnumber dynamically in a register. This makes it im-possible to write reusable I/O handlers for identicaldevices on different ports of the MCS-48 or of thesame expander chip. The same problem exists in theMCS-48's older brother, the 8080. However, it is lessserious in the MCS-48 for two reasons. First, theMCS-48 is intended for smaller applications less like-ly to employ many copies of the same I/O device. Sec-ond, the available I/O expansion modes do allowdynamic device selection when each device uses aseparate IO chip.The processor architecture directly supports only

256 bytes of external data memory and four external4-bit I/O ports. However, the amount of external datamemory and I/O can be increased to any practicalamount using on-chip I/O-port bits to implementprogram-controlled bank switching.In addition to the I/O ports, an MCS-48 has three

additional input pins that can be tested by condi-tional jump instructions. All are multipurposepins-TO, which can be set up as a clock outputunderprogram control; Ti, which can be used as the inputto the on-chip timer/counter; and the external inter-rupt input.The MCS-48 accepts interrupts from two sources-

a level-sensitive input pin and an on-chip timer/counter. When an interrupt is serviced, the 12-bit PCand four status bits (carry, half carry, flag 0, registerbank select) are pushed onto the internal stack.Depending on the source, a jump to either location 3or location 7 is taken. The interrupt system is single-level; interrupt service routines cannot be inter-rupted. An interrupt return instruction restores thePC and status bits and allows further interrupts tobeserviced.At the time of this writing, the Ti interrupt input is

generally useless for counting or timing asyn-chronous external events, because the current chip

February 1979 27

Figure 5. Type I bus control signals.

features a poorly designed synchronizer thatsometimes misses input edges and hence skipscounts. This is the second time in six months that Ihave seen an LSI chip whose designers were ap-parently unaware of problerms in synchronizer design(the other was the Z80-SIO, which Zilog has since fix-ed). I would suggest that chip designers read some ofthe papers on the subject4-6 and that academics warntheir students of the increasing likelihood of syn-chronization problems in modern system design.

Ease of programming

Compared to some of the older 4-bit and 8-bit micro-processors, the MCS-48 is a nice machine to program,but it leaves much to be desired compared with anM6801, a Z8, or even an 8085. The single-accumulatorarchitecture, the lack of index registers, and theabsence of even a direct data memory addressingmode means that the programmer must constantlybe moving things back and forth between the ac-cumulator, the two "pointer" registers RO and RI,and the rest of the data memory (and keeping track ofthem!). One may write macros to ease the burdensomewhat, at the expense of more inefficient code inthe cramped address space. For example, one canwrite a macro to simulate a direct data-memory-addressing mode:

LDA MACRO MEMADDRMOV RO, #MEMADDRMOV A,@ROENDM

COMPUTER

TYPEPROCESSOR

ADDR I)

(DATAAIA

READT P

(ADATAWRITE

W-R

28

TYPE Z

ADDR

(/Wlff UR

WRITE

DDAATA

REO0

Figure 6. Type Z bus-control signals.

To use such macros, however, the programmer mustgive up some registers for use by the macros. In theabove example, macros would use RO, leaving onlyRI available to the program as a pointer variable.(Buffer copying and other routines requiring two ormore pointers get to be a problem.)The lack of symmetry in the instruction set also

creates programming headaches. For example, whyare there INC RO, DEC RO, and INC @RO instructions, butnot DEC @RO? Or, why can we conditionally jump on

C,Z, TO, and Ti conditions true or false, buton FO, Fl,TF, and accumulator bits only true? Except for ac-

cumulator bits false, the proper "holes" exist in theinstruction set; in fact, it probably took more logic toturn the instructions off than to let them work. I havebeen told that these "unimportant" instructionsleave room for future enhancements, but any worth-while architectural enhancements would requirechanges more sweeping than a few special-purposeopcodes.While nice programs can be written for the

MCS-48, they-take more effort than those written for

Figure 7. Acceptable Z-to-I interface.

Figure 8. Unacceptable 1-to-Z interface.

a "general-purpose" architecture, Programming dif-ficulty and expense also increase as webump againstthe memory limits of the 8048. If we are writing oneshort (< 1K-byte) program and shipping 50,000 unitswith it, the programming expense is quite justifiable.If we are writing 10 different 2K- to 4K-byte pro-

grams, each of which will be shipped with 5000 units,we might be better off selecting a cleaner (albeit moreexpensive) machine.

Some electrical characteristics

The MCS-48 uses Intel's reliable n-channel silicon-gate MOS process. Several second sources for the

February 1979

TYPE IRIPHERAL

ADDR, R/W am,

RD or WR

TYPE 1 TYPE ZPROCESSOR PERIPHERAL

ADDR AM

RD or WR

R/W --_-_-_-_-___

N IJ

k .E-0

29

family have been announced-AMD, NEC, Signe-tics, Siemens, Intersil, RCA. Both Intersil and RCAhave announced plans for CMOS 'versions of MCS-48chips.The MCS-48 chips use a single +5 volt supply and

have logic input and output levels that are fully TTLcompatible. As with all MOS microprocessors, theoutput drive is limited-typically four or five low-power Schottky (LSTTL) unit loads.MCS-48 chips contain an oscillator to generate the

processor clock (nominally 6 MHz) from an externalcrystal or RC circuit. It is also possible to connect anexternal clock directly to the oscillator input. Theoutput of the oscillator feeds a divide-by-threecounter whose output (nominally 2 MHz) controls theinternal states of the processor. Since the divide-by-three counter cannot be synchronized externally, pro-cessor I/O cannot be referenced very well to the6-MHz clock for tricky interfaces, nor can processorsbe run in lock-step from a common clock in a tri-plicated microcomputer (author's pet project).

The MCS-48 family satisfied the usualIntel strategy of being the first in the

marketplace with an imperfect but usefulproduct.

The MCS-48 chips have an active-low reset inputpin connected to an internal high-impedance pullupresistor and Schmitt trigger. Thus, power-on resetcan be accomplished by an external 1 mF capacitor. Itis a little more difficult to add a logic-controlled reset(for example, by a watchdog timer), since open-col-lector or discrete transistor drive is required. Andunless the driver circuit is sophisticated, a logic-commanded reset will disable the processor for a longtime, due to the time constant of the power-on resetcircuit-about 200 msec. In any case, reset destroysthe state of the processor. It would be nice to have-anonmaskable interrupt (as in the 8085) that could beused for applications such as watchdog timers.

Development tools

Intel supports two major development tools for theMCS-48 family-a cross assembler and an in-circuitemulator, ICE, both of which run on an Intel MDSmicrocomputer development system. Unfortunately,Intel does not support any MCS-48 assemblers orsimulators that run on a large computing system, anecessity for any large development project.However, they can be obtained from independentsoftware houses and consultants such as Microtec.

Intel MDS software for the MCS-48 lacks the con-sistency one expects from a good set of softwaretools. For example, there are at least three very dif-ferent syntaxes that an engineer or programmermight use to change the value of amemory location inthe MDS, depending on whether the monitor, ICE, or

PROM programmer is being used. The monitor has anice syntax that allows us to open a location, changeit, and continue to the next location with a smallnumber of keystrokes. In ICE, to read and changefour locations, we must type (machine type under-lined):

*_CBYTE 144 TO 1470144H= 01H 3AH BFH 59H* CBYTE 144=11,27,FF,6A

To do the same thing in the PROM programmer, theprogrammer types:

* DISPLAY FROM 144 TO 147009001 3ABF59* CHANGE 144=11,27,FF,6A

In either syntax, one wastes keystrokes, and it's easyto lose track of the address in a long string. This isn'ttoo terrible until we discover that ICE has inter-preted and printed addresses and data in hex, whilethe PROM programmer has assumed inputs in deci-mal and printed outputs in hex (except for input FF,which the PROM programmer rejects because itlooks like an assembler label!).Another constant annoyance is that the MDS ac-

cepts only the RUB character for deleting characters(echoing the deleted character); backspace is not sup-ported. It would have been easy enough to supportboth erase characters, making both teleprinter andCRT users happy.

Conclusion

The MCS-48 microcomputer family was a reason-able contribution to the state ofthe artwhen it was in-troduced in 1976, in spite of its flaws. It achieved itsdesign goals and satisfied the usual Intel strategy ofbeing the first in the marketplace with an imperfectbut useful product.The MCS-48 is an acceptable choice for applica-

tions with initial estimated requirements of less than1K bytes of program store, 64 bytes of data memory,and only one or two different programs to be devel-oped. Designers whose applications require morememory or different programs in different chipsshould seek a more general-purpose architecture,such as the Z8 or 6801.

I have spent much of this article complaining thatthe MCS-48 is not a general-purpose 8-bit microcom-puter. This may seem unfair, since some people at In-tel claim the MCS-48 was never intended to go muchbeyond the old 4-bit market. So why criticize it onthat basis? First, to help designers who might other-wise be tempted to use it in a larger application (Intelsales engineers frankly recommend their three-chip8085 system in such cases). Second, to help designerswho have already selected the MCS-48 for a larger ap-plication. Third, because discussion of generalsystem requirements should benefit future systemdesigners and chip designers alike. Finally, becauseIntel does not now offer a clean architecture suitablefor the more general-purpose, single-chip, expan-dable microcomputer market, and I think theyshould. *

COMPUTER30

Acknowledgments

I appreciate the comments ofmy colleagues duringthe preparation of this article, especially those fromPrem Jain, Paul Frantz, Ed Yarwood, and DaveStearns. The comments of the reviewers were alsovery helpful. Thanks go to Dennis Allison for sug-gesting this article over a year ago, and to BernardPeuto and Len Shustek for making me finish it. Ofcourse, special thanks go to Intel for bringing us theMCS-48.Some of this material was prepared while I was a

lecturer at the Digital Systems Laboratory at Stan-ford University. Other material is adapted from mytextbooks, Microcomputers, VoL 1: Architecture andProgramming and Microcomputers, VoL 2: SystemHardware Design, to be published by John Wiley &Sons in late 1979. All opinions expressed in this arti-cle are my own.

References

1. Intel Corporation. MCS-48 Family ofSingle Chip Micro-computers User's Manual, Santa Clara, Calif., July1978.

2. L. J. Shustek, "Analysis and Performance ofComputerInstruction Sets," PhD dissertation, Stanford Univer-sity, Jan. 1978, available from University Microfilms,Ann Arbor, Mich.

3. J. F. Wakerly, "Microcomputer Input/Output Architec-ture," Computer, Vol. 11, No. 2, Feb. 1977, pp. 26-33.

4. T. J. Chaney, S. M. Ornstein, and W. M. Littlefield, "Be-ware the Synchronizer," presented at COMPCON-72,IEEE Comput. Soc. Conf., San Francisco, Calif., Sept.12-14, 1972.

5. T. J. Chaney and C. E. Molnar, "Anomalous Behavior ofSynchronizer and Arbiter Circuits," IEEE-TC (Cor-resp.), Vol. C-22, No. 4, Apr. 1973, pp. 421-422.

6. M. Pechoucek, "Anomalous Response Times of InputSynchronizers," IEEE-TC, Vol. C-25, No. 2, Feb. 1976,pp. 133-139.

John F. Wakerly is an independent con-sultant and a lecturer at Stanford Uni-versity, wherefrom 1974to 1976hewasan assistant professor of electricalengineering. He has published many

fItiES_7 technical articles in the areas of com-

puter reliability, microprocessors, anddigital systems education, and is theauthor of two textbooks, Logic DesignProjects Using Standard Integrated

Circuits (Wiley, 1976) and Error-Detecting Codes, Self-Checking Circuits, and Applications (Elsevier North-Holland, 1978).Wakerly received the BEE degree from Marquette

University in 1970 and the MSEE and PhD from StanfordUniversity in 1971 and 1973, respectively. He was a HertzFoundation Fellow during his studies at Stanford. He is amember of the IEEE Computer Society, ACM, Sigma Xi,Tau Beta Pi, and Eta Kappa Nu.

February 1979

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ExceptionalOpportunities

in*SYSTEMS CONCEPTSmSYSTEMS DESIGN*IMPLEMENTATIONand CHECKOUT

Computer Sciences Corporation, with over10,000 employees, is the leader in the Informa-tion Sciences Industry. Letthe leaderintroduceyou to truly challenging assignments in yourspecialities. Work with some of thefinest mindsin your field.The System Sciences Division has many chal-lenging career opportunities for personnel atthe senior and intermediate level in:Computer Performance EvaluationNetwork Modeling/Simulation

Hardware/ Software Tradeoff EvaluationDistributive Processing

Microprocessor Configuration DesignComputer to Computer Communications

Software EngineeringOperational Analysis and Support

Command Control and Communications

Join a corporation that has steadily grown insize and ability to solve complex informationsciences problems.CSC offers competitive salaries and acomplete benefits package, including aliberal relocation policy. For immediateconsideration, please send resumes

or call:

STAFFING DEPARTMENT 3402-CMCollect: (3013589-1545 orToll Free: 800-638-0842

COMPUTER ;51kw SphIfi, MD 20910SCIENCES u.a,oWmO.*AndFOdhIN..Tlhou t The Wodd

_CORPORATION An Eqo.. Opporlunity Employ.oM,F