meljun cortes sequential logic

8/8/2019 MELJUN CORTES Sequential Logic

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physically implemented by the sequentialcircuit

SequentialLogic

Sequential Circuit

a type of circuit whose output depends not onlyon its inputs’ present state, but also its previousinputs

made up of not only of the basic combinational

circuits but also of storage elements

classified according to the timing of its signals

Block Diagram of the Sequential Circuit

Sequential Logic * Property of STI Page 1 of 63

Source: Mano, “Digital Design”


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observes its inputs and internal states only atcertain, discrete points in time

SynchronousSequential Logic

Asynchronous Sequential Circuit

observes the behavior of its inputs at anyinstance of time, as well as the order in whichthese inputs change in continuous time

Block diagrams of Synchronous SequentialCircuit


Source: M. Mano, ”Logic and Computer Design Fundamentals”, 2nd ed updated


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has to be synchronized by making it follow atiming device called the clock generator or

SynchronousSequential Logic

simply, the clock

Clock

produces a periodic train of clock pulses fromwhich the required changes in the storagedevices are timed

Clock Pulses

are timed pulses of high and low-logic levelelectric signals



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the basic storage element from which flip-flopsare usually constructed

Latches

as long as there is electricity powering thiscircuit, it holds and maintains the binary state

fed to it

asynchronous in nature

they do not need to be clocked to functionproperly

digital circuit that has two outputs that shouldalways be at opposite states

digital circuits that have two outputs (commonlynamed as Q’ and Q ) that should always be ato osite states


Types of Latches:

the SR (and S’R’ )

D latches


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also called an RS latch

Crossed-NORSR Latch

The SR Latch from Two Cross-Coupled NORGates

short for SET-RESET


its present state triggering of its SET or RESET input line

the two NOR gates used in implementing thelatch are defined by the following equations:

NOR gate A

NOR gate B


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Crossed-NORSR Latch

S = 1 and R =0:

NOR gate A the set state

by Boolean simplification, this becomes:


NOR gate B an unchanged state


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Crossed-NORSR Latch

resetting the output Q to 0


an unused or undefined state


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Crossed-NORSR Latch

another unchanged state of the SR latch

Function Table for SR Latch:



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the S’R’ or SET’ RESET’ latch

ver much like the SR latch exce t that this is

Cross-NANDS’R’ Latch

active low the SET’ input must be at logic 0 to set the output

Q to logic 1

The S’R’ Latch and its implementation using

NAND Gates



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setting the Q output for the cross-NAND S’R’ latch


resetting


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unchanged statewhen outputs are set

unchanged state whenoutputs are reset


unused state whenboth inputs are logic 0


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Function Table for SR Latch:


Comparison of theSR and S’R’ Latches


their inputs are complements of each other inproducing the same output

different in the values of the outputs during anunused state

crossed-NAND inputs: active low

cross-NOR inputs: active high


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The GatedSR Latches

symbol of the Gated SR Latch


circuit construction of the Gated SR Latch


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The GatedSR Latches

setting the output Qwith CLK enabled

output Q is not reseteven with S=0 and R =1because CLK is inhibited

Function Table for Gated SR Latch:



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an improvement over the clocked-SR (or gated-SR) latch in the sense that it prevents the

TransparentD Latch

problem when both the inputs are logic 1 has only two inputs: the input D and the CLK

enable

The D latch symbol and construction using NANDGates



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TransparentD Latch

CLK is enabled and the input D sets the output Q tologic 1


CLK is enabled and the input D sets the output Q tologic 0s


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TransparentD Latch


CLK is inhibited and the output Q is not changed


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Function Table for the D Latch with 1Control:

TransparentD Latch

derives its name form its ability to hold data it is called transparent because the information

at the data line is transparent and can be seen

directly from the output as long as the CLK isenabled


D latch with 0 control symbol and construction

using NOR gates


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Function Table for the D Latch with 0Control:

TransparentD Latch



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Examples


the timing diagram of a D latch


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Examples

How the Timing Diagram of a D Latch works:

Part 1:

Since the CLK is at logic 1 (HIGH), the value ofD is LOW; D should just be transferred to theout ut Q . The out ut of Q’ should ust be the


opposite of the Q value for all cases.

Part 2:

There is a transition of logic level of the D inputfrom LOW to HIGH. However, the CLK is still atHIGH. This means that there should also be atransition of the Q output from LOW to HIGH.


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How the Timing Diagram of a D Latch works (cont.):

Examples

Part 3:

There is a transition of the CLK input to LOW.This means that any other change in the input D will not affect the output. The output Q and Q are therefore maintained at their respectivevalues.

Part 4:

Although D goes down to LOW, the output isstill latched to HIGH since CLK is still LOW.


Part 5: The value of D goes up to HIGH but the CLK is

still LOW. The outputs are not affected by theinput’s transition and they remain the same.


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Given the timing diagram below, determine theoutput waveform for an SR latch.

Example 1

Solution:



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Solution (cont.):

Example 1


the timing diagram corresponds to the high and lowlogic levels of the SR latch’s function table


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Draw the waveform of the outputs for a gatedSR latch given the inputs below.

Example 2

Solution:



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Solution (cont.):

Example 2


The gated SR latch can only function if the CLKinput is HIGH. When the CLK is LOW, theoutputs will not change whatever the value of

the S and R inputs are (hence the don’t caresymbol in then function table). Therefore, weneed only consider the instances when the CLK

is at logic 1.


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the basic element for storing binary informationin synchronous sequential circuits

Flip-Flop

made up of latch circuitry

D latch is triggered as long as the clock is enabled

Block diagram of the sequential circuit using a latchas stora e



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eliminates the problem associated with thepropagation of the state of the input of simple

Master-SlaveFlip-Flops

latches for storing information two SR latches may be combined to form a

master-slave configuration

Master-Slave SR Flip-Flops



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Second Latch

ives the final out ut of the fli -flo


1. When the CLK is triggered, the master stage isactivated and is immediately affected by theinputs S and R . The values of the S and R arestored in the master SR latch.

2. When the CLK is driven to logic 0, the output of

the inverter is logic 1 and the slave stage istriggered.

3. Since the slave and master are connected whilethe slave is triggered, the outputs Q and Q’ aresim l the values of the A and A’ master


outputs.

4. When CLK is again triggered, the master isenabled while the slave is inhibited.


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Timing Diagram of the SR Master-Slave

Fli -Flo s with Time Dela s




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made to avoid the unreliable operation that ispossible for ordinary SR master-slave flip-flops

The JK Flip-Flop

when the J and K inputs of the flip-flop are bothlogic 1, the outputs are simply complemented

The JK flip-flop symbol and master-slaveimplementation



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When both inputs of JK and the SR master- slave flip-flops are 1, three things happen:

The JK Flip-Flop

1. When the flip-flop is presently operatingnormally, the outputs are complemented. Forexample, Q = 1 while Q’ = 0.



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2. When the CLK is triggered, the master SR latchis either SET or RESET since its inputs are

The JK Flip-Flop

guaranteed to be complementary and the exactopposite the flip-flop’s output values.



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3. After the CLK pulse stops triggering, the slavewill now get the value from the master’s outputs.

The JK Flip-Flop



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Function Table for the JK Flip-Flop:

The JK Flip-Flop

Master-slave flip-flops are sometimes called pulse- triggered flip-flops :

the master latch continues to get the inputs until


t e s n te


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Consider the following illustration of a JK flip-flop’s

slave SR latch:

The JK Flip-Flop

1. When the present state of Q n is logic 0 (and Q n ’ logic 1), and given the following instance fromits timing diagram:



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2. Consider the case when the input to the S lineis delayed internally in the latch. An immediate

The JK Flip-Flop

observation is that the output n +1 is in error.



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The pulse-triggered flip-flop is susceptible to two

problems:

The JK Flip-Flop

1. as long as the CLK is triggered HIGH(intentional or not), the inputs are processedand recognized by the outputs

2. long delays will cause the S and R lines of thelatches inside the flip-flop to change during a

clock pulse



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are employed when time delays and unreliableoscillations are present in a sequential circuit

Edge-TriggeredFlip-Flops

triggers only during the transition of the CLKsignal and ignores the pulse when it is at aconstant level (whether it is HIGH or LOW)

Two Types:

1. Positive edge or leadingedge or rising edge

triggering occurs during theLOW-to-HIGH transition


2. Negative edge or trailingedge or falling edge triggering occurs during the

HIGH-to-LOW transition


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D-type trailing edge-triggered flip-flop

an exam le of a ne ative ed e-tri ered fli -


flop implementation constructed by using a D latch, a gated SR

latch, and connected using an inverter

Trailing Edge D-Type Flip-Flop Implementation



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1. When the clock is at logic 1, the master D latchis turned on and the output at A will follow the


value of the input D .



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2. When the negative transition from logic 1 tologic 0 takes place, the master D latch is turned


off but the slave transfers the value from itsinputs to the output.



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Function table for the trailing edge D-typeflip-flop:




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Leading Edge D-Type Flip-Flop Implementation


Function Table for the Leading Edge D-Type

Flip-Flop:



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Symbols for Latches and Flip-Flops

A Summary of the

Different Flip-Flops



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A Summary of the




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A Summary of the




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T flip-flop

it to les the out ut when it is activated

A Summary of the


whenever its input becomes logic 0, the outputis toggled or complemented

T Flip-Flop from a JK Flip-Flop



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Function Table for the SR Flip-Flop:

Flip-FlopFunction Tables

Function Table for the JK Flip-Flop:



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Function Table for the D Flip-Flop:

Flip-FlopFunction Tables

Function Table for the T Flip-Flop:



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A Sequential Circuit

CircuitAnalysis

Input Equations

Y = (BC)’

D x = (AB )’+ (BC )’ + X’



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State Table



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4 steps to come up with the state table:

State Table

1. List all possible combinations of the presentstates and inputs in order. The present state isthe output of the flip-flops.

2. If there are outputs coming directly from logicgates present, write down their outputequations. Continue with step 2, making

another column for each flip-flop used.3. If there are outputs coming directly from logic

gates present, write down their outputequations.

4. Get the res ective values of the next state from


the input and present state combinations. We

will use the flip-flop characteristics we havediscussed to evaluate the next state of the flip-flop.


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Derive the state table given the logic diagrambelow:

Example 3



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Solution:

In ut E uations

Example 3

JK flip-flop: J x = AX + (AB)’

K x = (BZ)’

D flip-flop: D y = (BZ)’

NAND-gate: Z = (AB)’

State Table for Example 3:



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an alternative way to represent the states in asequential circuit

State Diagram

more intuitive for human interpretation represented by circles - the more flip-flops there

are for a certain circuit, the more circles areneeded

State Diagram from the State Table for Example 3



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Derive the state table given the logic diagrambelow:

Example 4

Solution:


D flip-flop: D x = (AY + AX’)’ NAND-gate: Y = AX’


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Write down the state table by enumerating thepresent state and input

Example 4

Evaluate the value of the output Y from theAND-gate equation



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The next state Xn+1 results from following theinput equation for the D-type flip-flop

Example 4

The state diagram is directly derived from theabove state table



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State Equation

ma be directl derived from the state table of a

Design and Synthesis

of Sequential Circuits

sequential circuit consists of simple Boolean expressions for the

output combinational circuit using the sum ofminterms, with the left-hand side of the equationcontaining the output variable

State Table for Example 4:



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State Equations:

Z A X Y = S 1 2 4 6



D X (A,X,Y ) = S(2,5,6)

D Y (A,X,Y ) = S(0,2,3,4,6)

K-Map Simplification for the State Equations



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K-Map Simplification for the State Equations





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The simplified state equations are therefore:

Z = A’ •X’ •Y + XY’ + A•Y’ = A’X’Y + A+X Y’



D X = AY + A’XY’

D Y = Y’ + A’X

Logic Diagram of the Sequential Circuit

meljun cortes sequential logic

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