microelectronic circuits by meiling chen 1 lecture 13 mosfet differential amplifiers

Microelectronic circuits by Meiling CHEN

1

Lecture 13Lecture 13MOSFET Differential MOSFET Differential

Amplifiers Amplifiers


2

topicstopics• Ideal characteristics of differential amplifier

– Input differential resistance– Input common-mode resistance– Differential voltage gain– CMRR

• Non-ideal characteristics of differential amplifier– Input offset voltage – Input biasing and offset current

• Differential Amplifier with active load• Frequency response


3

Figure 7.1 The basic MOS differential-pair configuration.

MOS differential pair


4

CSV

Figure 7.2 The MOS differential pair with a common-mode input voltage vCM.

Common mode operation

DDDDDD

tGSnD

GSCMs

DD

RIVvv

VVL

Wk

II

Vvv

III

QQ

21

2'

21

21

)(2

1

2

2

Q1 and Q2 in saturation mode

)(2

(min)

(max)

tGStCSssCM

DDDtCM

VVVVVv

RI

VVv

BJT’s differential pair VCM no bound

Make sure current source is working

tsCMSDDDD

tGSDS

VvvvRIV

Vvv

)(

GSSSCSCM

tSSCSCM

tsCMtGS

vVVv

VVVv

VvvVv

)(


5

Exercise 7.1 kRmAIVVVmAL

WkVVV DtnSSDD 5.2,4.0,5.0,/4,5.1 2'

5.0816.0

15.22.05.1

816.0

)5.0(22.02

)(2

1

2

2'

tGSDS

DS

GS

GS

tGSnD

VVV

VkmV

VV

VmI

VVL

WkI

Saturation mode

5.011

1

D

tCMDtGD

tSGSD

tGSDS

CM

V

VVVVVV

VVVVV

VVV

VV

Saturation modeVVCM 5.1(max)


6

Figure 7.3 (Continued)

48.0

VV

V

CM

CS

2.05.148.082.0

48.0

(min)

(min)


7

Figure 7.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid vG1 – vG2.

Large signal operation

22

'2

21

'1

)(2

1

)(2

1

tGSnD

tGSnD

VvL

Wki

VvL

Wki

2121 GGGSGSid vvvvv

2

'

'1

2

'

'1

2'2!

21

'21

21

2/1

22

1

2

21

2/1

22

1

2

2

12

2

1

LW

k

vvI

L

Wk

Ii

LW

k

vvI

L

Wk

Ii

vL

WkIii

Iii

vL

Wkii

n

ididnD

n

ididnD

idnDD

DD

idnDD


8

Figure 7.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2.


9

Figure 7.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.

2

'

'1

21

2/1

22

1

2

LW

k

vvI

L

Wk

Ii

n

ididnD

More k is bigger more linear range of vid


10

Figure 7.8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small-signal operation of the circuit.

7-2.1 Small signal operation (differential gain)

idCMG

idCMG

vvv

vvv

2

12

1

2

1

21

21

2vvv

vvv

id

CM


11

)//(

)//(2

1),//(

2

1

)//(2

)//(2

12

22

11

22

11

oDmid

ood

oDmid

ooDm

id

o

oDid

mo

oDid

mo

rRgv

vvA

rRgv

vrRg

v

v

rRv

gv

rRv

gv

DR

gsv gsmvgor

1ov

2idv

Doo

id

RrR

R

//21


12

ro effects

idoDmooo

idoDmo

idoDmo

vrRgvvv

vrRgv

vrRgv

)//(

)2/)(//(

)2/)(//(

12

2

1


13

2id

m

Vg

1oV

gsV

2idV

2idV

gsV

2

idm

Vg

1or DR DR 2or

2oV

Differential-mode equivalent circuit

)//(

)//(

)2/)(//(

)2/)(//(

12

12

2

1

oDmid

ood

idoDmooo

idoDmo

idoDmo

rRgv

vvA

vrRgvvv

vrRgv

vrRgv


14

Common-mode gain et CMRR

SS

D

icm

o

icm

omSS

SSm

D

icm

o

icm

o

R

R

v

v

v

vgR

Rg

R

v

v

v

v

2/1

2/1

11

21

ssmcm

d

DmdssDcm

RgA

ACMRR

RgARRA

2

1,2/

21

21

(1) Half circuit of differential pair

(2) Full circuit

cm

d

Dmidoodicmoocm

A

ACMRR

RgvvvAvvvA /)(,0/)( 1212

mg

1 DR

1ov

ssR2

di

icmR2

icmv

di


15

SSV

DDV DDV

fIRe

1DI

2DI

R

VVVI

IIIvv

VvL

WkI

GSSSDDD

refDDGSGS

tGSnD

1

2121

2' )(2

1

SSoo RrR

gsvgsmvg

or

1ov

R

gsvgsmvg

or


16

Non zero common gain due to RD mismatch

D

Dssm

cm

d

Dmd

D

D

ss

D

ss

Dcm

icmss

Doo

icmss

DDo

icmss

Do

DD

R

RRg

A

ACMRR

RgA

R

R

R

R

R

RA

vR

Rvv

vR

RRv

vR

Rv

RRconsider

/2

22

2

2

2

12

2

1

21

mg

1 DR

1ov

ssR2

di

icmR2

icmv

di

SS

D

icm

o

icm

omSS

SSm

D

icm

o

icm

o

R

R

v

v

v

vgR

Rg

R

v

v

v

v

2/1

2/1

11

11


17

Figure 7.11 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the gm values of Q1 and Q2.

Non zero common gain due to gm mismatch

21

21

22

21

11

21

2121

2

1

2

121

21

)(

)(

)(

)()(

mmm

ssmm

icmmd

ssmm

icmmd

ss

icmddicms

ss

sddssdds

m

m

d

dgsgs

mm

ggglet

Rgg

vgi

Rgg

vgi

R

viivv

R

viiRiiv

g

g

i

ivv

ggconsider

)(

)(2

2

tgsox

m

tgsox

d

VvL

WCg

VvL

WCi


18

m

mssm

cm

d

Dmd

m

m

ss

Dcm

ssm

icmDmDdDdoo

ssm

icmmd

ssm

icmmd

g

gRg

A

ACMRR

RgA

g

g

R

RA

Rg

vRgRiRivv

Rg

vgi

Rg

vgi

/2

2

2

2

2

1212

22

11


19

Figure 7.25 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the terminals with opposite polarity reduces VO to zero.

Input offset voltage

2121

21

21

.3

.2

.1

2

2

1

1

tt

LW

LW

DD

VVQQ

QQ

RR


20))(

2(

))(2

)((

)(

)(

2

2

)2

(2

)2

(2

2

2

22

12

2

1

2

1

21

D

DOVos

D

DtGS

D

D

tGSLWC

tGSLWC

Dm

D

Dm

O

d

Oos

DDDO

DDDDD

DDDDD

DDD

DDD

DD

R

RVV

R

RVV

R

R

VV

VV

Rg

RI

Rg

V

A

VV

RI

VVV

RR

IVV

RR

IVV

RRR

RRR

RRconsider

ox

ox

))/(

)/()(

2(

)/(2

)/(

2

)/(

)/(

22

)/(

)/(

22

)(2

1)(

)(2

1)(

2

1

2

1

21

LW

LWVV

LW

LWII

LW

LWIII

LW

LWIII

L

W

L

W

L

WL

W

L

W

L

W

QQconsider

OVos

oVV


21tos

OV

t

tGS

t

tGSn

tGS

ttGSn

tGS

ttGSn

tGS

ttGSn

ttGSn

ttt

ttt

tt

VV

V

VI

VV

VII

IVV

L

Wk

VV

VVV

L

WkI

VV

VVV

L

WkI

VV

VVV

L

Wk

VVV

L

WkI

VVV

VVV

VVconsider

2

2

2

2

2)(

2

1

)1()(2

1

)1()(2

1

])(2

1[)(2

1)

2(

2

12

2

2'

2'12

2'1

22'2'1

2

1

21

222 )())/(

)/(

2()

2( t

OV

D

DOVos V

LW

LWV

R

RVV


22

Differential amplifier with active load

1. Differential gain 2. Common-mode gain et CMRR

Active load


23


24

Differential-mode equivalent circuit with active load

2idV

2id

m

Vg 1or

mo gr

1//3

4gsmVg 4or 2or

oV

)2

( idm

Vg

2idV

2idV

2id

m

Vg 1or

mo gr

1//3

4gsmVg 4or 2or

oV

)2

( idm

Vg

2idV

1Q 4Q 2Q

3Q

42 // ooo rrR

om

d

ooo

oomid

oovv

m

id

od

v

m

vm

moo

vmgs

oogsv

mo

rg

A

rrrwhen

rrgv

rrg

v

vA

gg

grrgv

rrvgv

idid

ididid

id

2

)//()//)((

1)

1////(

)//)((

42

424222

223124

4242

)//( oDmd rRgA Passive load

active load

SSoo RrR Passive load

active load


25

Common-mode equivalent circuit with active load

iCMViCMV

di

di

mg

11or

mo gr

1//3

4gsVoV

4gsmVg

ssR2 1i

2i

4or 2or

di

mg

1

ssR22i

)( oss rR

iCMViCMViCMViCMV

di

di

mg

11or

mo gr

1//3

4gsVoV

4gsmVg

ssR2 1i

2i

4or 2or

di

mg

1

ssR22i

)( oss rR

1i

SSicm

SSicm

mogs

gsmoo

Riv

Riv

griv

ivgrv

2

2

)1

//(

)(

2

1

414

244

moSS

o

icm

ocm

SS

icm

mo

SS

icmmoo

mo

SS

icmgs

SS

icmgsmoo

grR

r

v

vA

R

v

gr

R

vgrv

gr

R

vv

R

vvgrv

3

4

34

34

44

1

1

2

]2

)1

//(2

[

)1

//(2

)2

(


26

Figure 7.29 Determining the short-circuit transconductance Gm ; io/vid of the active-loaded MOS differential pair.

1. Find the transconductance Gm


27

mm

idmo

mmmmm

idm

id

m

mmo

idmgmo

id

m

mg

moo

oom

idmg

gG

vgi

ggggg

vg

v

g

ggi

vgvgi

v

g

gv

grr

rrg

vgv

2143

23

41

234

3

13

331

133

13

,

)2

()2

)((

)2

(

)2

(

)/1(,

)////1

)(2

(


28

2. Find the output resistance Ro

3. Find the differential gain

42

4244

22

22

12222

2

//

22

2

1

)/1)(1(

/

oox

xo

o

x

o

x

o

x

o

xx

oo

om

momoo

ox

rri

vR

r

v

R

v

r

vi

r

viii

rR

rg

grgrR

Rvi

om

d

ooo

oomomid

od

rg

A

rrrwhen

rrgRGv

vA

2

)//(

42

42


29

Figure 7.31 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.

Common-mode gain et CMRR


30ssmom

mmooo

ssmoomcm

d

ssmcm

ooom

om

o

ssicm

ocm

oom

moo

om

mgm

om

g

ssomssooo

ss

icm

RgrgCMRR

ggrrrlet

RgrrgA

ACMRR

RgA

rrrg

rg

r

Rv

vA

rirg

igriiv

rg

igvgi

rg

iv

RrgRrRR

R

vii

342

342

3

4333

33

4

4233

14424

33

14344

33

13

21

21

,

]2)][//([

2

1

,1

12

1

])//1

([)(

)//1

(

)//1

(

22

2

microelectronic circuits by meiling chen 1 lecture 13 mosfet differential amplifiers

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