CNU EE 6.1-1

Microelectronic Circuits II

Ch 6 : Building Blocks of Integrated-Circuit

Amplifier

6.3 The Cascode Amplifier

CNU EE 6.1-2

Cascode AmplifierCascodingUse of a common gate transistor to provide current buffering for the output of a common-sourceamplifying transistorMOS cascode- Q1 : CS configuration à amplifying transistor- Q2 : CG configuration with a dc bias voltage VG2 (signal ground) at its gate à cascode transistor- Cascode transistor passes the current gm1vi to the output node while raising the resistance level by a

factor of K- What is K ?

Q2 : cascode transistorQ1 : amplifying transistor

CNU EE 6.1-3

(a) MOS cascode amplifier w/o a load circuit & w/ the gate of Q2 connected to signal ground(b) Output equivalent circuit of the cascodeamplifier à parameter Gm & Ro(c) short-circuit transconductance Gm by short-circuiting (from a signal point of view) the output of the cascode amplifier d2 to ground

i

om v

iG =

The MOS Cascode

CNU EE 6.1-4

(d) By replacing Q1 & Q2 with their small-signal models à Determine io in terms of vi- Voltage at (d1, s2) node = -vgs2à node equation at (d1, s2)

imgsmoom

imgsoo

m

imo

gs

o

gsgsm

vgvgrrgSince

vgvrr

g

vgrv

rv

vg

122212

1221

2

12

2

1

222

1,1

11

»>>

=÷÷ø

öççè

æ++

=++

The MOS Cascode : Gm

- Current of the controlled source of Q2 = current of the controlled source of Q1- Node equation at d2 :

- From

2222

22

222

1gsmogs

om

o

gsgsmo vgiv

rg

rv

vgi »÷÷ø

öççè

æ+=+= >

11 mi

omimo g

viGvgi === >

imgsm vgvg 122 »

à 6.1-17

CNU EE 6.1-5

- Ro determination : vi = 0 à Q1 = ro1 at (a), Q2 à hybrid-p model & test voltage vx at (b)

- Since the source current of Q2 = ix & voltage at s2 = -vgs2 à- vx = sum of the voltages across ro2 & ro1 à

- Ro :

- CG transistor Q2 raises the Ro of the amplifier by the factor (gm2ro2), which is intrinsic gain Ao2.- CG transistor simply passes the current (gm1vi) to the output node

à CG or cascode transistor is the current buffer with K = A02 = gm2ro2

( ) ( ) fromrrgrrivrirvgiv oomooxxoxogsmxx 122211222 ++=+-= >

The MOS Cascode : Ro

12 oxgs riv =-

( ) 12212221 oomooomooo rrgRrrgrrR »++= >

x

xo i

vR =

12 oxgs riv =-

CNU EE 6.1-6

§ Voltage gain(a) Cascode amplifier loaded w/ an ideal constant current source(b) equivalent circuit to find voltage gain

- For the case gm1=gm2=gm & ro1=ro2=ro,

- Cascoding increases the gain magnitude from Ao to Ao2

( )( )22111 omomomi

ovo rgrgRg

vvA -=-==

The MOS Cascode : Voltage gain

( ) 22oomvo ArgA -=-=

CNU EE 6.1-7

§ Cascode current source- Q4 : current-source transistor, Q3 : CG cascode transistor - VG3 & VG4 : dc bias voltage - Q3 multiplies output resistance of Q4, ro4 by (gm3ro3)

( ) 433 oomo rrgR =

( ) 22

21

21

oomv ArgA -=-=

The MOS Cascode

Cascode amplifier + cascode current-source à increase in the magnitude of gain by a factor of Ao

§ Cascode amplifier + cascode current-source- Voltage gain

- If all transistors are identical,

[ ] ( )[ ] ( )[ ]{ }43312211 |||| oomoommoponmi

ov rrgrrggRRg

vvA -=-==

CNU EE 6.1-8

Distribution of Voltage gain in a Cascode Amplifier§ Voltage gains of the CS stage Q1 & the CG stage Q2(a) Cascode amplifier with a load resistance RL (=Ro of current-source load + additional resistance )

- Overall voltage gain :

- (b) Av1=vo1/vi : find the total resistance between d1 (D of Q1) & ground à Rd1

- Rd1 = parallel equivalent of ro1 and Rin2 à Rin2 : input resistance of the CG transistor Q2- (c) equivalent circuit of Q2 with its load resistance RL

( )2 2 1o m o oR g r r@

( ) ( ) ÷÷ø

öççè

æ÷÷ø

öççè

æ==-=-=

1

212112211 ||||

o

o

i

ovvLoommLomv v

vvvAARrrggRRgA

111

1 dmi

ov Rg

vvA -==

CNU EE 6.1-9

Distribution of Voltage gain in a Cascode Amplifier(c) equivalent circuit of Q2 with its load resistance RL- Since the voltage at the source of Q2 = -vgs2,

i : current flowing into the source of Q2

- Source voltage, -vgs2=sum of he voltage drop across ro2and RL :

- Since gm2ro2 >> 1,

- If ro2 is infinite, Rin2 à 1/gm2- If ro2 cannot be neglected, general case of IC amplifiers, RL is divided by (gm2ro2) à “flip side” of the impedance transformation of the CG.- Av1 of Q1 :

- Av2 of Q2 is obtained by dividing the total gain Av by Av1

( )22

2222222 1 om

oLgsinLogsmgs rg

rRiv

RiRrvgiv++

=-

º++=- >

iv

R gsin

22

-=

2222

1

mom

Lin grg

RR +»

( )211111211 |||| inomdmvinod RrgRgARrR -=-== >

CNU EE 6.1-10

Distribution of Voltage gain in a Cascode Amplifier

Table 6.2 Gain distribution in the MOS Cascode Amplifier for Various Values of RL(ro1 = ro2 = r & different RL)

1

2

3

4

LR 2inR 1dR 1vA 2vA vACase¥ ¥ 0r 0rgm- 0rgm

20 )( rgm-

20 )(

21 rgm-0rgm)(

21

0rgm-00 )( rrgm 0r 2/0r

0rmg

2mg

2 )(21

0rgm )( 0rgm-

mg10 1- 0 0

2-

mg1

RL = infinity à ideal current-source loadRL = (gmro)ro à cascode current-source loadRL = ro àsimple current source loadRL = 0 à signal short circuit at the ground

CNU EE 6.1-11

Output resistance of Source-Degenerated CS Amplifier

- CS amplifier with a source resistance Rs, source-degeneration resistanceà Rs reduces the effective transconductance to gm/(1+gmRs), by a factor of (1+gmRs)à The factor (1+gmRs) increases linearity & bandwidth.

- Ro determination : vi = 0 à transistor Q appears as a CG transistor.

- Source degeneration increases the output resistance of the CS amplifier from ro to (1+gmRs) ro, by the same factor (1+gmRs)- Rs introduces negative (degenerative) feedback of an amount (1+gmRs)

( ) 1sin1 >>+»++= omosmosomoso rgcerRgRRrgrRR

CNU EE 6.1-12

Double Cascoding

§ Double-cascode amplifier- Higher output resistance and gain à another level of cascoding

- Q1 : CS transistor à ro1- Q2 : CG cascode transistor à (gm2ro2)ro1- Q3 : second CG cascode transistor

- raise output resistance by (gm3ro3) à (gmro)2ro w/ identical transistor

- voltage gain : (gmro)3 or Ao3

- Each transistor needs a certain minimum vDS(at least equal to VOV)

- Difficulty posed by stacking additional transistorsbecause VDD is only a little more than 1 V à there is a limit on the number of transistors in

a cascode stack

CNU EE 6.1-13

Folded cascodeWith folded cascode, the demerit of normal cascode can be removed. (very popular building block in CMOS Amp.)

§ Folded-cascode amplifier- NMOS Q1 : CS transistor, bias current (I1-I2)- PMOS Q2 : CG cascode transistor, additional

current-source I2- VG2 : Q1 & Q2 in saturation region- Small-signal operation is similar to that of the

NMOS cascode - signal current gmvi is folded down and made

to flow into S of Q2 à folded cascode

CNU EE 6.1-14

(a) BJT cascode amplifier w/o an ideal current –source load. VB2 is a dc bias voltage for the CBcascode transistor Q2. (b) Output equivalent circuit of the cascodeamplifier à parameter Gm & Ro(c) short-circuit transconductance Gm by short-circuiting (from a signal point of view) the output of the cascode amplifier c2 to ground

i

om v

iG =

The BJT Cascode

CNU EE 6.1-15

(d) By replacing Q1 & Q2 with their small-signal models à Determine io in terms of vi- Voltage at (c1, e2) node = -vp2à node equation at (c1, e2)

immoom

imoo

m

vgvgrrrgSince

vgrv

rv

rvvg

1222122

12

2

2

2

1

222

1,1,1 »>>

=+++

pp

p

pppp

The BJT Cascode : Gm

- Node equation at c2 :

- From

- identical to that for the MOS case

222

222 p

pp vgi

rvvgi mo

omo »+= >

11 mi

omimo g

viGvgi === >

imm vgvg 122 »p

à 6.1-17

CNU EE 6.1-16

- Ro determination : vi = 0 à Q1 = ro1 at (a), Q2 à hybrid-p model & test voltage vx at (b)

- Since the emitter current of Q2 = ix & ro1||rp2, voltage at e2 = -vp2 à- vx = sum of the voltages across ro2 & ro1 à

- Ro :

- Not identical to that for the MOS cascode- Because of the finite b of the BJT, rp2 appears in parallel with ro1

à significant constraint on Ro of the BJT cascode

( ) ( ) fromrrirvgiv oxomxx 21222 || pp +-=

The BJT Cascode : Ro

( )212 || pp rriv ox=-

( ) ( )( ) ( )( ) ( )( )21222212222122212 ||||1|||| pppp rrrgrrrrgrrrrgrrrR oomooomooomooo +»++=++=

x

xo i

vR =

( ) xxoox ivRrriv ==- &|| 212 pp

CNU EE 6.1-17

- Because (ro1|| rp2) is always lower than rp2, the maximum possible value of Ro is

à maximum Ro realizable by cascoding is b2ro2à Unlike the MOS case, double cascoding with a BJT would not be useful

§ Voltage gain- Open-circuit voltage gain of the bipolar cascode :

à Avo will be less than (gmro)2 in magnitudeà maximum possible gain magnitude when ro >> rp :

- BJT cascode amplifier with a cascode current-source load

( ) 22222222max oomomo rrrgrrgR bpp ===

The BJT Cascode : Ro , Voltage gain

( )( )

( ) ( )[ ] 2121

21221

,||

||

oommomom

oommomi

ovo

rrggforrrgrg

rrrggRGvvA

==-=

-=-==

p

p

oomvo ArgA bb ==max

CNU EE 6.1-18

Output resistance of Emitter-Degenerated CE Amplifier- CE amplifier with a emitter resistance Re, emitter-degeneration resistance- from , ro2 à ro, gm2 à gm, rp2 à rp & ro1 à Re

à Emitter degeneration multiplies the transistor output resistance ro by the factor [1+gm(Re|| rp)]

( ) ( )( ) ( )( )( )[ ] oem

omeomoeomeoo

rrRgrgcerRrgrrRrgrRrR

p

ppp

||11sin||||||

+=>>+»++=

( ) ( )( )2122212 |||| pp rrrgrrrR oomooo ++=

CNU EE 6.1-19

BiCMOS Cascode

§ BiCMOS cascode amplifier (a)- MOSFET : infinite input resistance

BJT : Larger output resistance(β of BJT > Ao of MOSFET & ro,BJT > ro,MOS)

- lower input resistance Rin2 à reducedMiller effect in Q1

§ BiCMOS cascode amplifier (b)- MOSFET : 2nd level of cascoding in

bipolar cascode amplifier- Maximum Rout of BJT = βro- Q3 raises output resistance by the

factor Ao3