PIPELINED ARCHITECTURE

Prof.P.C.PatilProf.P.C.PatilDepartment of Computer EnggMatoshri College of Engg.Nasik

pcpatil18@gmail.com.

MICROPROCESSOR ARCHITECTUREUOP S.E.COMP (SEM-I)

Bus Cycles of 80386

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The internal and external bus operations of 80386 are synchronized by the clock signal.

The 80386 perform variety of machine (bus) cycles in response to intemal requirements and external requirements

There are seven types of machine (bus) cycles In each machine cycles corresponding status signals

are activated. The memory read and memory write machine cycles

can be locked to prevent another bus master from using the bus.

Bus Cycles of 80386

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In each machine cycles corresponding status signals are activated.

The memory read and memory write machine cycles can be locked to prevent another bus master from using the bus.

Bus Cycles of 80386

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Seven types of machine (bus) cycles/operations.1) Memory read1) Memory read2) Memory write2) Memory write3) I/O read3) I/O read4) I/O write4) I/O write5) Lestruction fetch5) Lestruction fetch6) Interrupt acknowledge6) Interrupt acknowledge7) Halt/Shut down7) Halt/Shut down

Bus Cycles of 80386

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Bus Cycles of 80386

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System Clock

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System clock syrchronizes the internal and external bus operations in the 80386DX.

The 80386DX can operate on four different clock speeds

1.1. 80386DX 80386DX -- 16 (16 MHz)16 (16 MHz)2.2. 80386DX 80386DX -- 20 (20 MHz)20 (20 MHz)3.3. 80386DX 80386DX -- 25 (2s MHz) 25 (2s MHz) 4.4. 80386DX80386DX-- 33 (33 MHz)33 (33 MHz)

Operating frequency of the 80386DX is half of, the CLK2 frequency.

Therefore, CLK2 of an 80386DX - 20 is driven by 40 MHz signal. (Shown in Fig below)

System Clock

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System Clock

Bus States

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Each machine (bus) cycle consists of at least two bus states T1 and T2,

and each bus state consists of two CLK cycles. 1. During the first bus state (T1), address and bus status address and bus status

pin are active. 2. During the second bus state (T2), actual data lransferactual data lransfer

takes place. The 80386 DX can perform two types of machine

cycles : 1.1. Nonpipelined Nonpipelined 2.2. PipelinedPipelined.

Bus States

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Dynamic Bus Sizing

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Dynamic data bus sizing is a feature allowing direct processor connection to 32-bit or 16-bit data buses for memory or I/O.

A single processor may connect to both size buses Transfers to or from 32 to 16 bit ports are supported

by dynamically determining the bus width during each machine cycle.

The 80386DX microprocessor's bus size 16 (BS-16 [Bar/Complement])[Bar/Complement]) )) input is used to inform the 803B6DX at the currently addressed device is a 16-bit device rather than a 32-bit device‘

Dynamic Bus Sizing

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Nonpipelined Machine (Bus) Cycles

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Nonpipelined Bus Cycle

During T1, the 803B6DX sends the address, bus status signal and control signals.

In case of write cycle, data to be output is also send on the data bus, during T1.

After address access time, read or write data transfer takes place over the data bus.

This activity is carried out in T2.

Nonpipelined Bus Cycle

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Pipelined Machine (Bus) Cycles

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Pipelining allows machine cycles to be overlapped. The main advantage of pipelining is that it increases

the amount of time required for the memory or I/O device to respond.

This time is also referred as access time. The 80386DX implements pipelining by overlapping

addressing of the next bus cycle with the data transfer of previous bus cycle.

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Pipelined Bus Cycle

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Pipelined Bus Cycle

Fig shows that address becomes valid in T2 state of the previous bus cycle, and the data transfer for address takes place in T2-state of the current bus cycle.

IMP :IMP : address AAn + 1 n + 1 becomes valid during T2 of the current bus cycle and actual data transfer for address AAn + 1 n + 1 takes place in T2 state of the next bus cycle.

If the processor is 80386DX-20 then one T-state time is 50 ns.

In pipelined bus cycle the access time for memory and I/O In pipelined bus cycle the access time for memory and I/O device is 100 ns whereas access time for memory and l/O device is 100 ns whereas access time for memory and l/O device in nonpipelined bus cycle is approximately 50 ns.device in nonpipelined bus cycle is approximately 50 ns.

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Pipelined Bus Cycle

Nonpipelined ReadCycle

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Enlarge Image

The sequence of events for the nonpipelined read cycle: The sequence of events for the nonpipelined read cycle: 1. The read operation starts at the beginning of phase starts at the beginning of phase

in the T1 statein the T1 state of the bus cycle. 2. In this phase, 80386DX sends the address on the sends the address on the

address busaddress bus and enables signals(BE0enables signals(BE0 (Bar)(Bar) -- BE3BE3 (Bar)(Bar)) ) according to data transfer type.

3. In the same phase, it activates ADS it activates ADS (Bar)(Bar) signal to indicate valid address indicate valid address is placed on the address bus.

4. In phase 1phase 1 of T1 T1 -- state state it also activates the bus cycle definition signals : M/IO, D/C and W/RM/IO, D/C and W/R.

Nonpipelined Read Cycle

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5. At the beginning of phase 1 of T2 statebeginning of phase 1 of T2 state, extemal device activates BS16activates BS16 (BAR)(BAR) signal.

6. Then samples this signal in the middle of phase 1 of middle of phase 1 of T2T2--state. state. 32-bit data transfer: If BS16BS16 (BAR)(BAR) =1=1 16-bit data transfer: If BS16BS16 (BAR)(BAR) =0=0

7. The 80386 DX does this data transfer in phase 2 of phase 2 of T2T2--state.state.

8. At the end of phase 2 of T2end of phase 2 of T2--state state the READY READY (BAR(BAR))signal is sampled.

9. The logic 1logic 1 on this signal inserts wait state wait state in the current bus cycle to extend the bus cycle.

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Nonpipelined Read Cycle

10. The LOCK LOCK (Bar)(Bar) signal lowlow indicates that it is bus locked cycle.

11. If bus cycles are locked the other bus master is not allowed to take control of the bus between two locked bus cycles.

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Nonpipelined Read Cycle

Nonpipelined WriteCycle

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The sequence of events for the nonpipelined read cycle: The sequence of events for the nonpipelined read cycle: 1. It is similar to nonpipelined read cycle. 2. The write operation write operation starts at the beginning of phase beginning of phase

1 in the T1 state 1 in the T1 state of the bus cycle. 3. In this phase, 80386DX sends the address on the address on the

address busaddress bus and enables signals BE0BE0(Bar) (Bar) --BE3BE3(Bar(Bar) ) according to data transfer type.

4. After sending address in the same phase it activates its ADSADS(Bar)(Bar) signal to indicate valid address is placed on the address bus.

Nonpipelined Write Cycle

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10.10. In phase 1 of T1In phase 1 of T1--state state it also activates the bus cycle definition signals M/IO, D/C and W/RM/IO, D/C and W/R

11. At the beginning of phase 2 of T1beginning of phase 2 of T1--statestate, it sends data on the data bus. This data remains valid until the valid until the start of phase 2 of the T1start of phase 2 of the T1--state state of the next bus cycle.

12. At the end of phase 2 of T1end of phase 2 of T1-- state, ADSstate, ADS(Bar)(Bar) is returned to its inactive logic 1 inactive logic 1 states.

13.13. The address bus, byte enable pins, and bus status The address bus, byte enable pins, and bus status pins remain active through the end of the write cyclepins remain active through the end of the write cycle.

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Nonpipelined Write Cycle

10. In the middle of phase 1 of T2-State, 80386DX samples BS16(Bar)(Bar) input.

11. If this signal is high, 80386 DX does the 32-bit data transfer otherwise 80386DX performs 16-bit data transfer.

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Nonpipelined Write Cycle

Comparison of Read and Write Cycle

Pipelined Read/WriteCycle

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In the pipelined bus cycle the address for the next address for the next bus cycle is sent during the T2 bus cycle is sent during the T2 -- state state of the current cycle.

NA (next address) NA (next address) signal initiates address pipelining.

Pipelined Read/Write Cycle

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It then samples NA signal at the beginning of phase beginning of phase 2 of any T2 of any T state in which ADSADS is not active, specifically.

In the second Tsecond T--statestate of a non-pipelined address cycle In the first Tfirst T--state state of a pipelinedpipelined address cycle In any wait state any wait state of a nonnon--pipelinedpipelined address or pipelined

address cycle unless NA has already been sampled active

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Pipelined Read/Write Cycle

The NANA(Bar)(Bar) is tested as 0 (active) during T2 of cycle 2T2 of cycle 2which ensures that 80386DX has to execute next execute next cycle as pipelined cycle as pipelined bus cycle.

The cycle 2 (nonpipelined read cycle) is also extended with one wait state because READY pin is not active,

in wait statewait state, the valid address for the next bus cycle is sent on the address bus as next bus cycle is pipelined bus cycle.

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Pipelined Read/Write Cycle

The next cycle (cycle 3) next cycle (cycle 3) is pipelined write pipelined write cycle. In this, data is sent on the data bus in phase 2 of phase 2 of

T1pT1p--statestate and remains valid for the rest of the cycle. The READY signal is sampled at the end of T2p -

state. As it is low,low, write cycle is completed without wait

state.

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Pipelined Read/Write Cycle

The next cycle (cycle 4) next cycle (cycle 4) is pipelined read cyclepipelined read cycle. . In this, READY signal is tested 0 at the end of phase

2 of T2p - state. This means that read cycle is completed without

wait state. It is important to note that due to pipelined address due to pipelined address

cycle, access time is extended and one state (Tcycle, access time is extended and one state (T--wait) wait) of read cycle is saved.of read cycle is saved.

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Pipelined Read/Write Cycle