CSE 466-02au-

Microprocessor Development Tools

CSE466 - Fall 2002- 2

Tool Types

Software Tools

! Assembler! Linker! Loader! Compiler! Libraries! Pre-compiled IP! Simulator! IDE

CSE466 - Fall 2002- 3

Hardware Tools

In Circuit Emulator (ICE)Logic AnalyzerMicroprocessor Development SystemsSystem Development Systems

CSE466 - Fall 2002- 4

Atmel AVR Architecture

CSE466 - Fall 2002- 5

ATmega16

CSE466 - Fall 2002- 6

AVR CPU

CSE466 - Fall 2002- 7

Simple Princeton Architecture

ALUROMLinear

AddressSpace

W/ MemMapped

IO

PC SPGPRsIR

mux

Control

IR

I/O PortTimer, SFR’s

Status

Reset VectorInterrupt Vect

RAM address

data

CSE466 - Fall 2002- 8

Analysis

Bottleneck into and out of memory for data and code

Use of critical 8-bit address space (256) for memory mapped I/O and special function registers (timers and their controllers, interrupt controllers, serial port buffers, stack pointers, PC, etc). For example, the Motorola 6805 processor has only 187 RAM locations.

But, easy to program and debug. Compiler is simple too.

CSE466 - Fall 2002- 9

8051: Modified Harvard Architecture

ALU

PC

Internals

Control

Status

Reset VectorInterrupt VectInterrupt VectInterrupt Vect

RAM

SFR’s(direct)

UsuallyStack

(indirect)

Bit Addressable

Reg. Banks

addressmux

data

(indirect orDirect)

8051 standard +Enhancements

PSW – 2-bits bank sel.

4x8instruction 3 bits reg sel

------------------5 bits of reg. addr

CSE466 - Fall 2002- 10

8051 Memory Architecture

Advantages! Simultaneous access to Program and Data store! Register banks great for avoiding context switching on

interrupt and for code compression! 8-bit address space extended to 256+128 = 384 registers by

distinguishing between direct and indirect addressing for upper 128 bytes. Good for code compression

! Bit addressable great for managing status flags

Disadvantage! A little bit confusing, with potential for errors.

CSE466 - Fall 2002- 11

Motorola 56367 DSP

CSE466 - Fall 2002- 12

Motorola 56367 DSP

Advantages

! Three memory spaces allow ALU op and two moves simultaneously

" Macc x1,y1,a x1,x:(r3)+ y:(r6)+,y1 ; in one cycle

" Really, really,really fast

Disadvantages

! frightening to program

! Very difficult to write a good compiler

CSE466 - Fall 2002- 13

AVR CPU

CSE466 - Fall 2002- 14

Registers

CSE466 - Fall 2002- 15

Register Mapping

CSE466 - Fall 2002- 16

ALU Opcode Timing

CSE466 - Fall 2002- 17

Pipeline

CSE466 - Fall 2002- 18

SRAM access

CSE466 - Fall 2002- 19

Instructions by Type