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MICROPROCESSORS ANDINTERFACING

Instuctor : Dr. T. V. Rao

Room : C 004

Contact Hours : 4 pm 5 pm OR

with prior appointment

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Text Book :v Microprocessors and

Interfacingv by Douglas V Hall, Revised 2 nd editionv McGraw Hill Publication

Referece Books :

Brey, Intel Microprocessors The 8086,8088, 80186, 80286, 80386, 80486

Architecture, Programming & Interfacing,4th Edition, PHI. Peter Abbel, IBM PC assembly language,

5th edition PHI Yu-Cheng Liu and Glenn A. Gibson,

Microcomputer Systems: The 8086/8088

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Scope andObjectives The purpose of the

microprocessorto give an in-depth study of both

the hardware and software includedin microcomputer systems.

The conceptsare based on a particular

microprocessor, the Intel 8086, and

its associated supporting devices andsoftware and assembl lan ua e

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Main Objectives2) TO MAKE THE STUDENTS TO DEVELOP DIFFERENT TYPES OF APPLICATIONS INASSEMBLY LANGUAGE USING

8086 INSTRUCTION SET.

3) TO MAKE THE STUDENT TO BECOME HANDS ON TASM/MASM ASSEMBLER FOR THEDEVELOPMENT

OF PROGRAMS IN ASSEMBLY LANGUAGE.

4) TO MAKE THE STUDENT ANALYZE VARIOUS TYPES OF INTERFACINGS OFPERIPHERAL DEVICES .

5) TO UNDERSTAND SOME OF THE TOPICS OF COURSE BY STUDENTS THEMSELVES .

6) THE STUDENT MUST LEARN THE ADVANCED MICROPROCESSORS ARCHITECTURESESPECIALLY DUAL-CORE

AND QUAD-CORE.

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SYLLABUS UNIT I : Introduction: Microprocessor evolution and types, 8086 family overview,

8086 internal architecture, introduction to programming 8086. Programmingstructure and representation formats, Finding right instructions, writing a

program, addressing modes. 9 Hrs UNIT II : 8086 string instructions, 8086 instruction description and assembler

directives, Standard programming structures. writing and using procedures,writing and using assembler macros.

9 - Hrs UNIT III: Introduction to interfacing, Bus structure: minimum mode, Interrupts and

interrupt responses, 8259A priority interrupt controller, programmable parallelports and hand shake input and output, interfacing processor to 8255A,Peripheral interfacing: key boards, stepper motor.

9 - Hrs

UNIT IV: Maximum mode of operation, bus structure, Direct memory access Data

transfer(DMA), Interfacing with 8251A(USART), 8087 numeric data processors.9 Hrs

UNIT V : Multiuser/Multitasking operating concepts, the Intel 80286 microprocessor:architecture, real mode and protected mode, the Intel 80386: architecture, real

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BLOCK DIAGRAM OF A COMPUTER TIMESHARING SYSTEM

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BLOCK DIAGRAM OF A DISTRIBUTEDPROCESSING COMPUTER SYSTEM

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BLOCK DIAGRAM OF A SIMPLEMICROCOMPUTER

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ntel Family EvolutionProcessor Number

AlUSize(bits)

Data busSize(bits)

Address BusSize(bits)

8085 8 16 16

8086 16 16 20 Queue 6bytes

8088 8 20 20 Queue4bytes

80186 16 16 24

80286 16 16 24

80386 32 32 32

80486 32 32 32

Pentium 32 64 32

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Microprocessor Chip

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8086 Pin Diagram

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8086 INTERNAL BLOCK DIAGRAM

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8086 FLAG REGISTER FORMAT

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64Kb SEGMENT POSITION IN 1Mb AddressSpace OF 8086(One Way)

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Using CS and IP a) Physical address Diagramb)Physical address Computation

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Using SS&SPa) Physical address Diagram

b) Physical address Computation

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Using DS and Effective address accessingdata

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Flowchart for a program to read 24 samples

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Addressing Modes Datum Direct Register

Register Indirect Register relative Based Indexed Relative Based Indexed

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:mmediate Addressing mode InstructionDatum

:rect Addressing mode Instruction Mem

Address Datum

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:Register Addressing mode Instruction Register Register Datum

:egis te r Indirec t mode Instruction Register MemoryRegister Effective Address D a t u m

Register Displacement

eg is te r r ela ti ve:ddressing mode

Datum

Address

+

Instruction

Memory

Register

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Base Reg Index reg

:Based Indexed addressing mode

Datum

Address

+

Instruction

BaseRegister

Address

Index Register

MemoryEA

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Base Reg Index reg Displacement

elat ive Based Indexed:ddressing mode

Datum

Address

+

Instruction

Base Register

Address

I n d e x R e g i s t e r Memory

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Coding template for 8086 IN instructiona) Template b) Example

c) Hex codes

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Coding template for 8086 which MOV data betweenregisters or between a register and a memory location

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