midterm presentation winter 2010 performed by: tomer michaeli 052792769
DESCRIPTION
Midterm presentation Winter 2010 Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Supervisor: Shlomo Beer Gingold In collaboration with:. characterization of synchronizers and metastability. Our project subject. - PowerPoint PPT PresentationTRANSCRIPT
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Midterm presentationMidterm presentationWinter 2010Winter 2010
Performed by:Performed by:Tomer Michaeli 052792769Tomer Michaeli 052792769Liav Cohen 301242509Liav Cohen 301242509
Supervisor: Shlomo Beer GingoldSupervisor: Shlomo Beer GingoldIn collaboration with:In collaboration with:
characterization of synchronizerscharacterization of synchronizers and metastabilityand metastability
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Our project subject
Direct measurements of synchronization Circuits and comparison to measurement results by a built-in self on chip characterization unit.
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Project goals
Learning the direct measurement method.
Building and improving the measurement system for synchronization to characterize performance of synchronizers.
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Project environment
Test Chip 65nm
FPGA board
Signal generator
DLP socket (PC)
The test environment is composed by the FPGA board that generates control and data signals for the 65nm Synchronizer test chip.
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Achievements
Learning the measurement system. Learning the chip characteristics and
the measurement system GUI Initial results
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Top level design
f1=6.245 MHz
f2=6.25MHz (FPGA clock)
FF
DSO80204BScope
Input
TRIGGERDATA
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Searching for metastability
f1=6.245 MHz)data( 160.13 ns
f1=6.25 MHz)clock(
160 ns
FF out
The difference between the two clocks is 130 ps. The frequency of the FF output is 5 Khz (frequencies difference of
inputs) . The FF setup time is usually 50 ps so a metastability can occur at a 5
Khz rate. If we determine the difference to be lower than 130 ps we get less
chances for metastability. On the other hand, the probability to metastability will grow.
200 μs
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The GUI
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Test chip- top level design
(DATA)
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Test chip- Digital logic block
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The oscilloscope
The output of the flip-flop (FF) is connected through the PLD to the trigger input of the oscilloscope
The FPGA clock signal is connected through the PLD to the data channel of the scope
The digital sampling scope is capable of continuous data accumulation and the results are available for statistical analysis.
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The oscilloscope
Each data point accumulated by the scope represents one sampled rising transition of the clock signal.
Its horizontal displacement indicates the delay from the clock input to the data output of the FF.
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Initial results
figure [1]
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figure [2]
Previously known results [1]
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Initial results
In figure [2] we see the distribution of the samples propagation delay (how much longer it takes the output to be update relative to normal propagation delay).
White color indicates the largest number of cases with normal propagation delay.
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Previously known results [2]
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Project Schedule
Task Duration
-Learning the subject and building the measurement system
- Learning the chip characteristics and its GUI.
6 weeks
Initial results2 weeks
Resultscomparison to the results from the
chip
4 weeks
Results’ Analyzing 3 weeks
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References
[1] Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’ , Technion, Haifa.
[2] Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa.