mitll low-power fdsoi cmos processdilli/research/layout/...mim1), rf-optimized (rf07 and qds1), 3d...

MITLL Low-Power FDSOI CMOS Process

Design Guide

Revision 2006:4 (July 2006)Comprehensive Design Guide

© 2006 by MIT Lincoln Laboratory. All rights reserved.

This work was sponsored by the United States Air Force under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government.

MITLL Low-Power FDSOI CMOS Process: Design GuideCONTENTS

CONTENTS

Introduction............................................................................................................................................................ 7About Revision 2006:4 .............................................................................................................................................. 7About the Process ..................................................................................................................................................... 7Notes on Conventions ............................................................................................................................................... 7

Units of Measurement. .............................................................................................................................. 7Measurement Method. .............................................................................................................................. 8

Process Parameters .............................................................................................................................................. 9Process Descriptions................................................................................................................................................. 9Resistance Parameters ........................................................................................................................................... 10

High-Value Resistors Formed Using NOSLC ......................................................................................... 11Capacitance Parameters ......................................................................................................................................... 12

ILD Parameters ....................................................................................................................................... 13Notes on ILD parameters. ....................................................................................................................... 14

Other Film Parameters ............................................................................................................................................ 15Tolerance Parameters ............................................................................................................................................. 17Dopant Concentration Parameters .......................................................................................................................... 17

Design Layers ...................................................................................................................................................... 19Availability of Design Layers.................................................................................................................................... 19Notes on Design Layers .......................................................................................................................................... 26

Planar Process ....................................................................................................................................... 26Availability of Design Layers ................................................................................................................... 26Feature Bias ........................................................................................................................................... 26Fill Patterns ............................................................................................................................................. 26

Lithography Steps ............................................................................................................................................... 27Baseline Digital Process .......................................................................................................................................... 27RF Process .............................................................................................................................................................. 28Modified Digital Process for 3DM2 Tiers 1 and 2 .................................................................................................... 29Modified RF Process for 3DM2 Tier 3 ..................................................................................................................... 31Modified RF Process for QDS1 ............................................................................................................................... 33

Design Rules........................................................................................................................................................ 35Nomenclature .......................................................................................................................................................... 35Summary ................................................................................................................................................................. 36Active Area Layer (ACT, ACTF, ACTXPP).............................................................................................................. 59n-Channel Body Implant Layer (CBN) ..................................................................................................................... 61p-Channel Body Implant Layer (CBP) ..................................................................................................................... 62p-Type Capacitor Bottom Plate Implant Layer (CAPP) ........................................................................................... 63n-Type Capacitor Bottom Plate Implant Layer (CAPN) ........................................................................................... 64n-Type Capacitor Bottom Plate Implant Layer (CAPLCN)....................................................................................... 65Polysilicon Gate Layer (POLY, POLYF) .................................................................................................................. 66

Rev.: 2006:4 (Jul. 06) 3Comprehensive MITLL FDSOI design guide


Phase Shift Poly Layer (POLYPS) .......................................................................................................................... 68n+ Implant Layer (NSD) ........................................................................................................................................... 69p+ Implant Layer (PSD) ........................................................................................................................................... 71Salicide Protection Layer (NOSLC) ......................................................................................................................... 73Contact Cut Layer (CON) ........................................................................................................................................ 75Low Resistance Tungsten Gate Shunt for RF Devices (TGSRF)............................................................................ 76Metal 1 Layer (M1, M1F) ......................................................................................................................................... 78Metal 1/Metal 2 Via Layer (V12) .............................................................................................................................. 80Metal 2 Layer (M2, M2F) ......................................................................................................................................... 81Metal 2/Metal 3 Via Layer (V23) .............................................................................................................................. 83Metal 3 Layer (M3, M3F) ........................................................................................................................................ 84Metal 3/Metal 4 Via Layer (V34) ............................................................................................................................. 84Metal 4 Layer (M4, M4F) ........................................................................................................................................ 85Metal 4/Metal 5 Via Layer (V45) ............................................................................................................................. 85Metal 5 Layer (M5, M5F) ........................................................................................................................................ 86Top-Level RF Metal Via Layer (VTLRF) .................................................................................................................. 87Top-Level RF Metal Layer (MTLRF, MTLRFF) ....................................................................................................... 88Overglass Pad Cut Layer (OGC)............................................................................................................................. 89Metal Z Layer, Alternative Single Metal (MZ, MZF) ................................................................................................ 90MIM Capacitor Layer (MIMCAP)–Anodized Aluminum Version .............................................................................. 90MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version.................................................................................... 91MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version with Wet Etch............................................................. 913D Via Cut to Another Wafer Tier (3DCUT) ............................................................................................................ 923D Via Landing from Another Wafer Tier (3DLAND)............................................................................................... 94Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP) ............................................................................................ 953D Back Side Cut Through Buried Oxide (3DBOXC).............................................................................................. 953D Back Side Metal Gate (3DBMG) ........................................................................................................................ 95Pad Cut for Final 3D Stack (3DOGC)...................................................................................................................... 95Common Landing Metal Flag (3DCNX)................................................................................................................... 96Back Side Metallization Layers................................................................................................................................ 96Back Side Metal 1/Front Side Metal 1 Via Layer (BVIA0) ....................................................................................... 96Back Side Metal 1 Layer (BM1) ............................................................................................................................... 96RF Back Side Metal 1 Layer (BM1) ......................................................................................................................... 97Overglass Cut to Back Side Metal 1 (BOGC1)........................................................................................................ 97Back Side Metal 2/Back Side Metal 1 Via Layer (BVIA1)........................................................................................ 97Back Side Metal 2 Layer (BM2) ............................................................................................................................... 98Overglass Cut to Back Side Metal 2 (BOGC2)........................................................................................................ 98Additional Layers: Flag and Comment (Markup) .................................................................................................... 98NOFILL .................................................................................................................................................................... 98Channel Flag Region (FLGCHAN) .......................................................................................................................... 98Voltage Flag Layers (FLG33, FLG50) ..................................................................................................................... 99

4 Rev.: 2006:4 (Jul. 06) Comprehensive MITLL FDSOI design guide


DEVR....................................................................................................................................................................... 99DEVL ....................................................................................................................................................................... 99DEV-MC .................................................................................................................................................................. 99DEVD....................................................................................................................................................................... 99NOSLOT.................................................................................................................................................................. 99Red, Green, Blue, Yellow ........................................................................................................................................ 99

Layout Acceptance Requirements................................................................................................................... 101Design Grid............................................................................................................................................................ 101Layout Database Format ....................................................................................................................................... 101Top-Level Cell Labels ............................................................................................................................................ 1013D Layout and Tier Orientation ............................................................................................................................. 101Minimum Rule Set ................................................................................................................................................. 102Contact Information ............................................................................................................................................... 102Disclaimer .............................................................................................................................................................. 102

Miscellaneous .................................................................................................................................................... 105Special Notes for QDS1 ........................................................................................................................................ 105Special Notes for 3DM2......................................................................................................................................... 106

Contact Information .......................................................................................................................................... 111Revision History ................................................................................................................................................ 113


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MITLL Low-Power FDSOI CMOS Process: Design GuideINTRODUCTION

1. INTRODUCTION

1.1. About Revision 2006:4

This document contains Revision 2006:4 of the design guide for MIT Lincoln Laboratory’s 0.18-µ m low-power FDSOI CMOS process. It is intended for use as a reference guide for all MITLL FDSOI process versions. Design layers for linear capacitors, phase-shift-defined poly gates, and salicide protection are included.

Many versions of the MITLL FDSOI process are available. Therefore, left-marginalized, color-coded abbreviations or symbols are used to indicate the applicability of information or standards to particular reticle set(s). Symbols in blue designate the relevance of entire sections to the indicated set(s). Red symbols override the blue, designating applicability of individual subsections, paragraphs, or lines to the set(s).

This version of the guide applies to sets in the following MITLL FDSOI process versions: digital (YES2 and MIM1), RF-optimized (RF07 and QDS1), 3D (3DL1 and 3DM2), and 3D imager (MSC2).

For 3DM2, some margin notes are tier specific. In this case, the tier number is appended to the run identifier; e.g., 3DM2-T2 indicates tier 2 for the 3DM2 run.

1.2. About the Process

Consistent with its focus on research and development, Lincoln Laboratory has developed numerous process modules. In each MITLL process version, selected modules are combined in a way that optimizes the process for a particular set of applications. Some process steps are common to all process versions; others are rarely used. The most typical versions are described in the process parameters section. One typical version is a three-metal digital process. The other is an RF-optimized process in which the third metal level is optimized for design of passive components and trench contacts may be formed along MOS gates to reduce series resistance. Additional modules for experimental technologies such as 3D stacking, deeply scaled devices, low-voltage-coefficient capacitors, and dual-gate devices are available in other application-specific process versions. The goal of this document is to provide information pertaining to all available process modules so that it may serve as a comprehensive reference manual.

1.3. Notes on Conventions

1.3.1. Units of Measurement. In this era of deep-submicron scaling, it is becoming increasingly common to express feature sizes in nanometers rather than microns. Unfortunately, this often causes difficulty for designers who have Electronic Design Automation (EDA) tool configurations and legacy data with user units corresponding to microns. To aid designers, we have chosen to express all design rule values in microns. To facilitate quick conversion to nanometers, we have also elected to consistently maintain three decimal places. This convention does not apply to measured values and tolerance parameters, for which the number of decimal places must reflect the precision. Thickness parameters are consistently expressed in nanometers.


MITLL Low-Power FDSOI CMOS Process: Design GuideINTRODUCTION

1.3.2. Measurement Method. Throughout this guide all distances are Euclidean unless otherwise specified.


MITLL Low-Power FDSOI CMOS Process: Design GuidePROCESS PARAMETERS

2. PROCESS PARAMETERS

This section presents parameters for the three-metal digital FDSOI process and the RF-optimized FDSOI process. Parameters related to other optional process modules not part of these basic versions are also included. Note that electrical parameters are given for devices at 300 K.

YES2; MSC2; RF07; 3DL1; MIM1; QDS1; 3DM2

2.1. Process Descriptions

The digital and RF-optimized process versions may utilize either local or global SOI thinning. Modules available in other process versions include higher-level metals, deeply scaled PSM gates, 3D integration, local silicide, and additional implants.

YES2 • YES2 digital process version. FDSOI CMOS process with single-level poly and three-level metal with stacked contacts and vias, MIM capacitors, and local salicide. Only 1.5-V devices are available.

MIM1 • MIM1 digital process version. FDSOI CMOS process with single-level poly and five-level metal with stacked contacts and vias, MIM capacitors, and local salicide. 1.5-V and 3.3-V devices are available.

RF07 • RF07 RF-optimized process version. FDSOI CMOS process with single-level poly, two interconnect metal levels, and one metal level with ILD and metal thicknesses optimized for design of RF passives. Trench contacts may be formed along MOS gates to reduce series resistance. Contacts and vias may be stacked. Only 1.5-V MOS devices are available.

3DL1 • 3DL1 3D process version. Three tiers, each individually fabricated in the MITLL 0.18-µ m 1.5-V digital FDSOI process version, are vertically stacked and interconnected using dense inter-tier vias. The digital process version is an FDSOI CMOS process with single-level poly and triple-level metal with stacked contacts and vias.

MSC2 • MSC2 3D imager version. Two tiers are optimized for imager design. Only 3.3-V devices are available.

QDS1 • QDS1 RF-optimized process version. FDSOI CMOS process with single-level poly, two interconnect metal levels, and one metal level with ILD and metal thicknesses optimized for design of RF passives. Trench contacts may be formed along MOS gates to reduce series resistance. Contacts and vias may be stacked. Only 1.5-V MOS devices are available. FDSOI CCD structures may be formed using phase-shift-defined polysilicon cuts. Interconnect vias are borderless as fabricated for improved contacted metal pitch.

3DM2 • 3DM2 3D process version. Three tiers are vertically stacked and interconnected using dense inter-tier vias. Tiers 1 and 2 are each individually fabricated in the MITLL 0.18-µ m 1.5-V digital FDSOI process version, which includes single-level poly and triple-level metal with stacked contacts and vias. Tier 2 includes an additional back side metallization layer. Tier 3 is implemented using the MITLL 0.18-µ m 1.5-V RF-optimized process version, which includes single-level poly, three interconnect metal levels, a back side metallization level with ILD and metal thicknesses optimized for design of RF passives, tungsten gate shunts for reduced gate series resistance, local salicide, and stacked contacts and vias. Interconnect vias on all tiers are borderless as fabricated for improved contacted metal pitch. A top-level RF metal layer is not included on tier 3; rather back metal 1 should be used for formation of passives.




2.2. Resistance Parameters

Tables 2-1 through 2-4 list resistivity and resistance parameters. MITLL is working on improvements to the silicidation process that will affect the sheet resistance of all silicide layers and possibly the resistance of contacts to poly and active. Values may be lower than those given in the tables by as much as 50%. Further information will be provided as soon as it is available.

Table 2-1: Bulk resistivity (p-type handle wafer)

Parameter Value

Standard float zone substrate ~2000 Ω-cm

Table 2-2: Cobalt silicided silicon sheet resistance

Parameter Value

Silicided n+ active sheet resistance 15 ± 3 Ω/sq

Silicided p+ active sheet resistance 15 ± 3 Ω/sq

Silicided n+ polysilicon sheet resistance 15 ± 3 Ω/sq

Silicided p+ polysilicon sheet resistance 15 ± 3 Ω/sq

Table 2-3: Metal sheet resistances

Parameter Value

Lower level metal (all but top level) ~0.12 Ω/sq

Top-level metal:

YES2; MSC2; 3DL1; 3DM2 Digital process version (M3) ~0.08 Ω/sq

RF07; QDS1 RF process version (MTLRF) ~0.015 Ω/sq

YES2; RF07; QDS1 Metal Z (may be available)* ~0.1 Ω/sq

Back side metal:

3DM2-T2 Interconnect back side metal ~0.12 Ω/sq

3DM2-T3 RF-optimized back side metal ~0.015 Ω/sq

*See MITLL Low-Power FDSOI CMOS Process: Application Notes for an explanation of metal Z.



YES2; MIM1; QDS1; 3DM2-T3

2.2.1. High-Value Resistors Formed Using NOSLC. Resistors of more than a few hundred ohms can be made using poly and silicide block (NOSLC). The resistor is doped by the NMOS extension implant, which is specified by layer NSD. The silicide block, layer NOSLC, works by masking the spacer etch so that silicon nitride prevents formation of the silicide. That nitride also blocks the degenerate source-drain implant, so the amount of doping in the POLY is limited to the extension plus the halo implant. POLY doped with the present NMOS extension and halo implant has sheet resistance of ~400 Ω/sq. The details of those implants are determined by the requirements for short-channel transistors, and they will certainly be adjusted in the future. Designers are warned that the sheet resistance of (POLY + NSD + NOSLC) resistors could change by a factor of two in either direction. Matching of resistors on a given wafer has not been characterized, but it is expected to be within a few percent and should be unaffected by future changes in the implants. Dependence of resistance on temperature has also not been characterized, but designers should be aware that the resistors are isolated from the substrate heat sink by 400 nm of SiO2. The PMOS extension implant has much lower dose and is expected to produce at least ten times higher sheet resistance, but it has not been characterized at all.

The contacts at the two ends of the resistor must have silicide. Spacing details are covered by the design rules. There are no special rules on width or length of resistors, but of course small values of either width or length will result in more relative variability than large values.

Table 2-4: Contact and via resistances

Parameter* Value

Poly contact (0.250 µ m x 0.250 µ m) 10 ± 2 Ω

n+ active contact (0.250 µ m x 0.250 µ m) 10 ± 2 Ω

p+ active contact (0.250 µ m x 0.250 µ m) 10 ± 2 Ω

Interconnect metal via (0.300 µ m x 0.300 µ m) 4 Ω

RF07; QDS1 Top-level RF metal via (0.450 µ m x 0.450 µ m) 2.5 Ω

3DM2-T2; 3DM2-T3 Back side metal via 0 (BVIA0) (0.500 µ m x 0.500 µ m) 2.0 Ω

*Sizes are as drawn.




2.3. Capacitance Parameters

Capacitance parameters are summarized in Tables 2-5 and 2-6. See also “Device Characteristics” in MITLL Low-Power FDSOI CMOS Process: Device Models. Nearbody coupling capacitance is not easily represented in tabular form. However, this data is available to designers in the form of EDA tool technology files.

Table 2-5: Summary of capacitance parameters for 1.5-V devices

Parameter Value

MOS gate oxide (Cox) in inversion 6.5 fF/µ m2

n+ poly gate to CAPN active at +1.5 V 6.5 fF/µ m2

p+ poly gate to CAPP active at –1.5 V 6.5 fF/µ m2

Active island or poly to handle wafer (Cbox) 86 aF/µ m2

CAPLCN-implanted active to NSD-implanted poly(Low temperature and voltage coefficient capacitor)

5.2 fF/µ m2

Table 2-6: Summary of capacitance parameters for 3.3-V devices (drawn using FLG33)

Parameter Value

MOS gate oxide (Cox) in inversion 3.9 fF/µ m2

n+ poly gate to CAPN active at +3.3 V 3.9 fF/µ m2

p+ poly gate to CAPP active at –3.3 V 3.9 fF/µ m2

Active island or poly to handle wafer (Cbox) 86 aF/µ m2



2.3.1. ILD Parameters. Parameters for digital process and RF process versions are presented In Tables 2-7 and 2-8, respectively.

YES2; MSC2; 3DL1; MIM1; 3DM2

Table 2-7: ILD thickness and interconnect overlap and fringe capacitances: digital process versions

From Layer:

ActivePoly

(field)Poly

(on active)Metal 1 Metal 2

To Substrate:

Nominal thickness 400 nm 400 nm 1250 nm 2880 nm 4510 nm

Area capacitance 86 aF/µ m2 86 aF/µ m2 29 aF/µ m2 13 aF/µ m2 8 aF/µ m2

Fringe capacitance - - - - -

To Metal 1:

Nominal thickness 800 nm 650 nm 600 nm - -

Area capacitance 47 aF/µ m2 59 aF/µ m2 63 aF/µ m2 - -

Fringe capacitance 38 aF/µ m 47 aF/µ m 48 aF/µm - -

To Metal 2:

Nominal thickness 2430 nm 2280 nm 2230 nm 1000 nm -

Area capacitance 15 aF/µ m2 17 aF/µ m2 17 aF/µ m2 37 aF/µ m2 -

Fringe capacitance 35 aF/µ m 40 aF/µ m 40 aF/µm 54 aF/µ m -

To Metal 3:



Fringe capacitance 34 aF/µ m 38 aF/µ m 38 aF/µm 45 aF/µ m 54 aF/µ m



RF07; QDS1 Table 2-8: ILD thickness and interconnect overlap and fringe capacitances: RF process versions

2.3.2. Notes on ILD parameters. In Tables 2-7 and 2-8 the values for area capacitance are measured on lot neo1 (MP5 reticle set). The values for fringe capacitance are based on a model in which fringe field lines from one layer terminate on an infinite ground plane on another layer. MITLL welcomes measurement results on parasitic capacitance from multiproject designers. (EDA technology files for parasitic capacitance extraction are available from MITLL.) The ILD is planarized, resulting in a layout-dependent thickness distribution. Chemical-mechanical polishing (CMP) is most effective when active, poly, and metal features are evenly distributed across the wafer.

From Layer:

ActivePoly

(field)Poly

(on active)Metal 1 Metal 2

To Metal 1:

Nominal thickness 800 nm 650 nm 600 nm - -

Area capacitance 49 aF/µ m2 59 aF/µ m2 63 aF/µ m2 - -

Fringe capacitance 38 aF/µ m 47 aF/µ m 48 aF/µm - -

To Metal 2:

Nominal thickness 2430 nm 2280 nm 2230 nm 1000 nm -

Area capacitance 15 aF/µ m2 17 aF/µ m2 17 aF/µ m2 40 aF/µ m2 -

Fringe capacitance 35 aF/µ m 40 aF/µ m 40 aF/µm 54 aF/µ m -

To Metal 3:



Fringe capacitance - - - - -




2.4. Other Film Parameters

Tables 2-9 through 2-11 present properties of various process levels.

Table 2-9: Thickness and other parameters

Parameter Value

MOS transistor gate oxide thickness (ellipsometric)

YES2; RF07; 3DL1; QDS1; 3DM2 1.5-V process 4.2 nm

MSC2 3.3-V process 7.0 nm

SOI buried oxide (BOX) thickness 400 nm

SOI silicon thickness (in channel region) 40 nm

Polysilicon thickness 200 nm

Gate/silicide spacer thickness

YES2; RF07; 3DL1; QDS1; 3DM2 1.5-V process 10 nm : 65 nm

MSC2 3.3-V process 150 nm

Gate/silicide spacer material

YES2; RF07; 3DL1; QDS1; 3DM2 1.5-V process SiO2 : Si3N4

MSC2 3.3-V process SiO2

Isolation technology Mesa-etched

Overglass thickness 1000 nm, not planarized

Thermal oxide dielectric constant 3.9

Deposited ILD oxide dielectric constant 4.2

Silicon substrate thickness 675 ± 25 µ m

Silicon thermal conductivity 1.5 W/cm-K

SiO2 thermal conductivity 14 mW/cm-K



MITLL does not have a formal electromigration requirement for current density in metal wires and vias because we expect that our multiproject lots will be used for demonstration of concepts in the short term, not for deployment in the field. We have found that current density in the aluminum of up to 3 mA/µ m2 of aluminum cross section has been acceptable for our circuits and test devices. This translates as 1.5 mA/µ m of metal linewidth for the digital process metal layers and 6 mA/µ m of linewidth for the RF metal.


Table 2-10: Structure of metal layers: digital process version

RF07; QDS1 Table 2-11: Structure of metal layers: RF process version

(Bottom to top)

Contact plug metal

To active island Ti:TiN:W (30 nm : 75 nm : 700 nm)

To field poly Ti:TiN:W (30 nm : 75 nm : 550 nm)

Via plug metal Ti:TiN:W (30 nm : 75 nm : 900 nm)

Metal levels Ti:AlSi :Ti:TiN (40 nm : 500 nm : 40 nm : 50 nm)

(Bottom to top)

Contact plug metal

To active island Ti:TiN:W (30 nm : 75 nm : 700 nm)

To field poly Ti:TiN:W (30 nm : 75 nm : 550 nm)

3DM2-T3 RF gate shunt (TGSRF) metal Ti:TiN:W (30 nm : 75 nm : 500 nm)

Via plug metal

Below top level Ti:TiN:W (30 nm : 75 nm : 900 nm)

Top level Ti:TiN:W (30 nm : 75 nm : 1400 nm)

Metal levels

Below top level Ti:AlSi:Ti:TiN (40 nm : 500 nm : 40 nm : 50 nm)

Top level Ti:AlSi:Ti:TiN (40 nm : 2000 nm : 40 nm : 50 nm)




2.5. Tolerance Parameters

Active island and polysilicon width tolerances are presented in Table 2-12.

Table 2-12: Width tolerance parameters


2.6. Dopant Concentration Parameters

Table 2-13 presents n- and p-type dopant concentration parameters.

Table 2-13: Dopant concentration parameters

Parameter Value

Active island width(Active is bloated by 0.075 µ m per side in making the reticle. Channel width is normally determined by sidewall post processing; see MITLL Low-Power FDSOI CMOS Process: Application Notes.)

±0.025 µ m

Polysilicon width(For 1.5-V processes, poly widths drawn at 0.200 µ m are exposed to produce 0.180-µ m etched poly width on the silicon wafer.)

±0.020 µ m

Parameter ValueSheet

Resistance

p-channel active (CBP) n-type dopant concentration ~5x1017/cm3

n-channel active (CBN) p-type dopant concentration ~5x1017/cm3

CAPP* p-type dopant concentration(NMOS sidewall implant used for capacitor)

~5x1018/cm3 ~5 kΩ/sq

CAPN* n-type dopant concentration(PMOS sidewall implant used for capacitor)

~1x1019/cm3 ~1 kΩ/sq

CAPLCN n-type dopant concentration(Low temperature and voltage coefficient capacitor)

~1x1020/cm3 ~160 Ω/sq

*CAPN and CAPP can be used to form high-value resistors using active regions. Salicide protection is required. See MITLL Low-Power FDSOI CMOS Process: Application Notes for details.


MITLL Low-Power FDSOI CMOS Process: Design GuideDESIGN LAYERS

3. DESIGN LAYERS

3.1. Availability of Design Layers

The following chart summarizes availability of design layers for the digital (YES2 and MIM1), MSC 3D imager (MSC2), RF-optimized (RF07 and QDS1), and 3D (3DL1) process versions. Note that GDS layers not listed below are used in post-submission processing or reserved for future use. GDS layers not listed for a target process will be filtered out.

GDS CIF Layer No. Name Description Note YES2 MSC2 RF07 3DL1 MIM1 QDS1 3DM2

Availability

ACT 1 ACT Active island

ACTF 2 ACTF Active island fill

ACTXPP 3 ACTX Active island with suppressed [1]sidewall processing

CBN 4 CBN n-Channel body implant

CBP 5 CBP p-Channel body implant

CAPP 6 CAPP ~5x1018 cm-3 p-type island implant

CAPN 7 CAPN ~1x1019 cm-3 n-type island implant

CAPLCN 8 CLC ~1x1020 cm-3 n-type island implant

POLY 9 POLY Polysilicon

POLYF 10 POLF Polysilicon fill

POLYPS 11 PPS Phase shift poly flag

NSD 12 NSD n+ Implant (degenerate doping)

Note: [1] ACTXPP suppresses normal post-submission processing. Not for general use. See MITLL Low-Power FDSOI CMOS Process: Application Notes.

Availability indicators: = available for this run. T2,T3 = available only on specified tier. = available for MITLL AST group use only. = available, but not for general design use; see MITLL Low-Power FDSOI CMOS Process: Application Notes.




Availability

PSD 13 PSD p+ Implant (degenerate doping)

NOSLC 14 XSLC Salicide protection T3

CON 15 CON Contact cut(metal 1 to active or poly)

TGSRF 16 TGRF Low-resistance tungsten gate [3] T3shunt for RF

M1 17 M1 Metal 1

M1F 18 M1F Metal 1 fill

V12 19 V12 Metal 1/metal 2 via

M2 20 M2 Metal 2



M3 23 M3 Metal 3



M4 26 M4 Metal 4



Note: [3] Formerly CONRFG.





Availability

M5 29 M5 Metal 5


VTLRF 31 VRF MTLRF/next lower metal via

MTLRF 32 MRF Top level metal for RF process

MTLRFF 33 MRFF MTLRF fill

OGC 34 OGC Overglass cut

MZ 36 MZ Metal for single metal process [2]

MZF 37 MZF Metal fill for single metal process [2]

3DCUT 41 3DCT 3D via cut to another wafer tier T2,3

3DLAND 42 3DLD Landing of 3D via from another T1,2wafer tier

3DALT 43 3DAR Flag for alternative 3D via rule set

3DFLIP 44 3DFL Flag for flipped wafer tier w.r.t.final 3D stack

3DBOXC 45 3DBX 3D back side pad cut throughburied oxide

3DBMG 46 3DBM 3D back side metal gate

3DOGC 47 3DPC Pad cut for final 3D stack [4] T3

3DCNX 48 3DCX Flag to indicate 3D via cuts share T2,3a common landing pad

Notes: [2] MZ is an alternative metal layer to be used in experimental fabrication runs that use only one layer of metal. See MITLL Low-Power FDSOI CMOS Process: Application Notes. [4] Formerly 3DPAD.





Availability

NOFILL 51 XFIL Flag to suppress generationof fill structures

DEVR 52 DEVR Indicates device is resistorfor verification and simulation

DEVL 53 DEVL Indicates device is inductorfor verification and simulation

DEVMC 54 DVMC Indicates metal 1-2 capacitor devicefor verification and simulation

DEVD 55 DEVD Indicates device is lateral diodefor verification and simulation

RED 58 RED Comment layer

GREEN 59 GRN Comment layer

BLUE 60 BLUE Comment layer

YELLOW 61 YELW Comment layer

BVIA0 62 BV0 Via from front metal 1 T2,3to back side metal 1

BM1 63 BM1 Back side metal 1 T2,3

BOGC1 64 BOG1 Back side overglass contact cutto back metal 1

BVIA1 65 BV1 Via from back side metal 1to back side metal 2

BM2 66 BM2 Back side metal 2

BOGC2 67 BOG2 Back side overglass contact cutto back metal 2

FLGCHAN 80 FLCH Channel region indicator forspecial device verification

FLG33 86 FL33 Flag to indicate 3.3-V device

FLG50 87 FL50 Flag to indicate 5.0-V device





Availability

PORTHANDLE 104 HDLP Port layer text for handlewafer node

PORTACT 105 ACTP Port layer text for active

PORTPOLY 106 POLP Port layer text for poly

PORTM1 107 M1P Port layer text for metal 1





PORTMTLRF 112 MRFP Port layer text for MTLRF

PORTMZ 113 MZP Port layer text for metal Z

PORTBM1 114 BM1P Port layer text for back metal 1

PORTBM2 115 BM2P Port layer text for back metal 2

TEXTACT 121 ACTT Net annotation text layer for active

TEXTPOLY 122 POLT Net annotation text layer for poly

TEXTM1 123 M1T Net annotation text layer for metal 1







Availability



TEXTMTLRF 128 MRFT Net annotation text layer for MTLRF

TEXTMZ 129 MZT Net annotation text layer for metal Z

TEXTBM1 130 BM1T Net annotation text layer for back metal 1

TEXTBM2 131 BM2T Net annotation text layer forback metal 2

ACTBLKG 140 ACBX Active blockage layer for automaticrouting tools

POLYBLKG 141 POBX Poly blockage layer for automaticrouting tools

M1BLKG 142 M1BX Metal 1 blockage layer for automaticrouting tools





MZBLKG 147 MZBX Metal Z blockage layer for automaticrouting tools

MTLRFBLKG 148 MRBX MTLRF blockage layer for automaticrouting tools

NOSDX 150 XSDX Flag to suppress source/drain T3extension implant

NODEG 151 XDEG Flag to suppress source/drain T3degenerate implant





Availability

TKOX 152 TKOX Flag to force thick gate oxide

MIMCAP 153 MCAP MIM capacitor




3.2. Notes on Design Layers

3.2.1. Planar Process. The FDSOI devices in this process require a silicon island thickness of about 40 nm. These thin silicon regions are formed by global oxidation thinning.

3.2.2. Availability of Design Layers. The MITLL 0.18-µ m low-power FDSOI CMOS process is a baseline process upon which many application-specific processes have been built. The design layer tables in Sections 3.1–3.4 reflect this multitude of process versions. In all process versions, optional layers that are not part of the baseline process are designated by a footnote. Each application-specific process version will include a subset of these additional optional layers. Please contact MIT Lincoln Laboratory for more details.

3.2.3. Feature Bias. Minimum-width (0.18 µ m) poly features are drawn at 0.200 µ m. Exposure and etch bias will produce poly lines 0.18 ± 0.02 µ m. Contacts and vias will be slightly oversized through lithographic feature bias.

To avoid formation of parasitic edge transistors, layout data will be post-processed by Lincoln Laboratory to allow for sidewall implants. This operation will create the required sidewall implant mask layers, and will adjust the size of active islands slightly to ensure that MOS channel widths correspond to the drawn data. Active island features are bloated by 0.075 µ m per side during sidewall post-processing. For more information see the section on layout post-processing for sidewall implants in MITLL Low-Power FDSOI CMOS Process: Application Notes.

3.2.4. Fill Patterns. The design layer sections above include nine fill layers: ACTF, POLYF, M1F, MZF, M2F, M3F, M4F, M5F, and MTLRFF. These are for inclusion of fill patterns on active, poly, and metal layers to achieve the required feature densities. These layers will be logically ORed with ACT, POLY, M1, MZ, M2, M3, M4, M5, and MTLRF, respectively, before physical masks for these layers are generated. These layers should only be used for fill features that do not contribute to the circuit topology of the design. They may also be used for labels.

Submitted layouts will be post-processed to create patterns of floating rectangles to fill unoccupied regions on each active, poly, and metal level. The output of this automatic generation routine for each design will be made available to its designer, with several days allowed for designer rework. To suppress this automatic fill generation, the NOFILL layer is provided. Note that submitted layouts that use the NOFILL layer must be compliant with layer density specifications. Density violations may affect other designs on a multiproject die; hence Lincoln Laboratory may require changes in designs that violate density rules.

See MITLL Low-Power FDSOI CMOS Process: Application Notes for more details.


MITLL Low-Power FDSOI CMOS Process: Design GuideLITHOGRAPHY STEPS

4. LITHOGRAPHY STEPS

This section describes lithography steps for several exemplary FDSOI process versions. In actual runs the lithography flow may be slightly different. Contact MITLL for further information or lithography steps for a specific run.

YES2; 3DL1 4.1. Baseline Digital Process

Step Field Reticle Related Design Layers Description

1 Clear Active area ACT, ACTF, ACTXPP Defines silicon islands

2 Dark n-channel sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls

3 Dark p-channel sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls

4 Dark n-channel body implant CBN n-channel threshold adjust implant

5 Dark p-channel body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect

7 Dark n+ implant mask (NSD) NSD Implant n-channel source/drain extensions

8 Dark p+ implant mask (PSD) PSD Implant p-channel source/drain extensions

9 Dark n+ implant mask (NSD) NSD Implant n+ degenerate regions

10 Dark p+ implant mask (PSD) PSD Implant p+ degenerate regions

11 Dark Contact cut CON Defines contacts to active and poly

12 Clear Metal 1 M1, M1F Defines first-level metal interconnect

13 Dark Via 12 V12 Defines metal 1/metal 2 vias

14 Clear Metal 2 M2, M2F Defines second-level metal interconnect


16 Clear Metal 3 M3, M3F Defines third-level metal interconnect

17 Dark Overglass OGC Defines pad openings in overglass

Total Photolithography Levels: 17

Total Reticles: 15



RF07 4.2. RF Process



2 Dark n-channel sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls

3 Dark p-channel sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls

4 Dark n-channel body implant CBN n-channel threshold adjust implant

5 Dark p-channel body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect

7 Dark n+ implant mask (NSD) NSD Implant n-channel source/drain extensions

8 Dark p+ implant mask (PSD) PSD Implant p-channel source/drain extensions

9 Dark n+ implant mask (NSD) NSD Implant n+ degenerate regions

10 Dark p+ implant mask (PSD) PSD Implant p+ degenerate regions

11 Dark RF gate shunt TGSRF Defines tungsten gate shunt

12 Dark Contact cut CON Defines contacts to active and poly




16 Dark VTLRF via VTLRF Defines metal 2/metal 3 vias

17 Clear MTLRF top metal MTLRF, MTLRFF Defines third-level metal interconnect

18 Dark Overglass OGC Defines pad openings in overglass

Total Photolithography Levels: 18

Total Reticles: 16



3DM2-T1; 3DM2-T2

4.3. Modified Digital Process for 3DM2 Tiers 1 and 2



2 Dark NMOS sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls and p-type capacitor bodies

3 Dark PMOS sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls and n-type capacitor bodies

4 Dark NMOS body implant CBN n-channel threshold adjust implant

5 Dark PMOS body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect after etch of narrow slots

7 Dark NMOS source and drain NSD Implant n-channel source/drain extensions

8 Dark PMOS source and drain PSD Implant p-channel source/drain extensions

9 Dark NMOS source and drain NSD Implant n+ degenerate regions (blocked by NOSLC or POLY)

10 Dark PMOS source and drain PSD Implant p+ degenerate regions (blocked by NOSLC or POLY)

11 Dark Contact cut CON Defines holes in oxide for contacts to oxide and poly


13 Dark Via 12 V12 Defines holes in oxide for metal 2/metal 1 vias


15 Dark Via 23 V23 Defines holes in oxide for metal 3/metal 2

vias

Continued on next page



3DM2-T1; 3DM2-T2

4.3. Modified Digital Process for 3DM2 Tiers 1 and 2 (Continued)


16 Clear Metal 3 M3, M3F Defines normal-thickness third-level metal interconnect

17 Dark Overglass OGC* Defines probe and bonding openings in overglass

Total photolithography levels: 17 before wafer bonding

Total reticles: 15 before wafer bonding

*Not for general use.

After wafer bonding, handle wafer removal, and 3D via formation, 3DM2-T2 gets additional oxide, vias BVIA1, and back

metal BM1. Overglass is used only for wafer-yield testing before wafer bonding. OGC should only be used for circuits

that are testable before wafer bonding. 3DOGC should be used to define overglass cuts for the final assembly.



3DM2-T3 4.4. Modified RF Process for 3DM2 Tier 3



2 Dark NMOS sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls and p-type capacitor bodies

3 Dark PMOS sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls and n-type capacitor bodies

4 Dark NMOS body implant CBN n-channel threshold adjust implant

5 Dark PMOS body implant CBP p-channel threshold adjust implant

6 Clear Polysilicon ACT, POLY, POLYF Defines polysilicon gates and interconnect after etch of narrow slots

7 Dark NMOS extension (XN) NSD, NOSDX Implant n-channel source/drain extensions

8 Dark PMOS extension (XP) PSD, NOSDX Implant p-channel source/drain extensions

9 Clear Silicide block NOSLC Defines Si3N4 silicide block that accompanies sidewall spacers

10 Dark NMOS source and drain NSD Implant n+ degenerate regions (blocked by NOSLC or POLY)

11 Dark PMOS source and drain PSD Implant p+ degenerate regions (blocked by NOSLC or POLY)

12 Dark RF gate shunt TGSRF Defines slot in oxide for tungsten gate shunt

13 Dark Contact cut CON Defines holes in oxide for contacts to oxide and poly








3DM2-T3 4.4 Modified RF Process for 3DM2 Tier 3 (Continued)


18 Clear Metal 3 M3, M3F Defines normal-thickness third-level metal interconnect

19 Dark Overglass OGC* Defines probe and bonding openings in overglass

Total photolithography levels: 19 before wafer bonding

Total reticles: 19 before wafer bonding

*Not for general use.

After wafer bonding, handle wafer removal, and 3D via formation, 3DM2-T3 gets additional oxide, vias BVIA1, thick

back metal BM1 and overglass. Overglass is used only for wafer-yield testing before wafer bonding. OGC should

only be used for circuits that are testable before wafer bonding. 3DOGC should be used to define overglass cuts

for the final assembly.



QDS1 4.5. Modified RF Process for QDS1

Step Field Resist Reticle Related Design Layers Description

1 Clear + Active area ACT, ACTF, ACTXPP Defines silicon islands

2 Dark + NMOS sidewall implant ACT, POLY, CBN, CAPP Implant n-channel island sidewalls and p-type capacitor bodies

3 Dark + PMOS sidewall implant ACT, POLY, CBP, CAPN Implant p-channel island sidewalls and n-type capacitor bodies

4 Dark + NMOS body implant CBN n-channel threshold adjust implant

5 Dark + PMOS body implant CBP p-channel threshold adjust implant

6 Dark + CCD graded implant GRADED_IMP CCD graded Implant

7 Dark + CCD gate implant CCDGI Pre-implant CCD gate poly

8 Clear – Phase shift poly slots PSM_180, PSM_CHROME 100-nm slots in poly using phase edge and negative resist for CCDs

9 Dark – Erase poly slots defined in SLOT_ERASE Fill in unwanted CCD slots by second previous PSM exposure exposure of negative resist

10 Clear + Polysilicon ACT, POLY, POLYF Defines poly gates and interconnect after etch of narrow slots

11 Dark + NMOS extension (XN) NSD, NOSDX Implant n-channel source/drain extensions

12 Dark + PMOS extension (XP) PSD, NOSDX Implant p-channel source/drain extensions

13 Clear + Silicide block NOSLC Defines Si3N4 silicide block that accompanies sidewall spacers

14 Dark + NMOS source and drain NSD Implant n+ degenerate regions (blocked by NOSLC or POLY)

15 Dark + PMOS source and drain PSD Implant p+ degenerate regions (blocked by NOSLC or POLY)

16 Dark + RF gate shunt TGSRF Defines slot in oxide for tungsten gate shunt

17 Dark + Contact cut CON Defines holes in oxide for contacts to oxide and poly




QDS1 4.5 Modified RF Process for QDS1 (Continued)

Step Field Resist Reticle Related Design Layers Description

18 Clear + Metal 1 M1, M1F Defines first-level metal interconnect

19 Dark + Via 12 V12 Defines holes in oxide for metal 2/ metal 1 vias

20 Clear + Metal 2 M2, M2F Defines second-level metal interconnect

21 Dark + RF vias VTLRF Defines larger holes in thicker oxide for metal RF/metal 2 vias

22 Clear + RF metal MTLRF, MTLRFF Defines thicker third-level metal interconnect

23 Dark + Overglass OGC Defines probe and bonding openings in overglass

Total photolithography levels: 23

Total reticles: 23


MITLL Low-Power FDSOI CMOS Process: Design GuideDESIGN RULES

5. DESIGN RULES


5.1. Nomenclature

In order to facilitate a concise presentation of the design rules, the following terms will be used:

• Gate region is the intersection of POLY and ACT.

• MOS channel region is the intersection of POLY and ACT without CAPN, CAPP, or CAPLCN. Exception: Where one side of a poly line receives an NSD implant and the other receives a PSD implant, that width is excluded from the MOS channel region. This excluded region is seen in body-contacted transistor and diode layouts. To ensure proper determination of the MOS channel region for verification and simulation, FLGCHAN (layer 80) should be drawn over the desired MOS channel region.

• Capacitor region is the intersection of POLY and ACT inside CAPLCN, CAPN, or CAPP. It corresponds to the drawn area of a capacitor.

• Gate extension is POLY that extends from a standard non-body-contacted transistor for a distance of up to 0.400 µ m. For body-contacted devices, gate extension includes that portion of POLY or ACT that serves to form the body contact (as opposed to the channel).

• Flag layer is a logical layer that is used to control verification or autogeneration processing of a layout, but does not directly correspond to the design data for a particular reticle.

• D as a prefix to a rule number denotes a density requirement, applied after generation of fill patterns by MITLL, as described in MITLL Low-Power FDSOI CMOS Process: Application Notes.

• R as a prefix to a number denotes a rule that is recommended but not required.

Active Poly FLGCHANNSD PSD



5.2. Summary


Active Area Layer (ACT, ACTF, ACTXPP)

The ACT layer is generally used to define silicon islands corresponding to MOS active areas, capacitor bottom plates, etc.MITLL will oversize features drawn on ACT by 0.075 µm per side to accommodate the sidewall implant process.This oversized active area will be ORed with ACTF and ACTXPP to produce a single active mask.MITLL will add a sidewall implant where POLY crosses the edge of ACT on a transistor; if this implant is not desired, as in a diode or a native or accumulation transistor, the designer should use ACTXPP instead of ACT.For more information on ACTXPP, see MITLL Low-Power FDSOI CMOS Process: Application Notes.

Rule Value Description

1.01 0.500 µm Minimum ACT width

1.02 0.300 µm Minimum spacing ACT to (ACT or ACTF or ACTXPP)

1.03 0.500 µm Minimum extension of ACT beyond POLY

1.04 Prohibited ACTF interacting with ACT, POLY, or ACTXPP prohibited

1.05 0.450 µm Minimum (ACT and POLY and (CBN or CBP)) spacing

1.06 0.375 µm Minimum (ACT or ACTF or ACTXPP) spacing to (POLY and ACT and (CBN or CBP))

2.01 0.500 µm Minimum ACTF width

2.02 0.300 µm Minimum spacing ACTF to (ACT or ACTF or ACTXPP)

2.03 0.300 µm Minimum spacing ACTF to POLY3.01 0.600 µm Minimum ACTXPP width 3.02 0.300 µm Minimum spacing ACTXPP to (ACT or ACTF or ACTXPP)

D1.01 30% Required minimum active density within any 1 mm x 1 mm window

D1.02 70% Required maximum active density within any 1 mm x 1 mm window

R1.01 Warning Active isolated from CONR3.01 ACTXPP Use of ACTXPP is high risk (not subject to ACT post-submission processing)




n-Channel Body Implant Layer (CBN)


p-Channel Body Implant Layer (CBP)

NMOS transistor active area should receive this p-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.


4.01 0.500 µm Minimum width4.02 0.450 µm Minimum surround of NMOS channel region

4.03 0.250 µm Minimum spacing CBN to CBN4.04 0.300 µm Minimum spacing field CBN to PMOS channel

4.05 0.400 µm Minimum spacing CBN to PMOS channel on common active4.06 Prohibited CBN–CBP overlap on (ACT and POLY)

4.07 0.250 µm Minimum CBN surround on SBC NMOS gate extension that forms the body contact

4.08 0.250 x 1.1 µm Minimum CBN rectangle adjacent to NMOS H-gate arm

PMOS transistor active area should receive this n-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.

Rule Value Description5.01 0.500 µm Minimum width5.02 0.450 µm Minimum surround of PMOS channel region5.03 0.250 µm Minimum spacing CBP to CBP5.04 0.300 µm Minimum spacing field CBP to NMOS channel5.05 0.400 µm Minimum spacing CBP to NMOS channel on common active5.06 Prohibited CBP–CBN overlap on (ACT and POLY)

5.07 0.250 µm Minimum CBP surround on SBC PMOS gate extension that forms the body contact

5.08 0.250 x 1.1 µm Minimum CBP rectangle adjacent to PMOS H-gate arm




p-Type Capacitor Bottom Plate Implant Layer (CAPP)


n-Type Capacitor Bottom Plate Implant Layer (CAPN)

n-Type Capacitor Bottom Plate Implant Layer (CAPLCN)

This is a p+ implant resulting in a doping density of about 5x1018 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with PSD-dopant gates and for high-value resistors with either undoped, floating poly gate or NOSLC.

Rule Value Description6.01 0.500 µm Minimum width6.02 0.250 µm Minimum spacing CAPP to CAPP (if not merged)6.03 0.300 µm Minimum spacing field CAPP to MOS channel6.04 0.400 µm Minimum spacing from intersection of CAPP and active to MOS channel

on common island

This is a n+ implant resulting in a doping density of about 1x1019 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates and for high-value resistors with either undoped, floating poly gate or NOSLC.

Rule Value Description7.01 0.500 µm Minimum width7.02 0.250 µm Minimum spacing CAPN to CAPN (if not merged)7.03 0.300 µm Minimum spacing field CAPN to MOS channel7.04 0.400 µm Minimum spacing from intersection of CAPN and active to MOS channel

on common island


It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description8.01 0.500 µm Minimum width8.02 0.250 µm Minimum spacing CAPLCN to CAPLCN (if not merged)8.03 0.300 µm Minimum spacing field CAPLCN to MOS channel8.04 0.400 µm Minimum spacing from intersection of CAPLCN and active to MOS channel

on common island




Polysilicon Gate Layer (POLY, POLYF)

Phase Shift Poly Layer (POLYPS)

This layer defines poly lines, MOS gates, capacitor top plates, etc.POLY will be ORed with POLYF to produce a single poly mask.The POLYF layer is to be used for fill patterns and labels only.When the 3.3 V flag (FLG33) is present anywhere 9.01a, 9.02a, and 9.05a apply.FLG33 AND FLG50 ARE OPTIONAL FLAGS–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description9.01 0.200 µm Minimum drawn width (will be reduced in fabrication to 0.18 µm)

9.01a 0.350 µm Minimum drawn width when inside FLG339.01b 0.500 µm Minimum drawn width when inside FLG509.02 0.250 µm Minimum spacing

9.02a 0.350 µm Minimum spacing when inside FLG339.02b 0.350 µm Minimum spacing when inside FLG509.03 0.350 µm Minimum spacing over ACT9.04 0.175 µm Minimum field POLY spacing to active area9.05 0.350 µm Minimum field POLY spacing to gate (square metric excludes straight gate extension POLY)

9.06 0.400 µm Minimum extension beyond active area9.07 Prohibited POLY on ACT outside of (NSD or PSD or DEVR)9.08 Prohibited POLYF may not interact with POLY, ACT, or ACTXPP

D9.01 15% Required minimum POLY/POLYF density within 1 mm x 1 mm windowD9.02 35% Required maximum POLY/POLYF density within 1 mm x 1 mm windowR9.01 Warning POLY outside of NSD, PSD, or DEVR not recommendedR9.02 Warning Non-fill POLY with no contacts not recommendedR9.03 0.350 µm Minimum surround by ACT when used as capacitor top plateR9.04 0.300 µm Minimum surround by CAPP, CAPN, or CAPLCN when used as

capacitor top plateR9.05 0.350 µm Minimum spacing (for improved yield)

This is a flag layer used in generation of phase shift masks for defining short poly gates.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description11.01 0.100 µm Drawn line width (only horizontal or vertical rectangles of this width allowed)11.02 0.050 µm Minimum POLY surround of POLYPS11.03 0.200 µm Extension beyond active area (only distance allowed)11.04 Prohibited POLYPS outside of (POLY and ACT) or gate extension poly (Rule 9.05)11.05 Prohibited Non-manhattan geometries prohibited (only straight horizontal or vertical lines

with no intersections allowed)




n+ Implant Layer (NSD)

This layer defines the NMOS source/drain and PMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope POLY. When NSD intersects with NOSDX, the

source/drain extension implant is suppressed and only the post-spacer degenerate implant step is performed. When NSD intersects with NODEG, the degenerate implant is suppressed and only the extension implant is performed.

Rule Value Description12.01 0.500 µm Minimum NSD width12.01a 0.500 µm Minimum width (NSD not NOSDX)12.01b 0.500 µm Minimum width (NSD not NODEG)12.02 0.400 µm Minimum NSD surround on NMOS channel region except in body contact region12.03 0.200 µm Minimum NSD extension beyond active area12.04 0.250 µm Minimum spacing NSD to NSD (if not merged)12.04a 0.250 µm Minimum spacing (NSD not NOSDX) to (NSD not NOSDX)12.04b 0.250 µm Minimum spacing (NSD not NODEG) to (NSD not NODEG)12.05 0.200 µm Minimum spacing field NSD to non-NSD active area12.06 0.400 µm Minimum spacing field NSD to PMOS channel region12.07 0.400 µm Minimum spacing from intersection of non-body contact NSD and active to

PMOS channel on common island12.08a 0.100 µm Minimum NSD overlap on poly gate12.08b 0.150 µm Minimum (NSD not NOSDX) overlap on poly gate (This rule applies to body

contact structures, where the gate receives NSD on one side and PSD on the other.)

12.08c 0.100 µm Minimum spacing outside edge of (NSD and NOSDX) to inside edge of poly gate12.08d 0.150 µm Minimum spacing outside edge of (NSD not NOSDX) to inside edge of poly gate12.09 Prohibited NSD-PSD overlap on ACT or POLY or NOSLC12.10 0.550 µm Minimum NSD surround on n-type capacitor top plate POLY

R12.01 0.150 µm Minimum recommended NSD overlap on poly gate (for improved yield)




p+ Implant Layer (PSD)

This layer defines the PMOS source/drain and NMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope POLY. When PSD intersects with NOSDX, the

source/drain extension implant is suppressed and only the post-spacer degenerate implant step is performed. When PSD intersects with NODEG, the degenerate implant is suppressed and only the extension implant is performed.

Rule Value Description13.01 0.500 µm Minimum PSD width

13.01a 0.500 µm Minimum width (PSD not NOSDX)13.01b 0.500 µm Minimum width (PSD not NODEG)13.02 0.400 µm Minimum PSD surround on NMOS channel region except in body contact region13.03 0.200 µm Minimum PSD extension beyond active area13.04 0.250 µm Minimum spacing PSD to PSD (if not merged)

13.04a 0.250 µm Minimum spacing (PSD not NOSDX) to (PSD not NOSDX)13.04b 0.250 µm Minimum spacing (PSD not NODEG) to (PSD not NODEG)13.05 0.200 µm Minimum spacing field PSD to non-PSD active area13.06 0.400 µm Minimum spacing field PSD to PMOS channel region13.07 0.400 µm Minimum spacing from intersection of non-body contact PSD and active to

PMOS channel on common island13.08a 0.100 µm Minimum PSD overlap on poly gate13.08b 0.150 µm Minimum (PSD not NOSDX) overlap on poly gate (This rule applies to body

contact structures, where the gate receives PSD on one side and NSD on the other.)

13.08c 0.100 µm Minimum spacing outside edge of (PSD and NOSDX) to inside edge of poly gate13.08d 0.150 µm Minimum spacing outside edge of (PSD not NOSDX) to inside edge of poly gate13.10 0.550 µm Minimum PSD surround on n-type capacitor top plate POLY

R13.01 0.150 µm Minimum recommended PSD overlap on POLY gate (for improved yield)




Salicide Protection Layer (NOSLC)


Contact Cut Layer (CON)

This layer defines unsilicided poly and active regions. It blocks both the silicide and the degenerate source/drain implant. It does not block the source/drain extension implants, so NOSDX must be used if extension implant doping is not desired. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description14.01 0.250 µm Minimum width14.02 0.400 µm Minimum spacing14.03 0.200 µm Minimum spacing to unrelated POLY or ACT14.04 0.400 µm Minimum spacing to POLY on related ACT14.05 0.200 µm Minimum extension beyond ACT or POLY14.06 0.275 µm Minimum spacing NOSLC to CON14.07 0.300 µm Minimum spacing NOSLC to TGSRF14.08 0.250 µm2 Minimum area of NOSLC14.09 0.100 µm Minimum overlap of NOSLC on POLY14.10 0.250 µm Minimum width of (MOS channel region interacting with NOSLC) not NOSLC14.11a 0.225 µm Minimum width (NSD and NOSLC)14.11b 0.225 µm Minimum width (PSD and NOSLC)14.12a 0.225 µm Minimum width (NOSLC not NSD)14.12b 0.225 µm Minimum width (NOSLC not PSD)14.13a 0.225 µm Minimum spacing outside edge of NSD to inside edge of NOSLC14.13b 0.225 µm Minimum spacing outside edge of PSD to inside edge of NOSLC

Use this layer to define contact cuts to the active and poly areas.

Rule Value Description15.01 0.250 x 0.250 µm Contact size (only size and shape allowed)15.02 0.350 µm Minimum spacing

15.02a 0.500 µm Minimum spacing for 5 to 24 closely placed CON15.02b 0.750 µm Minimum spacing for 25 or more closely placed CON15.03 0.175 µm Minimum ACT surround if contacting to ACT15.04 0.175 µm Minimum POLY surround if contacting to POLY15.05 0.275 µm Minimum spacing to POLY gate

15.05a 0.350 µm Minimum spacing to POLY gate inside FLG3315.05b 0.350 µm Minimum spacing to POLY gate inside FLG5015.06 0.175 µm Minimum (ACT and POLY) surround if contacting to POLY over ACT15.07 0.175 µm Minimum NSD OR PSD surround15.08 Prohibited CON not over POLY or ACT

R15.01 0.125 µm Minimum recommended exclusive NSD or PSD surroundNote: In this figure the region receiving NSD also illustrates the case where PSD is used.



RF07; QDS1; 3DM2-T3

Low Resistance Tungsten Gate Shunt for RF Devices (TGSRF)

Use this layer to define low gate series resistance RF T-gates. TGSRF will connect to any intersecting M1 features.Metal 1 must be placed over all TGSRF features. It is permissible for this metal 1 to have its edges coincident with TGSRF, though providing metal 1 extension up to 0.150 µ m may reduce risk.

Rule Value Description16.01 0.250 µm TGSRF contact trench width (only size allowed)16.02 0.350 µm Minimum spacing16.03 0.350 µm Minimum spacing TGSRF to CON16.04 0.025 µm Maximum extension of TGSRF beyond POLY16.05 0.175 µm Minimum NSD OR PSD surround16.06 Prohibited TGSRF outside metal 1 prohibited16.07 Required CON should be provided to POLY even if TGSRF also provides metal

connection to POLYNote: In this figure the region receiving NSD also illustrates the case where PSD is used. Metal 1 would be placed in the same location as the drawn TGSRF features. The required NSD surround on the channel region (Rule 12.02) is not included.




Metal 1 Layer (M1, M1F)MSC2; 3DL1

MSC2; 3DL1; 3DM2


Metal 1/Metal 2 Via Layer (V12)

This layer defines the first metal level.The M1 layer will be ORed with M1F to produce a single metal 1 mask.The M1F layer is to be used for fill patterns and labels only.Note: Also see Metal Z (MZ, MZF) Rule 36.xx.

Rule Value Description17.01 0.250 µm Minimum width17.02 0.300 µm Minimum spacing17.03 0.025 µm Minimum surround on contact cut17.04 0.150 µm Minimum line extension beyond contact cut (constraint must be met in at least

two opposite directions)17.05 Required Metal 1 over all TGSRF17.06 Prohibited Metal 1 interacting with M1F not allowed

D17.01 30% Required minimum metal 1 density within any 1 mm x 1 mm windowD17.02a 80% Required maximum metal 1 density within any 1 mm x 1 mm window

D17.02b 50% Required maximum metal 1 density within any 1 mm x 1 mm window when 3D integration is to be performed

R17.01 0.150 µm Minimum recommended surround on contact cut for improved contact resistance control

R17.02 0.300 µm2 Minimum recommended M1 areaR17.03 0.350 µm Minimum recommended M1 spacing for improved yieldR17.04 0.400 µm Minimum spacing if both metal line widths are >1.5 µ m wideR17.05 0.600 µm Minimum spacing if at least one metal line width is >5.0 µ m wideR17.06 1.000 µm Minimum spacing if at least one metal line width is >10.0 µ m wide

This layer defines vias between the first and second metal levels.

Rule Value Description19.01 0.300 x 0.300 µm Via size (only size and shape allowed)19.02 0.400 µm Minimum spacing19.02a 0.500 µm Minimum spacing for 5 to 24 closely placed V1219.02b 0.750 µm Minimum spacing for 25 or more closely placed V1219.03 0.025 µm Minimum metal 1 surround19.04 0.150 µm Minimum metal 1 line extension beyond V12 (constraint must be met in at least

two opposite directions)19.05 Allowed Stacked via V12 on contact (metal 1 must be present)19.06 Allowed Stacked via V12 on TGSRF (metal 1 must be present)

R19.01 0.150 µm Minimum recommended metal 1 surround on V12 for improved via resistance control




Metal 2 Layer (M2, M2F)

MSC2; 3DL1; 3DM2



This layer defines the second metal level.The M2 layer will be ORed with M2F to produce a single metal 2 mask.The M2F layer is to be used for fill patterns and labels only.

Rule Value Description20.01 0.250 µm Minimum width20.02 0.300 µm Minimum spacing20.03 0.025 µm Minimum surround on V1220.04 0.150 µm Minimum metal 2 line extension beyond V12 (constraint must be met in at least

two opposite directions)20.05 Prohibited Metal 2 interacting with M2F not allowed




R20.02 0.300 µm2 Minimum recommended metal 2 areaR20.03 0.350 µm Minimum recommended metal 2 spacing for improved yieldR20.04 0.400 µm Minimum spacing if both metal line widths are >1.5 µ m wideR20.05 0.600 µm Minimum spacing if at least one metal line width is >5.0 µ m wideR20.06 1.000 µm Minimum spacing if at least one metal line width is >10.0 µ m wide

This layer defines vias between the second and third metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


two opposite directions)22.05 Allowed Stacked via V23 on V12 (intervening metals must be present)






MSC2; 3DL1; 3DM2

YES2; MIM1 Metal 3/Metal 4 Via Layer (V34)

This layer defines the third metal level.The M3 layer will be ORed with M3F to produce a single metal 3 mask.The M3F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description23.01 0.250 µm Minimum width23.02 0.300 µm Minimum spacing23.03 0.025 µm Minimum surround on via V2323.04 0.150 µm Minimum metal 3 line extension beyond V23 (constraint must be met in at least






This layer defines vias between the third and fourth metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


two opposite directions)25.05 Allowed Stacked via V34 on V23 (metal 1 must be present)




MIM1 Metal 4 Layer (M4, M4F)


This layer defines the fourth metal level.The M4 layer will be ORed with M4F to produce a single metal 4 mask.The M4F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS



D26.01 30% Required minimum metal 4 density within any 1 mm x 1 mm windowD26.02a 80% Required maximum metal 4 density within any 1 mm x 1 mm windowD26.02b 50% Required maximum metal 4 density within any 1 mm x 1 mm window

when 3D integration is to be performedR26.01 0.150 µm Minimum recommended metal 4 surround on V34 for improved via resistance

controlR26.02 0.300 µm2 Minimum recommended metal 4 areaR26.03 0.350 µm Minimum recommended metal 4 spacing for improved yieldR26.04 0.400 µm Minimum spacing if both metal line widths are >1.5 µ m wideR26.05 0.600 µm Minimum spacing if at least one metal line width is >5.0 µ m wideR26.06 1.000 µm Minimum spacing if at least one metal line width is >10.0 µ m wide

This layer defines vias between the fourth and fifth metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS







RF07; QDS1 Top-Level RF Metal Via Layer (VTLRF)

This layer defines the fifth metal level.The M5 layer will be ORed with M5F to produce a single metal 5 mask.The M5F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS






This layer defines vias between the top-level RF metal level and the highest-level interconnect metal level below.For example, if the process includes three metal levels, and the third metal level corresponds to MTLRF, then VTLRF defines vias between MTLRF and M2.The rules for this layer are determined by the thickness of the ILD through which the via is formed.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description31.01 0.450 x 0.450 µm Via size (only size and shape allowed)31.02 0.550 µm Minimum spacing 31.02a 0.950 µm Minimum spacing for 5 or more closely placed VTLRF31.03 0.150 µm Minimum surround by lower level metal31.04 Allowed Stacked via VTLRF on prior via (underlying metal must be present)



YES2; RF07; QDS1

Top-Level RF Metal Layer (MTLRF, MTLRFF)


Overglass Pad Cut Layer (OGC)

MSC2; 3DL1; 3DM2

This layer defines a top-level metal layer optimized for RF design.The MTLRF layer will be ORed with MTLRFF to produce a single RF metal mask.The MTLRFF layer is to be used for fill patterns and labels only.The rules for this layer are determined by the thickness of the metal.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description32.01 1.000 µm Minimum width (wmin)32.02 1.000 µm Minimum spacing (dmin)32.03 0.250 µm Minimum surround on via VTLRF32.04 Prohibited MTLRF interacting with MTLRFF not allowed

D32.01 30% Required minimum metal MTLRF density within any 1 mm x 1 mm windowD32.02a 80% Required maximum metal MTLRF density within any 1 mm x 1 mm windowD32.02b 50% Required maximum metal MTLRF density within any 1 mm x 1 mm window

when 3D integration is to be performed

This layer defines pad cuts in the overglass, which allow top-level metal pads to be contacted.

Rule Value Description34.01 1.000 µm Spacing in from top-level metal pad edge34.02 Prohibited OGC not over top-level metal34.03 5.000 µm Minimum width34.04 5.000 µm Minimum spacing34.05 1.000 µm Spacing in from metal Z edge if metal Z is used

R34.01 Warning OGC should not be used on the separate tiers of a 3D circuit unless prior arrangements have been made with MITLL for access to unbonded wafers; use 3DOGC instead.



Metal Z Layer, Alternative Single Metal (MZ, MZF)

YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Anodized Aluminum Version

This layer defines an alternative single metal layer to allow testing without multiple metal layer processing.MZ is an alternative to, not a part of, the normal metal/via stack. (M1 is still required for normal wafer processing.) If used, MZ must satisify all M1 rules and surround OGC by 1.000 µm.See “Antenna Effects and the Metal Z Layer” in MIT Low-Power FDSOI CMOS Process: Application Notes.

OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description36.01 0.250 µm Minimum width36.02 0.350 µm Minimum spacing36.03 0.150 µm Minimum surround on contact cut36.04 Required MZ over all TGSRF36.05 Prohibited MZ interacting with MZF not allowed

D36.01 30% Required minimum metal Z density within any 1 mm x 1 mm windowD36.02 50% Required maximum metal Z density within any 1 mm x 1 mm window

For process versions that include anodized aluminum capacitors, the MIMCAP layer defines the top plate metal version. The alumina etch mask is automatically generated by oversizing the drawn MIMCAP features.The top plate is contacted by a via up to the top-level metal; for a process with four digital metal levels, this top-level via is V34 and the bottom plate metal level is M3.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionAOC153.01 2.000 µm Minimum MIMCAP widthAOC153.02 2.000 µm Minimum MIMCAP spacingAOC153.03 0.500 µm Minimum MIMCAP surround on top-level viaAOC153.04 0.800 µm Minimum MIMCAP spacing to top-level via (where top-level via does not

connect to the MIMCAP top plate)AOC153.05 1.000 µm Bottom plate metal surround on MIMCAP



YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version

YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version with Wet Etch

For process versions that include deposited oxide MIM capacitors, the MIMCAP layer defines the ILD oxide etch region. The top plate is formed by the top-level metal; for a process with four digital metal levels, the bottom plate metal level is M3 and the top plate metal is M4.The top-level vias must be isolated from MIMCAP regions. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionDOC153.01 2.000 µm Minimum MIMCAP widthDOC153.02 2.000 µm Minimum MIMCAP spacingDOC153.03 1.000 µm Minimum MIMCAP spacing to top-level viaDOC153.04 0.500 µm Top plate metal surround on MIMCAPDOC153.05 0.500 µm Bottom plate metal surround on MIMCAPDOC153.06 0.500 µm Minimum top-level metal width within 1 µ m of MIMCAP

For process versions that include deposited oxide MIM capacitors, the MIMCAP layer defines the ILD oxide etch region. The top plate is formed by the top-level metal; for a process with four digital metal levels, the bottom plate metal level is M3 and the top plate metal is M4.The top-level vias must be isolated from MIMCAP regions. These rules have been adjusted to allow the etch region to grow by 1.5 µm on each side during the wet etch.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionWDOC153.01 2.000 µm Minimum MIMCAP widthWDOC153.02 5.000 µm Minimum MIMCAP spacingWDOC153.03 2.500 µm Minimum MIMCAP spacing to top-level viaWDOC153.04 2.000 µm Top plate metal surround on MIMCAPWDOC153.05 2.000 µm Bottom plate metal surround on MIMCAPWDOC153.06 0.500 µm Minimum top-level metal width within 1 µ m of MIMCAP



MSC2; 3DL1; 3DM2

3D Via Cut to Another Wafer Tier (3DCUT)

3DCUT defines 3D via cuts to another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier. The 3D via originates on the back side of the cut tier. Its dimensions on the lower numbered tier are defined by a "doughnut" opening in the cut tier's highest level metal (required).Rules assume three metal levels per tier and cuts originate from BOX side of tier.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description41.01 1.750 x 1.750 µm 3DCUT size (only size and shape allowed)41.02 1.450 µm Minimum spacing 3DCUT to 3DCUT on the same tier

41.02a 3.750 µm Minimum spacing for 5 to 24 closely placed 3DCUT on the same tier41.02b 5.800 µm Minimum spacing for 25 or more closely placed 3DCUT on the same tier41.03 0.625 µm Minimum top-level metal extension beyond 3DCUT41.04 1.500 x 1.500 µm Top-level metal doughnut opening size (only size and shape allowed)41.05 0.125 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)41.06 Prohibited 3DCUT outside of BM1 (when BM1 is available)

41.07a 1.175 µm Minimum spacing 3DCUT to active on the same tier 41.07b 1.150 µm Minimum spacing 3DCUT to POLY/POLYF on the same tier41.07c 1.125 µm Minimum spacing 3DCUT to M1/M1F on the same tier41.07d 1.150 µm Minimum spacing 3DCUT to V12 on the same tier41.07e 1.075 µm Minimum spacing 3DCUT to M2/M2F on the same tier41.07f 1.100 µm Minimum spacing 3DCUT to V23 on the same tier41.08a 0.500 µm Minimum top-level metal width for wire connecting to top-level metal doughnut41.08b 0.350 µm Minimum top-level metal length at Rule 41.08a width for connecting to

top-level metal doughnut41.09 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier41.10 Prohibited 3DCUT without top-level metal doughnut



MSC2; 3DL1; 3DM2

3D Via Landing from Another Wafer Tier (3DLAND)

MSC2; 3DL1; 3DM2

Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP)

3D Back Side Cut Through Buried Oxide (3DBOXC)

3DLAND defines 3D via landings from another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier.The 3D via penetrates the "land" wafer from the back side and stops on the first metal layer unless 3DFLIP is present on the landing tier.The presence of 3DFLIP anywhere on the tier's layout indicates that when assembled with other tiers it will be flipped with the 3D via stopping on the top-level metal (not reaching POLY or ACT).OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description42.01 1.750 x 1.750 µm 3DLAND size (only size and shape allowed)42.02a 0.625 µm Minimum metal surround of 3DLAND back side metal if present; otherwise

first-level metal without 3DFLIP, top-level metal with 3DFLIP42.02b Prohibited 3DLAND outside of metal landing back side metal if present; otherwise,

first metal without 3DFLIP, top-level metal with 3DFLIP42.03 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier42.04a 1.350 µm Minimum space 3DLAND to active on non-3DFLIP tier when back side metal

is not used42.04b 1.250 µm Minimum space 3DLAND to POLY/POLYF on non-3DFLIP tier when back side

metal is not used

This is a flag layer that is used to indicate that during 3D assembly, a particular tier is flipped with respect to the final 3D stack.Tiers requiring 3DFLIP flags shall be determined by MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description44.01 Prohibited 3DCUT on a 3DFLIP tier

3DBOXC defines a cut made through the buried oxide under the silicon of a wafer tier that has been integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description45.xx No rules available



3D Back Side Metal Gate (3DBMG)

MSC2; 3DL1; 3DM2

Pad Cut for Final 3D Stack (3DOGC)

Common Landing Metal Flag (3DCNX)

3DBMG defines a metal gate formed on the back side of a wafer tier that is integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


3DOGC defines pad cuts for the final assembled 3D stack.Opens back side pad cuts to tier 3 back side metal if present; otherwise, to tier 3 front side metal 1Note that active and poly fill features are allowed under 3DOGC. It is important, however, to ensure that these are isolated from circuit features. Rules 47.02 and 47.03 do not prohibit ACTF and POLYF from being under 3DOGC. However, fill features must be isolated from circuit features per rules 1.05 and 9.10. Rules 47.02 and 47.03 do not apply if 3DOGC opens to back side metal.If overglass cuts to heat sink structures are desired, the same rules apply as for bondpads. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description47.01 1.0 µm Required minimum pad metal surround on 3DOGC47.02 6.650 µm 3DOGC spacing to POLY if back side metal is not used47.03 6.750 µm 3DOGC spacing to ACT if back side metal is not used47.04 5.000 µm 3DOGC minimum width47.05 5.000 µm 3DOGC minimum spacing

This flag layer indicates that particular 3DCUT features share a common landing pad.Should be drawn in a manner that is representative of the common landing metal.This flag suppresses enforcement of Rule 41.03.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS



3DM2-T2; 3DM2-T3

Back Side Metal 1/Front Side Metal 1 Via Layer (BVIA0)

3DM2-T2 Back Side Metal 1 Layer (BM1)

3DM2-T3 RF Back Side Metal 1 Layer (BM1)

This layer defines vias between the first front side metal and first back side metal.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description62.01 0.450 x 0.450 µm Size (only size and shape allowed)62.02 0.550 µm Minimum spacing

62.02a 3.750 µm Minimum spacing for 5 to 24 closely placed BVIA062.02b 5.800 µm Minimum spacing for 25 or more closely placed BVIA062.03 0.300 µm Minimum front side metal 1 surround62.04 0.400 µm Minimum BVIA0 spacing to POLY/POLYF62.05 0.350 µm Minimum BVIA0 spacing to active

This layer defines the first back side metal level.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description63.01 0.500 µm Minimum width63.02 0.500 µm Minimum spacing63.03 0.875 µm Minimum surround on 3DCUT63.04 0.150 µm Minimum surround on BVIA0

D63.01 30% Required minimum back side metal 1 density within any 1 mm x 1 mm windowD63.02 50% Required maximum back side metal 1 density within any 1 mm x 1 mm window


Rule Value DescriptionRF63.01 1.000 µm Minimum widthRF63.02 1.000 µm Minimum spacingRF63.03 0.625 µm Minimum surround on 3DCUTRF63.04 0.150 µm Minimum surround on BVIA0

RFD63.01 30% Required minimum back side metal 1 density within any 1 mm x 1 mm windowRFD63.02 80% Required maximum back side metal 1 density within any 1 mm x 1 mm window



Overglass Cut to Back Side Metal 1 (BOGC1)

Back Side Metal 2/Back Side Metal 1 Via Layer (BVIA1)

Back Side Metal 2 Layer (BM2)


This layer defines overglass cuts to back side metal 1.If back side metal 2 (BM2) is also used, BOGC1 will only be used to access circuits prior to BM2 if this is needed for testing. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description64.01 1.000 µm Minimum back side metal 1 surround on BOGC164.02 5.000 µm Minimum width64.03 5.000 µm Minimum spacing

This layer defines vias between the second and first back side metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description65.01 0.500 x 0.500 µm Width (only size and shape allowed)65.02 0.400 µm Minimum spacing

65.02a 0.500 µm Minimum spacing for 5 to 24 closely placed BVIA165.02b 0.750 µm Minimum spacing for 25 or more closely placed BVIA165.03 0.500 µm Minimum back side metal 1 surround

This layer defines the second back side metal level.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description66.01 2.000 µm Minimum width66.02 2.000 µm Minimum spacing66.03 0.500 µm Minimum back side metal 2 surround on via BVIA1


This layer defines overglass cuts to back side metal 2.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS




Additional Layers: Flag and Comment (Markup)


NOFILL

Channel Flag Region (FLGCHAN)

Voltage Flag Layers (FLG33, FLG50)


DEVR


DEVL


DEV-MC

(Comment layers are included as a design aid and have no effect on the layout other than the cell extents.)

This layer suppresses automatic fill generation. In regions not covered by NOFILL, fill structures are automatically generated by MITLL to force compliance with layer density rules.See MITLL Low-Power FDSOI CMOS Process: Application Notes.

Warning: When NOFILL is used the designer takes responsiblity for all layer density specifications in that region of use. Designs that use NOFILL must meet all density constraints after application of the automatic fill generation routine.

This layer indicates the channel region of nonsimple devices.For body-contacted devices, this should be drawn coincident with POLY, excluding the body contact gate extension POLY.

Rule Value Description80.01 Prohibited FLGCHAN and NOSDX

FLG33 and FLG50 are used to indicate 3.3-V and 5.0-V devices, respectively. Devices not enclosed by FLG33 or FLG50 will have the engineering for the default maximum supply rail voltage for the particular run, usually 1.5 V.Note that implant features drawn crossing voltage regions are split at the voltage boundary to form multiple masks and therefore must meet minimum width requirements within each voltage region. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description85.01 Prohibited Overlapping voltage regions prohibited85.02 0.400 µm Minimum exclusive 1.5-V-only region surrounding 1.5-V gate86.02 0.400 µm Minimum exclusive 3.3-V-only region surrounding 3.3-V gate87.02 0.400 µm Minimum exclusive 5.0-V-only region surrounding 5.0-V gate

Indicates device is resistor for verification and simulation

Indicates device is inductor for verification and simulation

Indicates device is metal 1/metal 2 capacitor for verification and simulation




DEVD

NOSLOT


Red, Green, Blue, Yellow

Indicates device is lateral diode for verification and simulation

Reserved for future use

Comment layers




Active Area Layer (ACT, ACTF, ACTXPP)

See illustrations on next page.

The ACT layer is generally used to define silicon islands corresponding to MOS active areas, capacitor bottom plates, etc.MITLL will oversize features drawn on ACT by 0.075 µm per side to accommodate the sidewall implant process.This oversized active area will be ORed with ACTF and ACTXPP to produce a single active mask.MITLL will add a sidewall implant where POLY crosses the edge of ACT on a transistor; if this implant is not desired, as in a diode or a native or accumulation transistor, the designer should use ACTXPP instead of ACT.For more information on ACTXPP, see MITLL Low-Power FDSOI CMOS Process: Application Notes.


1.01 0.500 µm Minimum ACT width

1.02 0.300 µm Minimum spacing ACT to (ACT or ACTF or ACTXPP)

1.03 0.500 µm Minimum extension of ACT beyond POLY

1.04 Prohibited ACTF interacting with ACT, POLY, or ACTXPP prohibited

1.05 0.450 µm Minimum (ACT and POLY and (CBN or CBP)) spacing

1.06 0.375 µm Minimum (ACT or ACTF or ACTXPP) spacing to (POLY and ACT and (CBN or CBP))

2.01 0.500 µm Minimum ACTF width

2.02 0.300 µm Minimum spacing ACTF to (ACT or ACTF or ACTXPP)

2.03 0.300 µm Minimum spacing ACTF to POLY3.01 0.600 µm Minimum ACTXPP width 3.02 0.300 µm Minimum spacing ACTXPP to (ACT or ACTF or ACTXPP)

D1.01 30% Required minimum active density within any 1 mm x 1 mm window

D1.02 70% Required maximum active density within any 1 mm x 1 mm window

R1.01 Warning Active isolated from CONR3.01 ACTXPP Use of ACTXPP is high risk (not subject to ACT post-submission processing)



Active Area Layer (ACT, ACTF, ACTXPP) (Continued)

RULE 1.01

(0.500 µm)

RULE 1.02

(0.300 µm)

RULE 1.03

(0.500 µm)

Same spacing:

NMOS-to-NMOS

PMOS-to-PMOS

NMOS-to-PMOS

Poly Active Contact Cut




n-Channel Body Implant Layer (CBN)

NMOS transistor active area should receive this p-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.


4.01 0.500 µm Minimum width4.02 0.450 µm Minimum surround of NMOS channel region

4.03 0.250 µm Minimum spacing CBN to CBN4.04 0.300 µm Minimum spacing field CBN to PMOS channel

4.05 0.400 µm Minimum spacing CBN to PMOS channel on common active4.06 Prohibited CBN–CBP overlap on (ACT and POLY)

4.07 0.250 µm Minimum CBN surround on SBC NMOS gate extension that forms the body contact

4.08 0.250 x 1.1 µm Minimum CBN rectangle adjacent to NMOS H-gate arm

RULE 4.02

(0.450 µm)

RULE 4.03

(If <0.250 µm,

merge features)RULE 4.04

(0.300 µm)

RULE 4.05

(0.400 µm)

RULE 4.01

(0.500 µm)

RULE 4.08

(0.250 x 1.1 µm)

Active CBN Poly Contact Cut

PMOS




p-Channel Body Implant Layer (CBP)

PMOS transistor active area should receive this n-type implant.Autogeneration routines used in mask generation assume NMOS transistors have CBN and PMOS transistors have CBP.For deviations from that such as native or accumulation transistors see MITLL Low-Power FDSOI CMOS Process: Application Notes.

Rule Value Description5.01 0.500 µm Minimum width5.02 0.450 µm Minimum surround of PMOS channel region5.03 0.250 µm Minimum spacing CBP to CBP5.04 0.300 µm Minimum spacing field CBP to NMOS channel5.05 0.400 µm Minimum spacing CBP to NMOS channel on common active5.06 Prohibited CBP–CBN overlap on (ACT and POLY)

5.07 0.250 µm Minimum CBP surround on SBC PMOS gate extension that forms the body contact

5.08 0.250 x 1.1 µm Minimum CBP rectangle adjacent to PMOS H-gate arm

Active CBP Poly Contact Cut

RULE 5.02

(0.450 µm)

RULE 5.03

(If <0.250 µm,

merge features)RULE 5.04

(0.300 µm)

RULE 5.05

(0.400 µm)

RULE 5.01

(0.500 µm)

NMOS

RULE 5.08

(0.250 x 1.1 µm)




p-Type Capacitor Bottom Plate Implant Layer (CAPP)

This is a p+ implant resulting in a doping density of about 5x1018 cm-3.

It is suitable for forming low-voltage-coefficient capacitor bottom plates with PSD-dopant gates and for high-value resistors with either undoped, floating poly gate or NOSLC.

Rule Value Description6.01 0.500 µm Minimum width6.02 0.250 µm Minimum spacing CAPP to CAPP (if not merged)6.03 0.300 µm Minimum spacing field CAPP to MOS channel6.04 0.400 µm Minimum spacing from intersection of CAPP and active to MOS channel

on common island

PolyActive Contact Cut

CAPP

RULE 6.01

(0.500 µm)

RULE 6.03

(0.300 µm)

RULE 6.02

(If <0.250 µm,

merge features)

MOS

MO

S

RULE 6.04

(0.400 µm)




n-Type Capacitor Bottom Plate Implant Layer (CAPN)


It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates and for high-value resistors with either undoped, floating poly gate or NOSLC.

Rule Value Description7.01 0.500 µm Minimum width7.02 0.250 µm Minimum spacing CAPN to CAPN (if not merged)7.03 0.300 µm Minimum spacing field CAPN to MOS channel7.04 0.400 µm Minimum spacing from intersection of CAPN and active to MOS channel

on common island


CAPN

RULE 7.01

(0.500 µm)

RULE 7.03

(0.300 µm)

RULE 7.02

(If <0.250 µm,

merge features)

MOS

MO

S

RULE 7.04

(0.400 µm)



n-Type Capacitor Bottom Plate Implant Layer (CAPLCN)


It is suitable for forming low-voltage-coefficient capacitor bottom plates with NSD-dopant gates.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description8.01 0.500 µm Minimum width8.02 0.250 µm Minimum spacing CAPLCN to CAPLCN (if not merged)8.03 0.300 µm Minimum spacing field CAPLCN to MOS channel8.04 0.400 µm Minimum spacing from intersection of CAPLCN and active to MOS channel

on common island


CAPLCN

RULE 8.01

(0.500 µm)

RULE 8.02

(If <0.250 µm,

merge features)

MOS

MO

S

RULE 8.04

(0.400 µm)




Polysilicon Gate Layer (POLY, POLYF)


This layer defines poly lines, MOS gates, capacitor top plates, etc.POLY will be ORed with POLYF to produce a single poly mask.The POLYF layer is to be used for fill patterns and labels only.When the 3.3 V flag (FLG33) is present anywhere 9.01a, 9.02a, and 9.05a apply.FLG33 AND FLG50 ARE OPTIONAL FLAGS–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description9.01 0.200 µm Minimum drawn width (will be reduced in fabrication to 0.18 µm)9.01a 0.350 µm Minimum drawn width when inside FLG339.01b 0.500 µm Minimum drawn width when inside FLG509.02 0.250 µm Minimum spacing9.02a 0.350 µm Minimum spacing when inside FLG339.02b 0.350 µm Minimum spacing when inside FLG509.03 0.350 µm Minimum spacing over ACT9.04 0.175 µm Minimum field POLY spacing to active area9.05 0.350 µm Minimum field POLY spacing to gate (square metric excludes straight gate extension POLY)

9.06 0.400 µm Minimum extension beyond active area9.07 Prohibited POLY on ACT outside of (NSD or PSD or DEVR)9.08 Prohibited POLYF may not interact with POLY, ACT, or ACTXPP

D9.01 15% Required minimum POLY/POLYF density within 1 mm x 1 mm windowD9.02 35% Required maximum POLY/POLYF density within 1 mm x 1 mm windowR9.01 Warning POLY outside of NSD, PSD, or DEVR not recommendedR9.02 Warning Non-fill POLY with no contacts not recommendedR9.03 0.350 µm Minimum surround by ACT when used as capacitor top plateR9.04 0.300 µm Minimum surround by CAPP, CAPN, or CAPLCN when used as

capacitor top plateR9.05 0.350 µm Minimum spacing (for improved yield)



Polysilicon Gate Layer (POLY, POLYF) (Continued)

Contact Cut

Active Poly

RULE 9.02

(0.250 µm)

RULE 9.04

(0.175 µm)

RULE 9.06

(0.400 µm)

RULE 9.03

(0.350 µm)RULE 9.01

(0.200 µm)

RULE 9.04

(0.175 µm)

0.4 µm Surround of Channel Region–Gate Extension Connects to Channel

Inside This Region

RULE 9.05

(0.350 µm)

Contact Cut

Poly

Active

CAPPor CAPN

or CAPLCN

RULE R9.04

(0.300 µm)

RULE R9.03

(0.350 µm)



Phase Shift Poly Layer (POLYPS)

This is a flag layer used in generation of phase shift masks for defining short poly gates.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description11.01 0.100 µm Drawn line width (only horizontal or vertical rectangles of this width allowed)11.02 0.050 µm Minimum POLY surround of POLYPS11.03 0.200 µm Extension beyond active area (only distance allowed)11.04 Prohibited POLYPS outside of (POLY and ACT) or gate extension poly (Rule 9.05)11.05 Prohibited Non-manhattan geometries prohibited (only straight horizontal or vertical lines

with no intersections allowed)

Active Poly Contact Cut

PhaseShiftPoly

RULE 11.01

(0.100 µm)

RULE 11.02

(0.050 µm)

RULE 11.03

(0.200 µm)




n+ Implant Layer (NSD)


This layer defines the NMOS source/drain and PMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope POLY. When NSD intersects with NOSDX, the

source/drain extension implant is suppressed and only the post-spacer degenerate implant step is performed. When NSD intersects with NODEG, the degenerate implant is suppressed and only the extension implant is performed.

Rule Value Description12.01 0.500 µm Minimum NSD width12.01a 0.500 µm Minimum width (NSD not NOSDX)12.01b 0.500 µm Minimum width (NSD not NODEG)12.02 0.400 µm Minimum NSD surround on NMOS channel region except in body contact region12.03 0.200 µm Minimum NSD extension beyond active area12.04 0.250 µm Minimum spacing NSD to NSD (if not merged)12.04a 0.250 µm Minimum spacing (NSD not NOSDX) to (NSD not NOSDX)12.04b 0.250 µm Minimum spacing (NSD not NODEG) to (NSD not NODEG)12.05 0.200 µm Minimum spacing field NSD to non-NSD active area12.06 0.400 µm Minimum spacing field NSD to PMOS channel region12.07 0.400 µm Minimum spacing from intersection of non-body contact NSD and active to

PMOS channel on common island12.08a 0.100 µm Minimum NSD overlap on poly gate12.08b 0.150 µm Minimum (NSD not NOSDX) overlap on poly gate (This rule applies to body

contact structures, where the gate receives NSD on one side and PSD on the other.)

12.08c 0.100 µm Minimum spacing outside edge of (NSD and NOSDX) to inside edge of poly gate12.08d 0.150 µm Minimum spacing outside edge of (NSD not NOSDX) to inside edge of poly gate12.09 Prohibited NSD-PSD overlap on ACT or POLY or NOSLC12.10 0.550 µm Minimum NSD surround on n-type capacitor top plate POLY

R12.01 0.150 µm Minimum recommended NSD overlap on poly gate (for improved yield)



n+ Implant Layer (NSD) (Continued)

Poly Contact Cut

NSD

RULE 12.02

(0.400 µm)

RULE 12.03

(0.200 µm)

RULE 12.01

(0.500 µm)

RULE 12.05

(0.200 µm)

RULE 12.08a

(0.100 µm)

PMOS

PMOS

NMOS

Active

RULE 12.04

(If <0.250 µm,

merge features)

Poly Contact Cut

NSD Active

RULE 12.07

(0.400 µm)

RULE 12.06

(0.400 µm)

RULE 12.10

(0.550 µm)

Capacitor

PMOS




p+ Implant Layer (PSD)


This layer defines the PMOS source/drain and NMOS body contact implant.Use this layer for n+ degenerate doping to form ohmic contacts and to dope POLY. When PSD intersects with NOSDX, the

source/drain extension implant is suppressed and only the post-spacer degenerate implant step is performed. When PSD intersects with NODEG, the degenerate implant is suppressed and only the extension implant is performed.

Rule Value Description13.01 0.500 µm Minimum PSD width

13.01a 0.500 µm Minimum width (PSD not NOSDX)13.01b 0.500 µm Minimum width (PSD not NODEG)13.02 0.400 µm Minimum PSD surround on NMOS channel region except in body contact region13.03 0.200 µm Minimum PSD extension beyond active area13.04 0.250 µm Minimum spacing PSD to PSD (if not merged)

13.04a 0.250 µm Minimum spacing (PSD not NOSDX) to (PSD not NOSDX)13.04b 0.250 µm Minimum spacing (PSD not NODEG) to (PSD not NODEG)13.05 0.200 µm Minimum spacing field PSD to non-PSD active area13.06 0.400 µm Minimum spacing field PSD to PMOS channel region13.07 0.400 µm Minimum spacing from intersection of non-body contact PSD and active to

PMOS channel on common island13.08a 0.100 µm Minimum PSD overlap on poly gate13.08b 0.150 µm Minimum (PSD not NOSDX) overlap on poly gate (This rule applies to body

contact structures, where the gate receives PSD on one side and NSD on the other.)

13.08c 0.100 µm Minimum spacing outside edge of (PSD and NOSDX) to inside edge of poly gate13.08d 0.150 µm Minimum spacing outside edge of (PSD not NOSDX) to inside edge of poly gate13.10 0.550 µm Minimum PSD surround on n-type capacitor top plate POLY

R13.01 0.150 µm Minimum recommended PSD overlap on POLY gate (for improved yield)



p+ Implant Layer (PSD) (Continued)

Poly Contact Cut

PSD

RULE 13.02

(0.400 µm)

RULE 13.03

(0.200 µm)

RULE 13.01

(0.500 µm)

RULE 13.05

(0.200 µm)

RULE 13.08a

(0.100 µm)

NMOS

NMOS

PMOS

Active

RULE 13.04

(If <0.250 µm,

merge features)

Poly Contact Cut

PSD Active

RULE 13.07

(0.400 µm)

RULE 13.06

(0.400 µm)

RULE 13.10

(0.550 µm)

Capacitor

NMOS




Salicide Protection Layer (NOSLC)

See illustration on next page.

This layer defines unsilicided poly and active regions. It blocks both the silicide and the degenerate source/drain implant. It does not block the source/drain extension implants, so NOSDX must be used if extension implant doping is not desired. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description14.01 0.250 µm Minimum width14.02 0.400 µm Minimum spacing14.03 0.200 µm Minimum spacing to unrelated POLY or ACT14.04 0.400 µm Minimum spacing to POLY on related ACT14.05 0.200 µm Minimum extension beyond ACT or POLY14.06 0.275 µm Minimum spacing NOSLC to CON14.07 0.300 µm Minimum spacing NOSLC to TGSRF14.08 0.250 µm2 Minimum area of NOSLC14.09 0.100 µm Minimum overlap of NOSLC on POLY14.10 0.250 µm Minimum width of (MOS channel region interacting with NOSLC) not NOSLC14.11a 0.225 µm Minimum width (NSD and NOSLC)14.11b 0.225 µm Minimum width (PSD and NOSLC)14.12a 0.225 µm Minimum width (NOSLC not NSD)14.12b 0.225 µm Minimum width (NOSLC not PSD)14.13a 0.225 µm Minimum spacing outside edge of NSD to inside edge of NOSLC14.13b 0.225 µm Minimum spacing outside edge of PSD to inside edge of NOSLC



Salicide Protection Layer (NOSLC) (Continued)

Poly Contact Cut

NOSLC Active

RULE 14.05

(0.200 µm) RULE 14.03

(0.200 µm)

RULE 14.04

(0.400 µm)

RULE 14.01

(0.250 µm)

RULE 14.02

(0.400 µm)RULE 14.06

(0.275 µm)




Contact Cut Layer (CON)

Use this layer to define contact cuts to the active and poly areas.

Rule Value Description15.01 0.250 x 0.250 µm Contact size (only size and shape allowed)15.02 0.350 µm Minimum spacing15.02a 0.500 µm Minimum spacing for 5 to 24 closely placed CON15.02b 0.750 µm Minimum spacing for 25 or more closely placed CON15.03 0.175 µm Minimum ACT surround if contacting to ACT15.04 0.175 µm Minimum POLY surround if contacting to POLY15.05 0.275 µm Minimum spacing to POLY gate15.05a 0.350 µm Minimum spacing to POLY gate inside FLG3315.05b 0.350 µm Minimum spacing to POLY gate inside FLG5015.06 0.175 µm Minimum (ACT and POLY) surround if contacting to POLY over ACT15.07 0.175 µm Minimum NSD OR PSD surround15.08 Prohibited CON not over POLY or ACT

R15.01 0.125 µm Minimum recommended exclusive NSD or PSD surroundNote: In this figure the region receiving NSD also illustrates the case where PSD is used.

Contact Cut

PolyActive NSD Metal 1

RULE 15.06

(0.175 µm)

RULES 15.04, 15.07

(0.175 µm)

RULE 15.05

(0.275 µm)

RULE 15.03

(0.175 µm)

RULE 15.02

(0.350 µm)

RULE 15.02a

(>0.500 µm,

5 to 24 contacts)–

RULE 15.02b

(>0.750 µm,

>25 contacts)–

RULE 15.01

(0.250 x 0.250 µm)

(Square)



RF07; QDS1; 3DM2-T3

Low Resistance Tungsten Gate Shunt for RF Devices (TGSRF)


Use this layer to define low gate series resistance RF T-gates. TGSRF will connect to any intersecting M1 features.Metal 1 must be placed over all TGSRF features. It is permissible for this metal 1 to have its edges coincident with TGSRF, though providing metal 1 extension up to 0.150 µ m may reduce risk.

Rule Value Description16.01 0.250 µm TGSRF contact trench width (only size allowed)16.02 0.350 µm Minimum spacing16.03 0.350 µm Minimum spacing TGSRF to CON16.04 0.025 µm Maximum extension of TGSRF beyond POLY16.05 0.175 µm Minimum NSD OR PSD surround16.06 Prohibited TGSRF outside metal 1 prohibited16.07 Required CON should be provided to POLY even if TGSRF also provides metal

connection to POLYNote: In this figure the region receiving NSD also illustrates the case where PSD is used. Metal 1 would be placed in the same location as the drawn TGSRF features. The required NSD surround on the channel region (Rule 12.02) is not included.



Low Resistance Tungsten Gate Shunt for RF Devices (TGSRF) (Continued)

Contact Cut

Poly

NSD

Active

TGSRF

RULE 16.03

(0.350 µm)

RULE 16.05

(0.175 µm)

RULE 16.01

(0.250 µm)

RULE 16.02

(0.350 µm)

RULE 16.04

(0.025 µm

maximum)

RULE 16.03

(0.350 µm)





MSC2; 3DL1; 3DM2


This layer defines the first metal level.The M1 layer will be ORed with M1F to produce a single metal 1 mask.The M1F layer is to be used for fill patterns and labels only.Note: Also see Metal Z (MZ, MZF) Rule 36.xx.

Rule Value Description17.01 0.250 µm Minimum width17.02 0.300 µm Minimum spacing17.03 0.025 µm Minimum surround on contact cut17.04 0.150 µm Minimum line extension beyond contact cut (constraint must be met in at least

two opposite directions)17.05 Required Metal 1 over all TGSRF17.06 Prohibited Metal 1 interacting with M1F not allowed



R17.01 0.150 µm Minimum recommended surround on contact cut for improved contact resistance control

R17.02 0.300 µm2 Minimum recommended M1 areaR17.03 0.350 µm Minimum recommended M1 spacing for improved yieldR17.04 0.400 µm Minimum spacing if both metal line widths are >1.5 µ m wideR17.05 0.600 µm Minimum spacing if at least one metal line width is >5.0 µ m wideR17.06 1.000 µm Minimum spacing if at least one metal line width is >10.0 µ m wide



Metal 1 Layer (M1, M1F) (Continued)

Compact Option Conservative Option

PolyActive Metal 1Contact Cut

RULE R17.01

(0.150 µm)

RULE 17.01

(0.250 µm)

RULE 17.03

(0.025 µm)

RULE 17.01

(0.250 µm)

RULE 17.04

(0.150 µm)

RULE 17.02

(0.300 µm)

RULE R17.03

(0.350 µm)

RULE 17.04

(0.150 µm)




Metal 1/Metal 2 Via Layer (V12)This layer defines vias between the first and second metal levels.


two opposite directions)19.05 Allowed Stacked via V12 on contact (metal 1 must be present)19.06 Allowed Stacked via V12 on TGSRF (metal 1 must be present)




Metal 1 V12

RULE R19.01

(0.150 µm)

RULE 19.02

(0.400 µm)

RULE 19.02a

(>0.500 µm,

5 to 24 V12)–

RULE 19.02b

(>0.750 µm,

25 or more V12)–

RULE 19.03

(0.025 µm)

RULE 19.01

(0.300 x 0.300 µm)

(Square)

RULE 19.02

(0.400 µm)

RULE 19.02a

(>0.500 µm,

5 to 24 V12)–

RULE 19.02b

(>0.750 µm,

25 or more V12)–

RULE 19.04

(0.150 µm)

RULE 19.01

(0.300 x 0.300 µm)

(Square)





MSC2; 3DL1; 3DM2


This layer defines the second metal level.The M2 layer will be ORed with M2F to produce a single metal 2 mask.The M2F layer is to be used for fill patterns and labels only.

Rule Value Description20.01 0.250 µm Minimum width20.02 0.300 µm Minimum spacing20.03 0.025 µm Minimum surround on V1220.04 0.150 µm Minimum metal 2 line extension beyond V12 (constraint must be met in at least








Metal 2 Layer (M2, M2F) (Continued)

RULE R20.01

(0.150 µm)RULE R20.03

(0.350 µm)

RULE 20.01

(0.250 µm)

V12 Metal 2

RULE 20.04

(0.150 µm)

RULE 20.02

(0.300 µm)

RULE 20.01

(0.250 µm)

RULE 20.03

(0.025 µm)






This layer defines vias between the second and third metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description22.01 0.300 x 0.300 µm Via size (only size and shape allowed)22.02 0.400 µm Minimum spacing

22.02a 0.500 µm Minimum spacing for 5 to 24 closely placed V2322.02b 0.750 µm Minimum spacing for 25 or more closely placed V2322.03 0.025 µm Minimum metal 2 surround22.04 0.150 µm Minimum metal 2 line extension beyond V23 (constraint must be met in at least

two opposite directions)22.05 Allowed Stacked via V23 on V12 (intervening metals must be present)


V23 Metal 2

RULE 22.02

(0.400 µm)

RULE 22.02a

(>0.500 µm,

5 to 24 V23)–

RULE 22.02b

(>0.750 µm,

25 or more V23)–

RULE 22.01

(0.300 x 0.300 µm)

(Square)

RULE R22.01

(0.150 µm)

RULE 22.02

(0.400 µm)

RULE 22.02a

(>0.500 µm,

5 to 24 V23)–

RULE 22.02b

(>0.750 µm,

25 or more V23)–

RULE 22.01

(0.300 x 0.300 µm)

(Square)

RULE 22.03

(0.025 µm)

RULE 22.04

(0.150 µm)






MSC2; 3DL1; 3DM2

YES2; MIM1 Metal 3/Metal 4 Via Layer (V34)

(See M2 illustration)This layer defines the third metal level.The M3 layer will be ORed with M3F to produce a single metal 3 mask.The M3F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS







(See V12 illustration)This layer defines vias between the third and fourth metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS






MIM1 Metal 4 Layer (M4, M4F)


(See M2 illustration)This layer defines the fourth metal level.The M4 layer will be ORed with M4F to produce a single metal 4 mask.The M4F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS






(See V12 illustration)This layer defines vias between the fourth and fifth metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


28.02a 0.500 µm Minimum spacing for 5 to 24 closely placed V4528.02b 0.750 µm Minimum spacing for 25 or more closely placed V4528.03 0.025 µm Minimum metal 4 surround28.04 0.150 µm Minimum metal 4 line extension beyond V45 (constraint must be met in at least






(See M2 illustration)This layer defines the fifth metal level.The M5 layer will be ORed with M5F to produce a single metal 5 mask.The M5F layer is to be used for fill patterns and labels only.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS








RF07; QDS1 Top-Level RF Metal Via Layer (VTLRF)

This layer defines vias between the top-level RF metal level and the highest-level interconnect metal level below.For example, if the process includes three metal levels, and the third metal level corresponds to MTLRF, then VTLRF defines vias between MTLRF and M2.The rules for this layer are determined by the thickness of the ILD through which the via is formed.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


31.02a 0.950 µm Minimum spacing for 5 or more closely placed VTLRF31.03 0.150 µm Minimum surround by lower level metal31.04 Allowed Stacked via VTLRF on prior via (underlying metal must be present)

UnderlyingMetal

VTLRF

RULE 31.02

(0.550 µm)

RULE 31.02a

(>0.950 µm,

recommended

for 5 or more)

–

RULE 31.01

(0.450 x 0.450 µm)

(Square)

RULE 31.03

(0.150 µm)



YES2; RF07; QDS1

Top-Level RF Metal Layer (MTLRF, MTLRFF)

This layer defines a top-level metal layer optimized for RF design.The MTLRF layer will be ORed with MTLRFF to produce a single RF metal mask.The MTLRFF layer is to be used for fill patterns and labels only.The rules for this layer are determined by the thickness of the metal.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description32.01 1.000 µm Minimum width (wmin)32.02 1.000 µm Minimum spacing (dmin)32.03 0.250 µm Minimum surround on via VTLRF32.04 Prohibited MTLRF interacting with MTLRFF not allowed

D32.01 30% Required minimum metal MTLRF density within any 1 mm x 1 mm windowD32.02a 80% Required maximum metal MTLRF density within any 1 mm x 1 mm windowD32.02b 50% Required maximum metal MTLRF density within any 1 mm x 1 mm window

when 3D integration is to be performed

MTLRF VTLRF

RULE 32.03

(0.250 µm)

RULE 32.01

(1.000 µm)

RULE 32.02

(1.000 µm)




Overglass Pad Cut Layer (OGC)

MSC2; 3DL1; 3DM2

This layer defines pad cuts in the overglass, which allow top-level metal pads to be contacted.

Rule Value Description34.01 1.000 µm Spacing in from top-level metal pad edge34.02 Prohibited OGC not over top-level metal34.03 5.000 µm Minimum width34.04 5.000 µm Minimum spacing34.05 1.000 µm Spacing in from metal Z edge if metal Z is used



RULE 34.01

(1.000 µm)

Top-Level Metal Pad

Pad Cut



Metal Z Layer, Alternative Single Metal (MZ, MZF)

YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Anodized Aluminum Version

This layer defines an alternative single metal layer to allow testing without multiple metal layer processing.MZ is an alternative to, not a part of, the normal metal/via stack. (M1 is still required for normal wafer processing.) If used, MZ must satisify all M1 rules and surround OGC by 1.000 µ m.See “Antenna Effects and the Metal Z Layer” in MIT Low-Power FDSOI CMOS Process: Application Notes.

OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description36.01 0.250 µm Minimum width36.02 0.350 µm Minimum spacing36.03 0.150 µm Minimum surround on contact cut36.04 Required MZ over all TGSRF36.05 Prohibited MZ interacting with MZF not allowed

D36.01 30% Required minimum metal Z density within any 1 mm x 1 mm windowD36.02 50% Required maximum metal Z density within any 1 mm x 1 mm window

For process versions that include anodized aluminum capacitors, the MIMCAP layer defines the top plate metal version. The alumina etch mask is automatically generated by oversizing the drawn MIMCAP features.The top plate is contacted by a via up to the top-level metal; for a process with four digital metal levels, this top-level via is V34 and the bottom plate metal level is M3.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionAOC153.01 2.000 µm Minimum MIMCAP widthAOC153.02 2.000 µm Minimum MIMCAP spacingAOC153.03 0.500 µm Minimum MIMCAP surround on top-level viaAOC153.04 0.800 µm Minimum MIMCAP spacing to top-level via (where top-level via does not

connect to the MIMCAP top plate)AOC153.05 1.000 µm Bottom plate metal surround on MIMCAP



YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version

YES2; MIM1 MIM Capacitor Layer (MIMCAP)–Deposited Oxide Version with Wet Etch

For process versions that include deposited oxide MIM capacitors, the MIMCAP layer defines the ILD oxide etch region. The top plate is formed by the top-level metal; for a process with four digital metal levels, the bottom plate metal level is M3 and the top plate metal is M4.The top-level vias must be isolated from MIMCAP regions. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionDOC153.01 2.000 µm Minimum MIMCAP widthDOC153.02 2.000 µm Minimum MIMCAP spacingDOC153.03 1.000 µm Minimum MIMCAP spacing to top-level viaDOC153.04 0.500 µm Top plate metal surround on MIMCAPDOC153.05 0.500 µm Bottom plate metal surround on MIMCAPDOC153.06 0.500 µm Minimum top-level metal width within 1 µ m of MIMCAP

For process versions that include deposited oxide MIM capacitors, the MIMCAP layer defines the ILD oxide etch region. The top plate is formed by the top-level metal; for a process with four digital metal levels, the bottom plate metal level is M3 and the top plate metal is M4.The top-level vias must be isolated from MIMCAP regions. These rules have been adjusted to allow the etch region to grow by 1.5 µm on each side during the wet etch.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value DescriptionWDOC153.01 2.000 µm Minimum MIMCAP widthWDOC153.02 5.000 µm Minimum MIMCAP spacingWDOC153.03 2.500 µm Minimum MIMCAP spacing to top-level viaWDOC153.04 2.000 µm Top plate metal surround on MIMCAPWDOC153.05 2.000 µm Bottom plate metal surround on MIMCAPWDOC153.06 0.500 µm Minimum top-level metal width within 1 µ m of MIMCAP



MSC2;3DL1; 3DM2

3D Via Cut to Another Wafer Tier (3DCUT)


3DCUT defines 3D via cuts to another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier. The 3D via originates on the back side of the cut tier. Its dimensions on the lower numbered tier are defined by a "doughnut" opening in the cut tier's highest level metal (required).Rules assume three metal levels per tier and cuts originate from BOX side of tier.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description41.01 1.750 x 1.750 µm 3DCUT size (only size and shape allowed)41.02 1.450 µm Minimum spacing 3DCUT to 3DCUT on the same tier

41.02a 3.750 µm Minimum spacing for 5 to 24 closely placed 3DCUT on the same tier41.02b 5.800 µm Minimum spacing for 25 or more closely placed 3DCUT on the same tier41.03 0.625 µm Minimum top-level metal extension beyond 3DCUT41.04 1.500 x 1.500 µm Top-level metal doughnut opening size (only size and shape allowed)41.05 0.125 µm 3DCUT surround of top-level metal doughnut opening (only surround allowed)41.06 Prohibited 3DCUT outside of BM1 (when BM1 is available)

41.07a 1.175 µm Minimum spacing 3DCUT to active on the same tier 41.07b 1.150 µm Minimum spacing 3DCUT to POLY/POLYF on the same tier41.07c 1.125 µm Minimum spacing 3DCUT to M1/M1F on the same tier41.07d 1.150 µm Minimum spacing 3DCUT to V12 on the same tier41.07e 1.075 µm Minimum spacing 3DCUT to M2/M2F on the same tier41.07f 1.100 µm Minimum spacing 3DCUT to V23 on the same tier41.08a 0.500 µm Minimum top-level metal width for wire connecting to top-level metal doughnut41.08b 0.350 µm Minimum top-level metal length at Rule 41.08a width for connecting to

top-level metal doughnut41.09 Prohibited 3DCUT not coincident with 3DLAND on next lower numbered tier41.10 Prohibited 3DCUT without top-level metal doughnut



3D Via Cut to Another Wafer Tier (3DCUT) (Continued)

RULE 41.07b

(1.150 µm)

RULE 41.07a

(1.175 µm)

RULE 41.02

(1.450 µm)

RULE 41.05

(0.125 µm)

RULE 41.03

(0.625 µm)

RULE 41.01

(1.750 µm)

(Square)

RULE 41.04

(1.500 µm)

(Square)

RULE 41.07c

(1.125 µm)

PolyActive Top-LevelMetal

3D Cut“Doughnut”Cut

Metal 1



MSC2; 3DL1; 3DM2

3D Via Landing from Another Wafer Tier (3DLAND)

3DLAND defines 3D via landings from another wafer tier.The term "tier" refers to a single "conventionally" fabricated wafer. When two tiers are stacked, 3DCUT defines the 3D via starting point on the higher numbered tier while 3DLAND indicates the 3D via stopping location on a metal layer of the lower numbered tier.The 3D via penetrates the "land" wafer from the back side and stops on the first metal layer unless 3DFLIP is present on the landing tier.The presence of 3DFLIP anywhere on the tier's layout indicates that when assembled with other tiers it will be flipped with the 3D via stopping on the top-level metal (not reaching POLY or ACT).OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description42.01 1.750 x 1.750 µm 3DLAND size (only size and shape allowed)

42.02a 0.625 µm Minimum metal surround of 3DLAND back side metal if present; otherwise first-level metal without 3DFLIP, top-level metal with 3DFLIP

42.02b Prohibited 3DLAND outside of metal landing back side metal if present; otherwise, first metal without 3DFLIP, top-level metal with 3DFLIP

42.03 Prohibited 3DLAND not coincident with 3DCUT in next higher numbered tier42.04a 1.350 µm Minimum space 3DLAND to active on non-3DFLIP tier when back side metal

is not used42.04b 1.250 µm Minimum space 3DLAND to POLY/POLYF on non-3DFLIP tier when back side

metal is not used

3DLAND Poly Active Landing Metal

RULE 41.01

(2.500 µm)

(Square)

RULE 42.04b

(1.250 µm)RULE 42.04a

(1.350 µm)

RULE 42.01

(1.750 µm)

(Square) RULE 42.02a

(0.625 µm)



MSC2; 3DL1; 3DM2

Flag for Flipped Wafer w.r.t. Final 3D Stack (3DFLIP)

3D Back Side Cut Through Buried Oxide (3DBOXC)

3D Back Side Metal Gate (3DBMG)

MSC2; 3DL1; 3DM2

Pad Cut for Final 3D Stack (3DOGC)

This is a flag layer that is used to indicate that during 3D assembly, a particular tier is flipped with respect to the final 3D stack.Tiers requiring 3DFLIP flags shall be determined by MITLL.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description44.01 Prohibited 3DCUT on a 3DFLIP tier

3DBOXC defines a cut made through the buried oxide under the silicon of a wafer tier that has been integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


3DBMG defines a metal gate formed on the back side of a wafer tier that is integrated into a 3D stack.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


3DOGC defines pad cuts for the final assembled 3D stack.Opens back side pad cuts to tier 3 back side metal if present; otherwise, to tier 3 front side metal 1Note that active and poly fill features are allowed under 3DOGC. It is important, however, to ensure that these are isolated from circuit features. Rules 47.02 and 47.03 do not prohibit ACTF and POLYF from being under 3DOGC. However, fill features must be isolated from circuit features per rules 1.05 and 9.10. Rules 47.02 and 47.03 do not apply if 3DOGC opens to back side metal.If overglass cuts to heat sink structures are desired, the same rules apply as for bondpads. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description47.01 1.0 µm Required minimum pad metal surround on 3DOGC47.02 6.650 µm 3DOGC spacing to POLY if back side metal is not used47.03 6.750 µm 3DOGC spacing to ACT if back side metal is not used47.04 5.000 µm 3DOGC minimum width47.05 5.000 µm 3DOGC minimum spacing



Common Landing Metal Flag (3DCNX)

Back Side Metallization Layers

3DM2-T2; 3DM2-T3

Back Side Metal 1/Front Side Metal 1 Via Layer (BVIA0)

3DM2-T2 Back Side Metal 1 Layer (BM1)

This flag layer indicates that particular 3DCUT features share a common landing pad.Should be drawn in a manner that is representative of the common landing metal.This flag suppresses enforcement of Rule 41.03.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

This layer defines vias between the first front side metal and first back side metal.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description62.01 0.450 x 0.450 µm Size (only size and shape allowed)62.02 0.550 µm Minimum spacing

62.02a 3.750 µm Minimum spacing for 5 to 24 closely placed BVIA062.02b 5.800 µm Minimum spacing for 25 or more closely placed BVIA062.03 0.300 µm Minimum front side metal 1 surround62.04 0.400 µm Minimum BVIA0 spacing to POLY/POLYF62.05 0.350 µm Minimum BVIA0 spacing to active


Rule Value Description63.01 0.500 µm Minimum width63.02 0.500 µm Minimum spacing63.03 0.875 µm Minimum surround on 3DCUT63.04 0.150 µm Minimum surround on BVIA0




3DM2-T3 RF Back Side Metal 1 Layer (BM1)


Back Side Metal 2/Back Side Metal 1 Via Layer (BVIA1)


Rule Value DescriptionRF63.01 1.000 µm Minimum widthRF63.02 1.000 µm Minimum spacingRF63.03 0.625 µm Minimum surround on 3DCUTRF63.04 0.150 µm Minimum surround on BVIA0

RFD63.01 30% Required minimum back side metal 1 density within any 1 mm x 1 mm windowRFD63.02 80% Required maximum back side metal 1 density within any 1 mm x 1 mm window

This layer defines overglass cuts to back side metal 1.If back side metal 2 (BM2) is also used, BOGC1 will only be used to access circuits prior to BM2 if this is needed for testing. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


This layer defines vias between the second and first back side metal levels.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description65.01 0.500 x 0.500 µm Width (only size and shape allowed)65.02 0.400 µm Minimum spacing

65.02a 0.500 µm Minimum spacing for 5 to 24 closely placed BVIA165.02b 0.750 µm Minimum spacing for 25 or more closely placed BVIA165.03 0.500 µm Minimum back side metal 1 surround



Back Side Metal 2 Layer (BM2)


Additional Layers: Flag and Comment (Markup)


NOFILL

Channel Flag Region (FLGCHAN)

This layer defines the second back side metal level.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description66.01 2.000 µm Minimum width66.02 2.000 µm Minimum spacing66.03 0.500 µm Minimum back side metal 2 surround on via BVIA1


This layer defines overglass cuts to back side metal 2.OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS


(Comment layers are included as a design aid and have no effect on the layout other than the cell extents.)

This layer suppresses automatic fill generation. In regions not covered by NOFILL, fill structures are automatically generated by MITLL to force compliance with layer density rules.See MITLL Low-Power FDSOI CMOS Process: Application Notes.

Warning: When NOFILL is used the designer takes responsiblity for all layer density specifications in that region of use. Designs that use NOFILL must meet all density constraints after application of the automatic fill generation routine.

This layer indicates the channel region of nonsimple devices.For body-contacted devices, this should be drawn coincident with POLY, excluding the body contact gate extension POLY.

Rule Value Description80.01 Prohibited FLGCHAN and NOSDX



Voltage Flag Layers (FLG33, FLG50)


DEVR


DEVL


DEV-MC


DEVD

NOSLOT


Red, Green, Blue, Yellow

FLG33 and FLG50 are used to indicate 3.3-V and 5.0-V devices, respectively. Devices not enclosed by FLG33 or FLG50 will have the engineering for the default maximum supply rail voltage for the particular run, usually 1.5 V.Note that implant features drawn crossing voltage regions are split at the voltage boundary to form multiple masks and therefore must meet minimum width requirements within each voltage region. OPTIONAL LAYER–NOT OFFERED IN ALL PROCESS VERSIONS

Rule Value Description85.01 Prohibited Overlapping voltage regions prohibited85.02 0.400 µm Minimum exclusive 1.5-V-only region surrounding 1.5-V gate86.02 0.400 µm Minimum exclusive 3.3-V-only region surrounding 3.3-V gate87.02 0.400 µm Minimum exclusive 5.0-V-only region surrounding 5.0-V gate

Indicates device is resistor for verification and simulation

Indicates device is inductor for verification and simulation

Indicates device is metal 1/metal 2 capacitor for verification and simulation

Indicates device is lateral diode for verification and simulation

Reserved for future use

Comment layers


MITLL Low-Power FDSOI CMOS Process: Design GuideLAYOUT ACCEPTANCE REQUIREMENTS


6. LAYOUT ACCEPTANCE REQUIREMENTS

6.1. Design Grid

Layouts must be done to a 0.025-µ m (25 nm) grid at the wafer; i.e., the smallest fundamental unit (λ) is 0.025 µ m, and all polygon corners in the layout must be on a 0.025-µ m grid. Noncompliance with the 0.025-µ m grid may lead to reticle errors and unpredictable results. Submissions with structures, substructures, or extents placed off this grid will not be accepted.

6.2. Layout Database Format

GDSII is the preferred format for all layout submissions. CIF is an acceptable alternative if GDSII is not possible. A list of GDSII layer numbers and CIF layer names is included in the “Design Layers” chapter.

In the layout database, the precision must be 1000 with a unit length in µ m (1E-6).

Any round-ended paths (GDS PATH TYPE 1) must be flattened to polygons prior to submission.

All data must be placed inside the intended rectangular extent of the top structure. Any data placed outside will result in additional fill pattern generation in that region during postprocessing and, consequently, will “grow” the submission to a larger unintended extent.

The following GDS data types or attributes are not supported and should not be included:

BOX NODE ABSOLUTE MAGNIFICATIONABSOLUTE ANGLESNONORTHOGONAL REFERENCES

6.3. Top-Level Cell Labels

All top-level cells must have instantiated within them a label containing a brief design identifier and the name of the submitting organization. It is strongly encouraged that this be drawn in top-level metal so that chips may be easily identified after fabrication.

MSC2; 3DL1; 3DM2

6.4. 3D Layout and Tier Orientation

Submissions for a 3D stacking process must have the same extent on all tiers, their origins centered in the extents, and the same top structure name with a final number designating to which tier each belongs. Exception: If a top-level cell on one tier is to be instantiated multiple times to align to a set of top-level cells on other tiers, then this top-level cell needs to be submitted only once. Detailed documentation must be provided, however, listing the submitted top-level cells, their corresponding tiers, and the alignment of the final assembly.



The submitted GDS files will represent data that is in the same orientation as the final chip, with the 3DOGC bond pads up. All data flipping needed for 3D integration is done by MITLL after all designs and other mask features are stitched together.

6.5. Minimum Rule Set

Table 6-1 lists the rules that must be followed for a layout to be accepted for inclusion in an MITLL FDSOI multiproject run. Any violation of these rules requires explicit permission from MITLL. The purpose of this rule subset is to protect other designs on the run. It is incumbent on designers to accept all responsibility for the effects of rules violations on their own designs.

6.6. Contact Information

Contributor contact information must accompany all submissions to allow follow-up as required.

6.7. Disclaimer

MITLL reserves the right to modify submission requirements at any time. It is strongly recommended that designs be made compliant with all design rules, so that future modifications to autogeneration routines, mask specifications, etc. will not create incompatibilities between design data and layout postprocessing, mask fabrication, and wafer fabrication processes.



Table 6-1: List of Mandatory Rules

Rule DescriptionConstraint for Baseline 2D

Process

Constraint for 3D Integrated

Processes

General Polygon and Path Rules:

0.1 Minimum feature width 0.200 µ m 0.200 µ m

0.2 Minimum feature spacing 0.250 µ m 0.250 µ m

0.3 Acute angles Prohibited Prohibited

Grid Rules:

0.4 Vertices must be on a 0.025-µ m grid

Density Rules (Enforced after Execution of MITLL Fill Generation Script):

Within any 1 mm x 1 mm window:

D1.01 Minimum active density 30% 30%

D1.02 Maximum active density 70% 70%

D9.01 Minimum poly density 15% 15%

D9.02 Maximum poly density 35% 35%

D17.01 Minimum metal 1 density 30% 30%

D17.02 Maximum metal 1 density 80% 50%







Density Rules (Enforced after Execution of MITLL Fill Generation Script):





D32.01 Minimum MTLRF density 30% 30%

D32.02 Maximum MTLRF density 80% 50%

D63.01 Minimum back metal 1 density 30%

D63.02 Maximum back metal 1 density 50%

D66.01 Minimum back metal 2 density 20%

D66.02 Maximum back metal 2 density 50%

RFD63.01 Minimum RF back metal 1 density 30%

RFD63.02 Maximum RF back metal 1 density 80%

Table 6-1: List of Mandatory Rules

Rule DescriptionConstraint for Baseline 2D

Process

Constraint for 3D Integrated

Processes


MITLL Low-Power FDSOI CMOS Process: Design GuideMISCELLANEOUS

7. MISCELLANEOUS

QDS1 7.1. Special Notes for QDS1

Use ACTXPP for definition of CCD active. Be mindful of sidewall effects.

All polysilicon not within a layer 10 POLY feature will be etched away, regardless of PSM design. Do not use layer 11 POLYPS for PSM definition. See Table 7-1.

The basic ground rules for PSM definition are as follows:

• The PSM_TARG spacing must be either exactly 0.1 µ m or ≥0.25 µ m. The minimum PSM_TARG width is 0.2 µ m.

• The PSM_CRIT must be inside POLY.

Table 7-1: New Layers for QDS1

Layer No. Note

Additional implant definition layers:

GRADED_IMP 154 Graded implant

CCDGI 155 CCD gate implant

PSM verification layers:

FLGCCD 156 Flag regions for CCD extraction

PSM_TARG 159 Desired PSM-defined final polysilicon feature (after PSM cuts are made)

PSM_CRIT 160 Critical PSM edge (where CD control is most important)

PSM definition layers:

PSM_180 161 PSM mask 180° phase region

PSM_CHROME 162 PSM mask chrome region

SLOT_ERASE 163 Erase PSM-defined slots by double exposure



7.2. Special Notes for 3DM2

Lincoln Laboratory has developed a three-dimensional (3D) integrated circuit technology in which circuit structures formed on several silicon-on-insulator (SOI) substrates may be integrated into a 3D integrated circuit. The building blocks of the 3D circuit integration technology are fully depleted SOI circuit fabrication, low-temperature wafer-wafer oxide bonding, precision wafer-wafer alignment, and electrical connection of the circuit structures with dense vertical interconnections. When compared to conventional bump bond technology, this 3D technology offers better circuit-to-interconnect ratio, higher-density vertical interconnections, and reduced system power. This section describes the integration process and highlights some unique design requirements.

Three-dimensional circuits are fabricated by transferring and interconnecting the active sections of wafers fabricated on 150-mm SOI substrates to a base wafer. The active section, labeled a tier, in a 3D system of n tiers consists of the interconnect and active silicon and is transferred to the base tier, tier 1, which can be either a bulk or SOI wafer. Since all 3D circuits that are designed as part of the digital 3D Multiproject program will be composed of three SOI tiers, the base wafer will also be SOI.

The 3D circuit integration process begins with the fabrication of three fully depleted SOI tiers, as shown in Fig. 7-1. Then, wafer 2 is inverted, aligned, and bonded to wafer 1, as shown in Fig. 7-2. The handle silicon is removed from tier 2, 3D vias are etched through the oxides of tiers 2 and 1 and stop on metal pads in tier 1, and tungsten is deposited and planarized using chemical-mechanical polishing (CMP). The structure shown in Fig. 7-3 is a two-tier assembly with electrical connections between the top-level metal of tier 2 and the top-level metal of tier 1. Following the inter-tier via formation, back side via (BVIA0) and back side metal (BM1) are formed, as shown in Fig. 7-4. Tier 3 is transferred to the two-tier assembly using the same processes as for the tier 2 transfer, except that the 3D vias connect the top-level metal of tier 3 to the back side metal of tier 2, as shown in Fig. 7-5. The completed 3D assembly is shown in Fig. 7-6 after back side metallization of tier 3. Bond pads and heat sink cuts are formed (3DOGC) to expose this tier 3 BM1 for probing, wire bonding, and cooling. A detailed list of layer thicknesses is presented in Fig. 7-7.



Figure 7-1: Three tiers that will be integrated to form a 3D integrated circuit at the completion of conventional integrated circuit fabrication.

Figure 7-2: Tier 2 aligned and bonded to tier 1 before removal of the handle silicon. The wafer bond is a low-temperature oxide bond.

Figure 7-3: Tier 2 electrically connected to tier 1 with tungsten plugs after removal of the handle silicon, etching of 3D vias between the tiers, and deposition and planarization of tungsten.

Buried Oxide

Buried Oxide

Buried Oxide

Wafer 3

Wafer 2

Wafer 1

Handle Silicon

Handle Silicon

Handle Silicon

Tier 3

Tier 2

Tier 1

Wafer

Bond

Wafer 2

Wafer 1

Handle Silicon

Tier 2

Tier 1

W Connection Concentric

3D Via

Wafer 1 Handle Silicon

Tier 2

Tier 1



Figure 7-4: Tiers 1 and 2 after teir 2 back side via and back side metal formation.

Figure 7-5: Tier 3 after it was aligned, transferred, and interconnected to the assembly shown in Fig. 7-4.

Figure 7-6: Three-tier assembly of Fig. 7-5 shown after tier 3 back side metal formation. Locations of possible 3DOGC overglass cuts are indicated.


Tier 2

Tier 1


Tier 2

Tier 1

Tier 3


Tier 2

Tier 1

Tier 3

3DOGC Opens to This Metal Level



Figure 7-7: Thickness stack for three-tier structure with actual layer thicknesses indicated. Final overglass is not shown.

Back metal 1

Back Metal 1 (RF)

630

Tier 3

Tier 3

Cap oxide 200

Tier 3 BOX 400

Tier 3 SOI island 50

Tier 3 LTO over island 800

Tier 3 Metal 1

630

Tier 3 ILD 1-2 PECVD TEOS

Tier 3 Metal 2

630


1000

Tier 3 Metal 3

630

Tier 3 M3 overglass PECVD TEOS

Tier 3 BSG cap oxide

2000

Tier 2


Tier 2

PECVD TEOS

Tier 2 Cap oxide 200

Tier 2 BOX 400



Tier 2 Metal 1 630


1000

Tier 2 Metal 2 630


Tier 2 Metal 3 630


1000


500Tier 1 BSG cap oxide

500

500

500


1000

Tier 1 Metal 3 630

Tier 1 ILD 2-3 PECVD TEOS 1000

Tier 1 Metal 2 630

Tier 1 ILD 1-2 PECVD TEOS 1000

Tier 1 Metal 1 630



Tier 1 BOX 400

Tier 1 Silicon substrate

Tier 3 : BM1 Tier 3 : BM1 Tier 3 : BM1

Tier 3 : M1

Tier 3 : M3

Tier 2 : BM1 Tier 2 : BM1

Tier 2 : M3

Tier 2 : M1

Tier 1 : M3

Tier 1 : M1

500

500

500

500

1450 nm

1450 nm

4710 nm3D Via

2000 nm

7340 nm

T2

BV0

T3

BV0

7340 nm

3D Via 3D Via4710 nm

2000 nm

Oxide-Oxide Bond

Oxide-Oxide Bond

3D

M2 T

ier 3

3D

M2 T

ier 2

3D

M2 T

ier 1



The layout of each tier of a 3D circuit should be done as in conventional 2D technology. The designer must take into account the integration process discussed above, since the two upper tiers will be inverted with respect to tier 1 and the three tiers must be designed such that they will be aligned during fabrication. The layers for each tier will be placed correctly on each reticle with existing layout software, provided the designer has designed each tier with coincident origins. Connections between tiers require a 3DCUT, which defines the 3D via starting point on the higher numbered tier, and 3DLAND, which defines the 3D via stopping location on a metal layer on the lower numbered tier. When the tiers are overlaid, the 3DCUTs must exactly match the 3DLANDs in the lower tier and each 3DLAND must have a matching 3DCUT in the higher tier. The top of a 3D via starts on the back side of the higher numbered tier, and the 3DCUT dimension determines its size. The size of the 3D via in the lower tier is defined by the doughnut opening in metal 3 of the upper tier; the doughnut is illustrated in the MITLL Low-Power FDSOI CMOS Process: Design Guide (Rule 41.06). The 3DCUT feature is unique to the 3D technology, but the designer must ensure that the 3DLAND and doughnut features are included in the metal designs of the FDSOI layers. Table 7-2 shows the metal layers of the 3DLAND and doughnut features for each tier; the two 3DCUT layers are color coded to associate them with the tiers to be interconnected.

Layouts for all three tiers should be done as viewed after assembly, with bond pads to the 3D circuit face up.

The analysis and control of temperature effects in a 3D circuit is a topic of current research. The designer can reduce the effects of power dissipation on the operation of 3D circuits by placing the circuits that dissipate the most power in tier 1, since the base of tier 1 is the silicon handle and it will be attached to an IC package for mechanical stability and heat conduction. Heat generated by circuits in tier 3 can be managed by including a back metal structure to aid the extraction of heat through the top side of the circuit.

Table 7-2: Metal features associated with 3DCUT and 3DLAND layers required for 3D circuit integration

Tier 3DLAND Doughnut Tier

3DCUT 11 Metal 3 None 1

2 Metal 1 Metal 3 23DCUT 2

3 None Metal 3 3


MITLL Low-Power FDSOI CMOS Process: Design GuideCONTACT INFORMATION


CONTACT INFORMATION

For specific inquiries:

Technical: Layout submission:

Brian Tyrrell Bruce Wheeler(781) 981-5496 (781) [email protected] [email protected]

Device modeling: Editorial:

Peter Wyatt Karen Challberg(781) 981-7882 (781) [email protected] [email protected]

For any other questions, comments, or suggestions:

MIT Lincoln Laboratory Advanced Silicon Technology Group 244 Wood Street Lexington, MA 02421 Phone: (781) 981-7880 Fax: (781) 981-7889 http://www.ll.mit.edu/AST

MITLL Low-Power FDSOI CMOS Process: Design GuideREVISION HISTORY

REVISION HISTORY

Rev. 2006:4 (Jul. 06)

In Section 2.1, modification of QDS1 and 3DM2 process version descriptionsRevision of Tables 2-2 and 2-4In Section 3.1, change of availability for NOSDX and NODEGRevision of Section 4.1 marginaliaDeletion of Section 4.3, Alternative Metal Z ProcessAddition of new Sections 4.3–4.5Modification of rules 12.01, 12.02, 12.03, 12.08, and 12.10Addition of rules 12.01a, 12.01b, 12.04a, 12.04b, 12.08a, 12.08c, and 12.08dShift of rule 12.08 to 12.08bDeletion of rule 12.11Modification of rules 13.01, 13.02, 13.03, 13.08, and 13.10Addition of rules 13.01a, 13.01b, 13.04a, 13.04b, and 13.08a, 13.08c, and 13.08dShift of rule 13.08 to 13.08bDeletion of rule 13.11Modification of rules 14.01 and 14.02Addition of rules 14.11a, 14.11b, 14.12a, 14.12b, 14.13a, and 14.13bModification of illustration of VTLRF layer rulesModification of illustration of MTLRF, MTLRFF layer rulesAddition of rule 80.01Revision of Table 7-1In Section 7.2, deletion of paragraph 4 and Figure 7-8

Rev. 2006:3 (Apr. 06)

Global replacement of notation TST1 by QDS1In Section 2.1, modification of YES2 and MIM1 process version descriptionsIn Section 3.1, modification of 3DALT and 3DLAND layer availability for 3DM2In Section 3.1, modification of M5, M5F, PORTM5, TEXTM5, and M5BLKG layer availability for MIM1In Section 4.1, deletion of marginal notation MIM1In Section 5.1, addition of definition for gate regionDeletion of rule 1.01 and shift of rules 1.02–1.07 to 1.01–1.06Shift of rules 9.09–9.10 to 9.07–9.08Modification of rule 12.09 and addition of rule 12.11Modification of rule 13.09 and addition of rule 13.11Modification of rule 14.06 and addition of rule 14.10Modification of rule 17.03Modification of illustration of Metal 1 layer rules



Modification of rules 41.02–41.02b, deletion of rule 41.03, shift of rules 41.04–41.06 to 41.03–41.05, addition of rule 41.06, deletion of rules 41.07–41.11, addition of rules 41.07a–f, and shift of rules 41.12–41.14 to 41.08–41.10

Modification of illustration of 3DCUT layer rulesDeletion of rules 42.02–42.03, shift of rules 42.04–42.07 to 42.02–42.04b, and modification of newly

numbered rules 42.04a and 42.04bModification of illustration of 3DLAND layer rulesDeletion of 3DCUT and 3DLAND alternate rule sets and of 3DALT rule setModification of rules 62.03–62.05 and deletion of rules ALT62.03 and 62.06Modification of rules 63.03–63.04 and RF63.03–RF63.04

Rev. 2006:2 (Mar. 06)

Update of Section 1.1In Section 2.1, addition of process description for 3DM2Introduction of tier-specific marginalia for 3DM2Throughout guide, update of marginalia for 3DM2In Table 2-3, addition of BM1 and RF BM1 sheet resistancesIn Table 2-4, addition of BVIA0 resistanceIn Section 3.1, introduction of tier-specific layer availability for 3DM2Revision of subsection 3.2.3Modification of rules D1.01, D1.02, D9.01, and D9.02Modification of description for polysilicon gate rulesModification of illustration of metal 1 layer rulesShift of rule 17.04 to 17.05, 17.05 to 17.06, R17.01 to R17.04, R17.02 to 17.05, and R17.03 to R17.06Modification of rules 17.02 and 17.03Addition of rules 17.04, R17.01, R17.02, and R17.03Modification of illustration of V12 layer rulesShift of rule 19.04 to 19.05 and 19.05 to 19.06Modification of rule 19.03Addition of rules 19.04 and R19.01Modification of illustration of metal 2 layer rulesShift of rule 20.04 to 20.05, R20.01 to R20.04, R20.02 to R20.05, and R20.03 to R20.06Modification of rules 20.02 and 20.03Addition of rules 20.04, R20.01, R20.02, and R20.03Modification of illustration of V23 layer rulesShift of rule 22.04 to 22.05Modification of rule 22.03Addition of rules 22.04 and R22.01Shift of rule 23.04 to 23.05, R23.01 to R23.04, R23.02 to R23.05, R23.03 to R23.06



Modification of rules 23.02 and 23.03Addition of rules 23.04, R23.01, R23.02, and R23.03Shift of rule 25.04 to 25.05Modification of rule 25.03Addition of rules 25.04 and R25.01Shift of rule 26.04 to 26.05, R26.01 to R26.04, R26.02 to R26.05, and R26.03 to R26.06Modification of rules 26.02 and 26.03Addition of rules 26.04, R26.01, R26.02, and R26.03Shift of rule 28.04 to 28.05Modification of rule 28.03Addition of rules 28.04 and R28.01Shift of rule 29.04 to 29.05, R29.01 to R29.04, R29.02 to R29.05, and R29.03 to R29.06Modification of rules 29.02 and 29.03Addition of rules 29.04, R29.01, R29.02, and R29.03Modification of section header for MTLRF rulesModification of rules 42.04a, 42.04b, 42.06, and 42.07Modification of rules ALT42.04a, ALT42.04b, ALT42.06, and ALT42.07Modification of description for 3DOGC rulesModification of rules 47.02 and 47.03Modification of rules 62.01, 62.02, 62.03, ALT62.03, and 62.04 to 62.06Elimination of heat sink only BM1 rulesModification of rules 63.01, 63.02, 63.03, and 63.04 Addition of RF BM1 layer rulesAddition of rules RF63.01, RF63.02, RF63.03, RF63.04, RFD63.01, and RFD63.02Modification of NOFILL usage warningUpdate of Table 6-1Revision of Table 7-1.Addition of Section 7.2

Rev. 2006:1 (Feb. 06)

In Section 2.1, addition of process description for TST1Addition of subsection 2.2.1In Section 3.1, addition of layer availability for TST1In Section 3.1, addition of layers NOSDX, NODEG, and TKOXAddition of rules 1.06, 1.07, 2.01, 2.02, 2.03, R9.05, R12.01, R13.01, R17.01, R17.02, R17.03, R20.01,

R20.02, R20.03, R23.01, R23.02, R23.03, R26.01, R26.02, R26.03, R29.01, R29.02, R29.03, and 34.05

Revision of rules 1.02, 1.03, 3.01, and 3.02, and R15.01Correction of labels in illustrations for rules 14.01, 14.02, 14.03, 14.05, 14.06, 32.01, 32.02, and ALT 41.07



Modification of description for 3DOGC rulesAddition of Section 7.1

Rev. 2005:4 (Jun. 05)

Addition of detailed revision logUpdate of introductionAddition of MIM1 to process description, layer availability table, and marginaliaIn Section 2.3, addition of notes on nearbody capacitance and file availability for capacitance extractionRevision of descriptions for rules 15.01, R15.01, 19.01, 22.01, 25.01, 28.01, 31.01, 41.01, 41.05, 42.01,

ALT41.01, ALT41.05, ALT42.01, 62.01, and 65.01Major revision of MIMCAP rules 153.xIn 3DOGC rules section, addition of clarification note Modification of rules 63.01, 63.02, 63.03, 66.01, and 66.02Modification of rules 62.02a and 62.02bAddition of heat sink only BM1 rules HS63.01 through HS63.04In Section 6.4, addition of paragraph on 3D tier orientationIn Table 6-1, change of rule #.005 to rule 0.4Update of design rules nomenclature sectionUpdate of description for ACT rulesReplacement of FLG350 with FLG33 in POLY rulesAddition of rule R34.01Revision of descriptions for CAPP and CAPN rulesUpdate of figure for POLY rules

Rev. 2005:3 (Apr. 05)

Update of layer availability table and availability marginaliaAddition of layer MIMCAPShift of rules 9.07 and 9.08 to R9.03 and R9.04Major revision of rules 14.xAddition of rule R15.01Replacement of D17.02, D20.02, D23.02, D26.02, D29.02, and D32.02 with Dx.02a and Dx.02bAddition of MIMCAP rules 153.x

Rev. 2005:2 (Feb. 05). Not released.

Introduction of process version marginaliaAddition of 3D process version descriptionsElimination of ~5–10 Ω-cm substrate optionShift of CAPLCN parameters from Table 2-13 to appropriate process parameter tablesAddition of 3.3-V device capacitance parameters



Revision of ILD parameter tablesAddition of other film parameters for 3.3-V devicesAddition of film thermal parametersRevision of active island width toleranceIncorporation of design layer tables into layer availability tableGlobal replacement of 3DPAD by 3DOGCAddition of layers 3DCNX, PORTHANDLE, PORTACT, PORTPOLY, PORTM1, PORTM2, PORTM3,

PORTM4, PORTM5, PORTMTLRF, PORTMZ, PORTBM1, PORTBM2, TEXTACT, TEXTPOLY, TEXTM1, TEXTM2, TEXTM3, TEXTM4, TEXTM5, TEXTMTLRF, TEXTMZ, TEXTBM1, TEXTBM2, ACTBLKG, POLYBLKG, M1BLKG, M2BLKG, M3BLKG, M4BLKG, M5BLKG, MZBLKG, and MTLRFBLKG

Deletion of layers NOSLOT and BREMReplacement of back side metal layers with the set BVIA0, BM1, BOGC1, BVIA1, BM2, and BOGC2Revision of design rules nomenclature sectionShift of rule 3.01 to R3.01, 3.02 to 3.01, and 3.03 to 3.02; addition of rule R1.01Replacement of rule 4.07 with new 4.07 and 4.08, and of rule 5.07 with new 5.07 and 5.08Addition of rules 9.01b and 9.02b; revision of 9.03, 9.04, and 9.05; deletion of 9.06; shift of 9.07–9.10 to

9.06–9.09; revision of new rule 9.09; addition of new rule 9.10; shift of 9.11 and 9.12 to R9.01 and R9.02 and revision of R9.01 and R9.02

Deletion of rules 12.11, 12.12, 13.11, and 13.12Revision of rule 14.08Revision of rule 15.05; addition of rules 15.05a and 15.05b; deletion of rule 15.09Revision of rules 19.02a, 19.02b, 22.02a, 22.02b, 25.02a, 25.02b, 28.02a, 28.02b, 31.02a, 32.01, and 32.02Addition of rules 17.05, 20.04, 23.04, 26.04, 29.04, 32.04, and 36.05Major revision of rules 41.x, 42.x, ALT41.x, and ALT42.x; revision of description for 3DALT; addition of 3DOGC

rules 47.01–47.05; addition of description for 3DCNX Addition of back side metal rules 62.x, ALT62.x, 63.x, D63.x, 64.x, 65.x, 66.x, D66.x,and 67.xAddition of description for FLGCHANAddition of FLG33 and FLG50 rules 85.x, 86.x, and 87.xIn Table 6-1, addition of a column to allow for separate specification of layer density rules for 2D and 3D

processes

Rev. 2005:1 (Feb. 05). Only RF01 version released.

Revision of spacer film parametersAddition of voltage specifications tableAddition of layers DEV-MC and DEVDGlobal replacement of FLG350 by FLG33Addition of rules 34.03 and 34.04Revision/addition of descriptions for DEVR, DEVL, DEV-MC, and DEVD



Rev. 2004:1 (Nov. 04). Replaces Version 6.x.

Application of new document formatting of data drawn from multiple inconsistent sourcesOrganization of document into three volumesMajor revision of process parameters sectionExpansion of design layers tableGlobal replacement of CONRFG by TGSRFOmission of general rule check sectionModification of design rules 12.11, 13.11, 15.09, 16.07, D17.02, D20.02, D23.02, D32.02, and D36.02Revision of layout acceptance requirementsRevision of 3D via design rules, based primarily on MSC1 dataRelease of RF01 and 3D01 versions


mitll low-power fdsoi cmos processdilli/research/layout/...mim1), rf-optimized (rf07 and qds1), 3d...

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