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Modeling and Control of Resonant Switched Capacitor DC-DC Converter

Yongjun LiSeth R. Sanders, Ed.Kristofer Pister, Ed.

Electrical Engineering and Computer SciencesUniversity of California at Berkeley

Technical Report No. UCB/EECS-2018-6http://www2.eecs.berkeley.edu/Pubs/TechRpts/2018/EECS-2018-6.html

March 14, 2018

Copyright © 2018, by the author(s).All rights reserved.

Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission.

Modeling and Control of Resonant Switched Capacitor

DC-DC converter

by Yongjun Li

Research Project

Submitted to the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II. Approval for the Report and Comprehensive Examination:

Committee:

_____________________________

Seth R. Sanders Research Advisor

_____________________________

Date

* * * * * *

_____________________________

Kristofer Pister Second Reader

_____________________________

Date

Feb. 23, 2018

March 14, 2018

1

Abstract

Modeling and Control of Resonant Switched Capacitor DC-DC Converter

by

Yongjun Li

Master of Science in Electrical Engineering and Computer Science

University of California, Berkeley

Professor Seth R.Sanders, Chair

Present-day mobile platforms call for a compact power management solution due to thenecessity of packing ever increasing functionality into a very constrained form factor. Theconventional buck/boost converter su↵ers from bulky magnetics with its compromise betweenthe size of passives and the performance. The emerging switched-capacitor (SC) convertershows great potential for a fully integrated solution with the on-die capacitor. However, theintrinsic charge sharing in a SC converter leads to an e�ciency and power density trade-o↵which inhibits its application in the battery powered devices that demands more than a fewwatts. In addition, a SC converter is only e�cient at a discrete conversion ratio determinedby its topology. The voltage regulation over a wide range usually comes at the cost ofe�ciency degradation.

As a way to mitigate the limitation of the inductor-based and switched-capacitor basedconverter, we explore the resonant switched capacitor (ResSC) topology as a hybrid ap-proach. The ResSC topology can utilize the favorable on-die capacitor for tight integrationwhile leveraging a small inductor to eliminate the intrinsic charge sharing. This enableshigher power density without e�ciency compromise along with lossless regulation. Theintroduced inductance is much less than that needed in the common buck/boost converter.

In order to facilitate the design and control of a ResSC converter, the harmonic-balancemethod is adopted for developing its large signal and small signal models. A current-phasebased compensation scheme based on the small signal model is developed to enable a fasttransient response. The e↵ectiveness of topology concept, modeling and control are verifiedby the switched-based simulation in a design example for on-chip power delivery.

i

Contents

Contents i

List of Figures ii

1 Introduction 1

2 Large Signal Model of Resonant Switched Capacitor Converter 32.1 Topology Overview and Principle Operation . . . . . . . . . . . . . . . . . . 32.2 Large Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Small Signal Model and Control Strategy of Resonant Switched Capac-itor Converter 103.1 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Simulation Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Conclusion and Future work 184.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Bibliography 19

ii

List of Figures

2.1 A Ladder Type 2-to-1 Resonant Switched-capacitor DC-DC Converter . . . . . 32.2 (a) Switch Gating Patterns of the ResSC (b) Waveforms of the Tank Voltage,

Inductor Current and Output Current . . . . . . . . . . . . . . . . . . . . . . . 42.3 Di↵erent States of the ResSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.4 Large Signal Phasor Model of the ResSC . . . . . . . . . . . . . . . . . . . . . . 62.5 Steady state operation points with V

in

=2V, ✓ = ⇡/4, Lr

= 1nH, Cr

= 405pF ,R

r

= 25m⌦, Co

= 10nF for (a) Iload

= 500mA and (b) Vout

= 1V . . . . . . . . 9

3.1 Bode Plot of H!!�, H!!v

o

and H!!ki

L

k . . . . . . . . . . . . . . . . . . . . . . 123.2 Small Signal Block Diagram of Close Loop System . . . . . . . . . . . . . . . . 133.3 Open Loop Comparison of Small Signal Model and Switch Based Simulation . . 143.4 Circuit Implementation of the Close Loop Resonant Switch Capacitor Converter 153.5 Waveform of Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.6 Load Transient Comparison of Small Signal Model and Switch Based Circuit

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1

Chapter 1

Introduction

The platform limitation in most portable electronics drives the demand for a compact ande�cient power conversion stage that delivers energy from the Lithium-ion (Li-ion) batteryto multiple functional blocks. The commonly-used buck/boost converter rely on bulky in-ductors which take a large amount of board area. Though increasing switching frequencycan help reduce the size of passives including the inductors, the benefits are limited due toperformance degradation that comes from the increased switching losses.

On the other hand, switched-capacitor (SC) based power converters have shown greatpromise for enabling fully-integrated power management solution, due to the favorable highenergy density of on-chip capacitors [1] [2] [3]. However, the power density in a standardswitched capacitor converter is limited by the available capacitor density of a given technol-ogy, along with the trade-o↵ with e�ciency due to the intrinsic charge sharing loss.

Recently, resonant switched-capacitor (ResSC) based converters have been proposed as anapproach that can mitigate the intrinsic charge-sharing loss in SC operation by introducinga small inductor in series with the flying capacitor [4] [5]. By avoiding charge sharing losses,substantially larger voltage swings can be sustained on the working capacitors, which enablesincreased power density while not compromising e�ciency. Therefore, this approach enablesconverters with higher e�ciency and power density for the fully or near-fully integrateddesigns.

In addition, by strategically designing the switch gating pattern, lossless voltage regula-tion of the ResSC converter can be enabled. To date, some regulation methods have beenproposed for the ResSC converter [6] [7] [8] [9]. By decoupling the phase control of twostacked sections of the ResSC circuit, lossless voltage regulation is enabled [10]. With thismodality, the circuit can best be viewed as a stacked series resonant converter. Thus, the wellknown control methodologies based on frequency tuning, phase-shifting, and/or phase-planecan be brought to bear on the problem. In order to e↵ect nominally lossless zero-voltageswitching, operation above resonance is maintained, in conjunction with properly adjusteddeadtimes. Parasitic capacitances associated with devices, flying capacitor bottom and topplates, and inductor capacitances constitute the contributing components to potential dy-namic switching losses.

CHAPTER 1. INTRODUCTION 2

In order to expand the application of integrated ResSC dc-dc converters to directly bridgethe battery voltage or a high dc bus voltage in the mobile or PC platforms, a stacked topologythat enables higher conversion ratios is also developed [11]. The topology can be extended toany N-to-1 conversion with reduced switch stress, which enables the use of standard CMOStechnology, and only a single inductor. To further reduce voltage ripple or the requiredbypass capacitors, multi-phase interleaving can be employed.

In this thesis, the author develops the framework of designing an analog control basedon the small signal model. The steady state operation of a ladder type 2-to-1 ResSC is firstanalyzed. Operation above resonance is presumed to e↵ect zero voltage switching (ZVS).Based on the generalized averaging method [12], the state space small signal model of theconverter is derived. According to the dynamics of the model, the author further develops acompensation method relying on a phase feedback loop. The switch-based simulations showthe e↵ectiveness of the developed model and proposed regulation scheme.

3

Chapter 2

Large Signal Model of ResonantSwitched Capacitor Converter

In this chapter, we start with the basic operation of a 2-to-1 ResSC converter and apply thegeneralized averaging methods to obtain the large signal model. The large signal model canbe illustrated with the phasor diagrams which facilitate the derivation of the zero voltageswitching (ZVS) conditions for the topology.

2.1 Topology Overview and Principle Operation

Ф1

Cr

Ф1

Ф2

Vin

Co

Lr

Rr

Vout

Iload

SW1

SW2

SW3

SW4

X

Y

iout

iL

vT

Ф2

+

Ci

Figure 2.1: A Ladder Type 2-to-1 Resonant Switched-capacitor DC-DC Converter

A ladder type 2-to-1 resonant switched-capacitor converter is shown in Fig. 2.1. Cr

andLr

form the resonant tank. Ci

and Co

are decoupling capacitors. Rr

represents all the series

CHAPTER 2. LARGE SIGNAL MODEL OF RESONANT SWITCHED CAPACITORCONVERTER 4

A

θ

Ф1

Ф2

B C D A B C D

ωst0 ϖ 2ϖ

vT

iL

iout

Vin

Vout

Iload

ωst

A B C D A B C D

0 ϖ 2ϖ

(a) (b)

Ф1

Ф2

Vin Vout

Figure 2.2: (a) Switch Gating Patterns of the ResSC (b) Waveforms of the Tank Voltage,Inductor Current and Output Current

resistance within the tank which includes the switch resistance, and the ESR of the inductorand capacitors. There are two complementary switch pairs SW1/SW2 and SW3/SW4. Eachswitch pair is driven by a square wave with 50% duty cycle. The switching of SW1/SW2leads that of SW3/SW4 by a phase angle of ✓. Fig. 2.2(a) shows the gating signals for eachswitch. With this switching pattern, the converter has four di↵erent switch states: A, B,C, and D, as shown in Fig. 2.3. Fig. 2.2(b) shows the representative waveforms of the tankvoltage v

T

, the inductor current iL

and the output current iout

, when the converter operatesabove the resonating frequency set by C

r

and Lr

.One benefit of the proposed ResSC operation is that all switches can potentially realize

zero voltage switching (ZVS), which helps to improve converter e�ciency. To achieve that,the tank current i

L

needs to flow into node X and out of node Y before turning SW1 orSW4 on, in which case IL needs to be negative given reference direction defined in Fig. 2.1.Similarly, a positive tank current favors the soft turn-on of both SW3 and SW2. By operatingthe converter under the proposed switching sequence above resonance, all switches can meetthe ZVS requirement.

However, this condition is not true for all possible operation points. In order to benefitfrom the ZVS, the zero crossing of the tank current should be constrained within the intervalset by switching actions of the top switch pair and the bottom switch pair. This leads to anacceptable output range with ZVS for the proposed operation, which will be illustrated inSection 2.2 after the phasor model is introduced.


Cr

Ф1

Ф2

Vin

Ci

Co

Lr

Rr

Vout

Iload

Cr

Ф1

Ф2

Vin

Ci

Co

Lr

Rr

Vout

Iload

Cr

Ф1

Ф2

Vin

Ci

Co

Lr

Rr

Vout

Iload

Cr

Ф1

Ф2

Vin

Ci

Co

Lr

Rr

Vout

Iload

State A State B

State C State D

Ф1

Ф2

Ф1

Ф2

Ф2 Ф2

Ф1 Ф1

+ +

++

Figure 2.3: Di↵erent States of the ResSC

2.2 Large Signal Model

Fig. 2.4(a) shows a simplified circuit model of the resonant converter in Fig. 2.1. Equivalentlywe can view the system as an LCR tank driven by two square waves V

s

and Vo

at nodes Xand Y . Assuming the Q of the tank is high, as enforced by design, we can further simplifythe system by considering only the fundamental sinusoidal components of the square wavesand use phasors to describe the system.

In Fig. 2.4(b)(c)(d),�!VX

and�!VY

represent the fundamental phasors of the two driving

signals vs

and vo

. The magnitudes of�!VX

and�!VY

determined by:

k �!VX

k = 2⇡(V

in

� Vout

)

k �!VY

k = 2⇡Vout

(2.1)

�!VX

leads�!VY

by a fixed phase angle of ✓.�!VT

represents the phasor of the tank voltagewhich is the di↵erence between

�!VX

and�!VY

.�!IL

represents the phasor of inductor current


Re

Im

VX

VY

VT

IL

Re

Im

Vx

VY

VT

IL

Re

Im

VX

VT

IL V

Y

(a)

(b)

(c)

(d)

Cr Lr Rr

vs vo

iLvC

X Y

vT

θ θ

θ

Figure 2.4: Large Signal Phasor Model of the ResSC

which should be perpendicular to the tank voltage phasor under high Q assumption andabove-resonance operation. Phase angle ✓ is a design parameter, selected based on thedesired voltage regulation range, and e�ciency considerations.

As discussed above, in order to benefit from ZVS operation, the zero crossing of thecurrent i

L

should happen between the switching actions of SW1 and SW3. In the phasordomain, this means the tank current phasor

�!iL

should be contained within the phase angleset by phasor

�!VY

and phasor�!VX

.Nominally for a 2-to-1 converter, V

out

equals half of Vin

. In this case,�!VX

and�!VY

have thesame magnitude such that the current phasor is aligned in the middle of the phase angle ✓as shown in Fig. 2.4(b). However, as the output voltage is modulated, the magnitude of

�!VX

and�!VY

adjust. This leads to the movement of the position of the current phasor accordingto the geometrical property of the triangle. As the output voltage decreases, the currentphasor

�!IL

moves closer to�!VX

. Therefore, the minimum output voltage with ZVS occurswhen the tank current is aligned with

�!VX

, as shown in Fig. 2.4(c). Similarly, the case of

maximum output voltage happens when the tank current is aligned with�!VY

, as shown inFig. 2.4(d). From the geometry of the right triangle, the ideal output voltage range withZVS is therefore given by:

Vin

cos ✓

1 + cos ✓< V

out

<Vin

1 + cos ✓(2.2)


We can see that the output range with ZVS can be adjusted by properly choosing ✓.This o↵ers the major benefit of the resonant switched-capacitor converter over conventionalswitched-capacitor converter, since the latter sacrifices e�ciency to achieve the regulation ofthe output voltage. In the design example for V

in

=2V and a 2-to-1 topology, with ✓ = ⇡4 ,the output can be losslessly adjusted from 0.83 to 1.17. As can be seen, a larger angle ✓result in a greater adjustment range, but at the cost of degraded power factor at sendingand receiving nodes with attendant e�ciency costs.

To obtain an analytic expression for the steady state operation, we apply the generalizedaveraging method [12] to the state-space equations of the converter which read:

diL

dt=

1

Lr

[(Vin

� vout

)si

� vout

so

+ vout

� iL

Rr

� vc

]

dvC

dt=

1

Cr

iL

dvout

dt=

1

Co

[so

si

iL

� (1� si

)(1� so

)iL

� Iload

]

(2.3)

where si

and so

represent the switching functions of SW1 and SW3, which take the form:

si

=1

2{sign[sin(!t)] + 1}

so

=1

2{sign[sin(!t� ✓)] + 1}

(2.4)

Applying operator h•i1 to the iL and vC state equations and operator h•i0 to the vout stateequation, we obtain:

dhiL

i1dt

= �j!hiL

i1 +1

Lr

[(Vin

� hvout

i0)hsii1 � hvouti0hsoi1 � hiLi1Rr � hvCi1]

dhvC

i1dt

= �j!hvC

i1 +1

Cr

hiL

i1

dhvout

i0dt

=1

Co

(hso

i�1hiLi1 + hsoi1hiLi�1 + hsii�1hiLi1 + hsii1hiLi1 � Iload)

(2.5)

where h•ik

represent the kth order complex Fourier coe�cient, which is also equivalent tothe phasor transformation in [13]. Using high Q assumption and neglecting the outputvoltage ripple, the first order Fourier coe�cient hi

L

i1 and hvCi1 and the zero order Fouriercoe�cient hv

out

i0, which is real, capture the most significant properties of the tank and theoutput. We then decompose the complex coe�cients into their real and imaginary parts

hiL

i1 =1

2X

i

L

+ j1

2Yi

L

hvC

i1 =1

2X

v

C

+ j1

2Yv

C

(2.6)


where Xi

L

and Yi

L

, Xv

C

and Yv

C

also represent the real and imaginary parts of the resonantinductor current and capacitor voltage in the complex phasor domain.

Applying operator h•i1 to the switching functions, we have:

hsi

i1 = �j1

⇡

hso

i1 = �j1

⇡e�j✓

(2.7)

Then the real-valued fifth order state space equations are obtained:

dXi

L

dt= �Rr

Lr

Xi

L

+ !Yi

L

� 1Lr

Xv

C

+1

Lr

2

⇡sin✓V

out

dYi

L

dt= �!X

i

L

� RrLr

Yi

L

� 1Lr

Yv

C

+1

Lr

2

⇡(1 + cos✓)V

out

� 1Lr

2

⇡Vin

dXv

C

dt=

1

CrX

i

L

+ !Yv

C

dYv

C

dt= �!X

v

C

+1

CrYi

L

dVo

dt=

1

Co

[� 1⇡sin✓X

i

L

� 1⇡(1 + cos✓)Y

i

L

)� Iload

]

(2.8)

To obtain the steady state, we have:

dXi

L

dt= 0

dYi

L

dt= 0

dXv

C

dt= 0

dYv

C

dt= 0

dVo

dt= 0

(2.9)

so that we can solve:

Iload

= � 1⇡

2⇡

!Cr

(1� !2!

2o

)2 + ( !!

o

Q

)2[sin✓(1� !

2

!2o

)Vin

� (1 + cos✓) !!o

Q(V

in

� 2Vo

)] (2.10)

with

!o

=1pLrC

r

Q =

qL

r

C

r

Rr

(2.11)


fsw

/ Hz

285 290 295 300 305 310

Vo

ut/ V

0.4

0.6

0.8

1

1.2

1.4

1.6Vout v.s. Freq

fsw

/ Hz

300 350 400 450 500

I lo

ad/ A

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

Iload

v.s Freq

(a) (b)

Figure 2.5: Steady state operation points with Vin

=2V, ✓ = ⇡/4, Lr

= 1nH, Cr

= 405pF ,R

r

= 25m⌦, Co

= 10nF for (a) Iload

= 500mA and (b) Vout

= 1V

From Eq. 2.10, the operating point of the converter can be uniquely determined givencertain V

in

, ✓. The proposed method uses the switching frequency ! as the tuning parameterfor the output voltage regulation under varying load and set-point commands. The phaseangle is chosen for the expected output range and is not tuned dynamically.

Consider a reasonably achievable design example for the chip-level power delivery ap-plication with L

r

= 1nH,Cr

= 405pF,Rr

= 25m⌦, Co

= 10nF , a set of operating pointsaccording to Eq. 2.10 are plotted in Fig. 2.5. Given certain load condition, modulating fre-quency can regulate the output voltage. In the design example, a 3% frequency change cancover a voltage regulation range of 40%. In terms of load regulation, the frequency range hasto be large enough to support the extreme light load condition. In this case, the e�ciencywill drop due to the increased switching loss. However, to alleviate this scenario, the burstoperation can be introduced to improve the light load e�ciency.

10

Chapter 3

Small Signal Model and ControlStrategy of Resonant SwitchedCapacitor Converter

In this chapter, the small signal model is further developed following the large signal model.The system dynamics are revealed by the transfer functions derived from the small signalmodel. A fast compensation method assisted with the phase information of the current isproposed and validated through the simulation.

3.1 Small Signal Model

To obtain the small signal model, we apply the small signal perturbation to Eq. 2.8 with thestate variables taken as:

xi

L

= Xi

L

+ x̂i

L

yi

L

= Yi

L

+ ŷi

L

xv

C

= Xv

C

+ x̂v

C

yv

C

= Yv

C

+ ŷv

C

vo

= Vo

+ v̂o

(3.1)

and the input variables taken as:

! = ⌦+ !̂

iload

= Iload

+ îload

(3.2)

The output variables that we are interested in are v̂o

, k îL

k and �̂i

L

. With

k îL

k =q(X

i

L

+ x̂i

L

)2 + (Yi

L

+ ŷi

L

)2 �qX2

i

L

+ Y 2i

L

�̂i

L

⇡ �̂i

L

= tan(�i

L

+îL

� �i

L

) =tan�

i

L

+îL

� tan�i

L

1 + tan�i

L

+îL

tan�i

L

(3.3)

CHAPTER 3. SMALL SIGNAL MODEL AND CONTROL STRATEGY OFRESONANT SWITCHED CAPACITOR CONVERTER 11

we can obtain:

k îL

k = XiLx̂iL + YiL ŷiLk iL

k

�̂i

L

=�Y

i

L

x̂i

L

+Xi

L

ŷi

L

k iL

k2(3.4)

Then the real-valued fifth-order small signal state space matrix is obtained as Eq. 3.5.

2

66666664

dx̂

i

L

dt

dŷ

i

L

dt

dx̂

v

C

dt

dŷ

v

C

dt

dv̂

o

dt

3

77777775

=

2

6666664

�RrL

r

⌦ � 1L

r

0 1L

r

2⇡

sin ✓�⌦ �Rr

L

r

0 � 1L

r

1L

r

2⇡

(1 + cos ✓)1C

r

0 0 ⌦ 00 1

C

r

�⌦ 0 0� 1

C

o

1⇡

sin ✓ � 1C

o

1⇡

(1 + cos ✓) 0 0 0

3

7777775

2

6666664

x̂i

L

ŷi

L

x̂v

C

ŷv

C

v̂o

3

7777775+

2

6666664

Yi

L

0�X

i

L

0Yv

C

0�X

v

C

00 � 1

C

o

3

7777775

"!̂

îload

#

2

664

v̂o

ˆk iL

k�̂i

L

3

775 =

2

664

0 0 0 0 1X

i

L

kiL

kY

i

L

kiL

k 0 0 0

� YiLkiL

k2X

i

L

kiL

k2 0 0 0

3

775

2

6666664

x̂i

L

ŷi

L

x̂v

C

ŷv

C

v̂o

3

7777775

(3.5)

For a convenient presentation, Eq.3.5 is rewritten as:2

66666664

dx̂

i

L

dt

dŷ

i

L

dt

dx̂

v

C

dt

dŷ

v

C

dt

dv̂

o

dt

3

77777775

= A

2

6666664

x̂i

L

ŷi

L

x̂v

C

ŷv

C

v̂o

3

7777775+

hB

!

Bi

load

i " !̂îload

#

2

664

v̂o

ˆk iL

k�̂i

L

3

775 =

2

64C

v

o

CkiL

kC

�

3

75

2

6666664

x̂i

L

ŷi

L

x̂v

C

ŷv

C

v̂o

3

7777775

(3.6)

Based on Eq. 3.6, the small signal transfer functions from the switching frequency tothe output voltage magnitude (k H k

!!vo

) and frequency to the resonant current properties(k H k

!!kiL

k and k H k!!�) are evaluated based on:

k H k!!v

o

= Cv

o

(sI�A)�1B!

k H k!!ki

L

k = CkiL

k(sI�A)�1B!k H k

!!� = C�(sI�A)�1B!(3.7)


Magnitude (

dB

)

-250

-200

-150

-100

10-1

100

101

102

103

Phase (

deg)

-720

-360

0

360

Bode Plot of ||H||ω→φBode Plot of ||H||ω→voBode Plot of ||H||ω→||iL||

Frequency (MHz)

fclk

Figure 3.1: Bode Plot of H!!�, H!!v

o

and H!!ki

L

k

Using the design example in Chapter 2 with Lr

= 1nH,Cr

= 405pF,Rr

= 25m⌦, Co

=10nF and according to Eq. 2.10, a set of operating point is given by f

clk

= 300MHz, Vin

=2V, V

out

= 1V, Iload

= 500mA, ✓ = ⇡/4. With the design parameters and the operatingpoint, the Bode plots of the transfer functions are plotted in Fig. 3.1. We can see fromthe Bode plot of H

!!vo

that there is a dominant pole introduced by the output capacitor,contributing a 90� phase lag and magnitude drop, followed by two complex conjugate poles,contributing another 180� phase lag and a large resonant peak in the magnitude responsearound 50MHz. This makes it challenging to do compensation with a pure voltage loop ata high crossover frequency. However, looking at the transfer function of H

!!�, a 180� phaselead, thanks to the complex conjugate zeros at a lower frequency than the resonant poles,is present. Therefore, we take advantage of the phase lead in the current phase transferfunction by adding in a phase loop to stabilize the system as shown in Fig. 3.2. The degreeof compensation can be adjusted by properly choosing respective gains of the phase loop andvoltage loop. Furthermore, a proportion-integral (PI) voltage loop can be used for reductionof the DC error.

3.2 Simulation Verification

To verify the small signal model and proposed control methodology. We implement theconverter and control loop using the switch model based simulator PLECS. The small signal


vref

H ω→voutGvco

i load

H ω→φ

ω

H i load→φ

H i load→vout

vout

φ

Resonant Switched Capacitor Converter

Gph

Gv

^

^

^

^

^

Voltage Loop

Phase Loop

Figure 3.2: Small Signal Block Diagram of Close Loop System

signal dynamics of the converter are verified with the open loop simulation. Fig. 3.3 showsthe dynamic response of the output voltage and current phase under a frequency step of1MHz, we see that circuit simulation match the developed small signal model very well.

In order to implement the phase loop, we use a passive phase sensing scheme as shownin Fig. 3.4. The R

s

and Cs

form a passive lossless current sensor. With the matched timeconstants of R

s

· Cs

and Lr

/Rr

, the voltage across Cs

(Vs

) replicates the voltage drop onthe parasitic resistance of the inductor. Moreover, as the inductor frequency is much higherthan the corner frequency set by L

r

/Rr

, a slight mismatch of the time constants would notresult in any significant error in the phase information captured by V

s

. Vs

is then mixed witha reference clock through an H-bridge. Fig. 3.5 shows the waveform of the reference clock(�3), Vs and Vph. The reference clock (�3) is shifted 90� ahead relative to the middle of thetop (�1) and bottom clock(�2) for high sensitivity. The DC component of the output (Vph)from the mixer approximates the phase error if the phase error is small:

hVph

i0 =k ILRr k2

⇡sin✓ ⇡k I

L

Rr

k 2⇡✓ (3.8)

The scaling e↵ect caused by the current magnitude is accounted for in the gain of Gph

. Thedesign here can be extended as one phase leg of a multi-phase converter.

With the developed small signal mode, a control design with proposed dual loop is pre-


t/µs1.9 2 2.1 2.2 2.3 2.4 2.5

Vout/V

1

1.05

1.1

1.15

1.2Output Voltage

Switch-based Simulation

Small Signal Model

t/µs1.9 2 2.1 2.2 2.3 2.4 2.5

φcurr

ent-φ

clo

ck/r

ad

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6Resonant Current Phase

Switch-based Simulation

Small Signal Model

Figure 3.3: Open Loop Comparison of Small Signal Model and Switch Based Simulation

sented

Gph

(s) = G11

1 + sp

Gv

(s) = G2s+ z

s

(3.9)

where, G1 = 4, G2 =110 , p = 1.01e8, z = 6.28e8. The low pass filter in the phase loop is

used for reducing the high frequency harmonics of the phase error. In a multi-phase system,the low pass filter can be eliminated due to the harmonics cancellation from interleaving.The voltage loop consists of a simple PI controller for the management of DC error. Thegains of phase and voltage loops are selected so that closed-loop sytem is stable and wellcompensated. Fig. 3.6 shows the closed-loop transient response of the voltage output undera 50mA load step. The overshoot and response time from the switch based circuit simulationmatch well with the prediction from the developed small signal model.


Cr

Lr

Rr

VCO

Vref

Ф1

Resonant Switched Capacitor Converter

Phase Deterctor

GphGv

Vout

Vph

Rs

CsVs

Ф2Ф3

Ф1

Ф2

Ф3

Figure 3.4: Circuit Implementation of the Close Loop Resonant Switch Capacitor Converter


θ

Ф1

Ф2

Vx

Vph

ωst

ϖ/2+θ/2

Ф3

Figure 3.5: Waveform of Phase Detector


t/µ s0.4 0.5 0.6 0.7 0.8 0.9

I lo

ad/A

0.4

0.45

0.5

0.55

t/µ s0.4 0.5 0.6 0.7 0.8 0.9

Vo

ut/V

0.95

1

1.05

Switch Based Simulation

Small Signal Model

Figure 3.6: Load Transient Comparison of Small Signal Model and Switch Based CircuitSimulation

18

Chapter 4

Conclusion and Future work

4.1 Conclusion

The thesis introduces the phase shift operation and regulation design for the ResSC converter.After exploring the operating strategies and large signal characteristics of this promisingcircuit, a detailed development of the circuit dynamics has been undertaken using a harmonicaveraging methodology. The method and models developed lead to simple strategies for thecontrol design and implementation.

4.2 Future work

For future, an IC implementation will be taped-out to demonstrate benefits of ResSC con-verter with the proposed operation. Popular 65nm CMOS technology or more advancednodes should be selected for the reasonable switching loss at a few hundreds MHz operatingfrequency. The inductance of a few nH can be realized with the bond-wire or a simple PCBtrace which is promising for a tight integration.

19

Bibliography

[1] S. Sanders, E. Alon, H.-P. Le, M. Seeman, M. John, and V. Ng, “The road to fullyintegrated dc-dc conversion via the switched-capacitor approach,” Power Electronics,IEEE Transactions on, vol. 28, pp. 4146–4155, Sept 2013.

[2] H.-P. Le, S. Sanders, and E. Alon, “Design techniques for fully integrated switched-capacitor dc-dc converters,” Solid-State Circuits, IEEE Journal of, vol. 46, pp. 2120–2131, Sept 2011.

[3] M. Seeman and S. Sanders, “Analysis and optimization of switched-capacitor dc-dcconverters,” Power Electronics, IEEE Transactions on, vol. 23, pp. 841–851, March2008.

[4] K. Kesarwani, R. Sangwan, and J. Stauth, “Resonant switched-capacitor converters forchip-scale power delivery: Modeling and design,” in Control and Modeling for PowerElectronics (COMPEL), 2013 IEEE 14th Workshop on, pp. 1–7, June 2013.

[5] Y. Lei and R. Pilawa-Podgurski, “Analysis of switched-capacitor dc-dc converters insoft-charging operation,” in Control and Modeling for Power Electronics (COMPEL),2013 IEEE 14th Workshop on, pp. 1–7, June 2013.

[6] K. Sano and H. Fujita, “Performance of a high-e�ciency switched-capacitor-based res-onant converter with phase-shift control,” Power Electronics, IEEE Transactions on,vol. 26, pp. 344–354, Feb 2011.

[7] Y. Lei, R. May, and R. Pilawa-Podgurski, “Split-phase control: Achieving completesoft-charging operation of a dickson switched-capacitor converter,” IEEE Transactionson Power Electronics, vol. 31, pp. 770–782, Jan 2016.

[8] K. Kesarwani, R. Sangwan, and J. T. Stauth, “Resonant-switched capacitor convert-ers for chip-scale power delivery: Design and implementation,” IEEE Transactions onPower Electronics, vol. 30, pp. 6966–6977, Dec 2015.

[9] A. Cervera, M. Evzelman, M. Peretz, and S. Ben-Yaakov, “A high-e�ciency reso-nant switched capacitor converter with continuous conversion ratio,” Power Electronics,IEEE Transactions on, vol. 30, pp. 1373–1382, March 2015.

BIBLIOGRAPHY 20

[10] Y. Li, M. John, J. Poon, J. Chen, and S. Sanders, “Lossless voltage regulation andcontrol of the resonant switched-capacitor dc-dc converter,” in Control and Modelingfor Power Electronics (COMPEL), 2015 IEEE 16th Workshop on, pp. 1–7, July 2015.

[11] Y. Li, J. Chen, M. John, R. Liou, and S. R. Sanders, “Resonant switched capacitorstacked topology enabling high dc-dc voltage conversion ratios and e�cient wide rangeregulation,” in 2016 IEEE Energy Conversion Congress and Exposition (ECCE), pp. 1–7, 9 2016.

[12] S. Sanders, J. Noworolski, X. Liu, and G. C. Verghese, “Generalized averaging methodfor power conversion circuits,” Power Electronics, IEEE Transactions on, vol. 6,pp. 251–259, Apr 1991.

[13] C. Rim and G. H. Cho, “Phasor transformation and its application to the dc/ac analysesof frequency phase-controlled series resonant converters (src),” Power Electronics, IEEETransactions on, vol. 5, pp. 201–211, Apr 1990.

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